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shailja
/
fine-tuned-codegen-16B-Verilog
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14
Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
Files
Files and versions
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ea3cbb6
fine-tuned-codegen-16B-Verilog
70 GB
2 contributors
History:
5 commits
shailja
Update README.md
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over 2 years ago
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initial commit
about 3 years ago
README.md
4.56 kB
Update README.md
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added_tokens.json
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about 3 years ago
config.json
1.01 kB
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about 3 years ago
fine-tuned-codegen-16B-4gpu.tar.zst
37.8 GB
xet
uploading 16B Verilog LLM
about 3 years ago
latest
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merges.txt
456 kB
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pytorch_model.bin
32.2 GB
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rng_state_0.pth
14.5 kB
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rng_state_1.pth
14.5 kB
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rng_state_2.pth
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special_tokens_map.json
99 Bytes
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tokenizer.json
2.11 MB
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tokenizer_config.json
283 Bytes
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trainer_state.json
849 Bytes
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training_args.bin
4.72 kB
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about 3 years ago
vocab.json
798 kB
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zero_to_fp32.py
18.9 kB
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