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shailja
/
fine-tuned-codegen-16B-Verilog

Text Generation
Transformers
PyTorch
codegen
code
Eval Results
Model card Files Files and versions
xet
Community
3
fine-tuned-codegen-16B-Verilog
70 GB
  • 2 contributors
History: 5 commits
shailja's picture
shailja
Update README.md
ea3cbb6 over 2 years ago
  • .gitattributes
    1.48 kB
    initial commit about 3 years ago
  • README.md
    4.56 kB
    Update README.md over 2 years ago
  • added_tokens.json
    1.08 kB
    uploaded model about 3 years ago
  • config.json
    1.01 kB
    uploaded model about 3 years ago
  • fine-tuned-codegen-16B-4gpu.tar.zst
    37.8 GB
    xet
    uploading 16B Verilog LLM about 3 years ago
  • latest
    15 Bytes
    uploaded model about 3 years ago
  • merges.txt
    456 kB
    uploaded model about 3 years ago
  • pytorch_model.bin
    32.2 GB
    xet
    uploaded model about 3 years ago
  • rng_state_0.pth
    14.5 kB
    xet
    uploaded model about 3 years ago
  • rng_state_1.pth
    14.5 kB
    xet
    uploaded model about 3 years ago
  • rng_state_2.pth
    14.5 kB
    xet
    uploaded model about 3 years ago
  • special_tokens_map.json
    99 Bytes
    uploaded model about 3 years ago
  • tokenizer.json
    2.11 MB
    uploaded model about 3 years ago
  • tokenizer_config.json
    283 Bytes
    uploaded model about 3 years ago
  • trainer_state.json
    849 Bytes
    uploaded model about 3 years ago
  • training_args.bin
    4.72 kB
    xet
    uploaded model about 3 years ago
  • vocab.json
    798 kB
    uploaded model about 3 years ago
  • zero_to_fp32.py
    18.9 kB
    uploaded model about 3 years ago