ANALYSIS, COMPUTER SIMULATION, AND PROPERTIES OF SEMICONDUCTOR DYNAMIC MEMORIES FOR VLSI IMPLEMENTATION (DRAM, MEMORY DESIGN, SEMICONDUCTOR)
As overall dynamic random-access memory capacity and performance continue to increase and improve, innovation is keeping pace to make basic cells smaller, faster, more reliable, and simpler. Two novel bipolar dynamic random-access memory (B-dRAM) cells are proposed, investigated, and analyzed. One cell incorporates three diodes in a composite structure and the other employs an npn transistor and a diode. Each of the basic cells consists of the junction capacitor, where data is stored in the form of charge, and the switching devices acting as a transfer gate. An open bit line organized array of cells is proposed with a simple sense/latch scheme and a dummy cell employed as a reference potential. This array organization can double the basic cells per sense/latch circuit as compared with a single-ended sense scheme.^ For the completeness of this thesis, the development of metal-oxide semiconductor field effect transistor (MOSFET) and of bipolar dynamic random-access memories are reviewed with emphasis on the memory basic cell structures in terms of cross-sectional and equivalent circuit view points, and including the sense/latch amplifier. A projected trend in the scalability of future dRAM's is discussed based on the available data. Finally, some candidates which have been proposed for memory cells of future dRAM's are discussed. ^
Engineering, Electronics and Electrical
YEUN CHEUL JEUNG,
"ANALYSIS, COMPUTER SIMULATION, AND PROPERTIES OF SEMICONDUCTOR DYNAMIC MEMORIES FOR VLSI IMPLEMENTATION (DRAM, MEMORY DESIGN, SEMICONDUCTOR)"
Dissertations and Master's Theses (Campus Access).