|Publication number||US7117280 B2|
|Application number||US 09/750,198|
|Publication date||Oct 3, 2006|
|Filing date||Dec 27, 2000|
|Priority date||Dec 27, 2000|
|Also published as||US20040225805|
|Publication number||09750198, 750198, US 7117280 B2, US 7117280B2, US-B2-7117280, US7117280 B2, US7117280B2|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (22), Classifications (18), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention generally concerns computer architectures, and in more particular concerns an architecture that provides intra-device interfacing via network-like messaging.
2. Background Information
A typical computer includes a main board or motherboard that includes one or more processors and provides various hardware interfaces for connecting peripheral devices to the motherboard. For example, personal computers (PCs) generally include a set of expansion “slots” into which peripheral cards can be inserted to provide certain functions, such as video, network interfacing, modem, auxiliary disk control, etc. Under conventional architectures, communication between the processor and the peripheral cards is enabled through a communications bus, such as the PCI bus or ISA bus. Accordingly, software application programs can communicate with peripheral devices through either direct system calls (e.g., direct writes or reads from memory) or through calls made to an operating system, which then will pass or retrieve the desired data either directly or through a device driver.
There are several problems with the conventional architecture. For example, some multiprocessor computer architectures do not enable peripheral devices to be shared between the processors, in a manner that scales across computers. Other multiprocessor architectures that allow such sharing present bus contention problems that may restrict access to the peripheral devices. Another problem with conventional architectures, such as the PCI bus, is that the bus speeds are insufficient to take advantage of higher-bandwidth communication links (e.g., present Gigabit/sec Ethernet networks and future 10 Gigabit/sec networks.
Another problem is security; configuration information can often be easily changed such by unauthorized users that the resource conflicts or other problems arise. For example, conventional bus architectures do not have any built-in security measures. As a result, unauthorized users may delete or corrupt bus and/or resource configuration information. This problem is exacerbated by today's distributed environment, wherein changes on one machine may adversely effect other machines connected to the network.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The present invention provides an architecture scheme that enables communication between application programs and internal peripheral devices through use of network-like messaging. Through application of both software and hardware interfaces, an application and a peripheral device are enabled to establish a connection using standard network protocols and communication standards, such as TCP/IP over an Ethernet.
Software portion 12 comprises three layers, including an application layer 18, as depicted by an application, a socket API (application program interface) layer 20, and a network interfaces abstraction layer 22, also referred to herein as a data link layer. Application layer 18 may optionally include an operating system 19. Application programs running in application layer 18 are enabled to access various hardware devices through use of socket API's corresponding to those devices operating in socket API layer 20 (as depicted by a video subsystem socket API 24, a external network socket API 26, and an storage subsystem API 28), and logical to physical device interface mapping provided by network interface abstraction layer 22.
Hardware layer 14 includes a CPU 30, a video subsystem 32, a memory subsystem 34, a network subsystem 36, a storage subsystem 38, and other peripheral subsystems 40. As used herein, the function of each subsystem may typically be performed by a corresponding “peripheral device.” The subsystems are connected to CPU 30 via respective network interfaces (I/F) 42, 44, 46, 48, and 50, each of which is connected to a network 52. In addition, CPU 30 may be connected to an external network 56 via network subsystem 36, an external network interface 58, and network interface 46.
Each of network interfaces 42, 44, 46, 48, and 50 may reside on the same board or within the same device housing as their corresponding subsystem or peripheral device, or may be disposed apart from their corresponding subsystem, with a communications link between the two. For example,
Some or all of the cards may be connected to communications link 66 via a respective network connector using standard network cabling. Optionally, some or all or the cards may be connected via a standard or auxiliary edge connector and corresponding slot 65 to network bus 67.
As discussed above, in some instances it may be desired to connect to one or more peripheral devices that are located outside of the computer, such as an external peripheral device 88. This can be accomplished in a similar manner as internal peripheral devices by implementing an appropriate network interface for the external peripheral device, as exemplified by a network interface 89.
Communications link 66 and network bus 67 preferably are implemented using a network communications standard. For example, communications link 66 or network bus 67 may comprise an Ethernet subnet, a token ring, or an FDDI (Fiber Distributed Data Interface) subnet. Applicable standards for Ethernet systems are provided by the IEEE 802.3 standards group. Preferably, an Ethernet implementation will support the Gigabit Ethernet standard (1000 Base ×), although the Fast Ethernet standard (100 BaseT) may also be used
One advantage with architecture 10 is that it is easily scalable. For example, the scheme may be used to enable a plurality of processors to share peripheral devices. This is depicted in
A flowchart illustrating the logic used by the invention in providing communication between a processor and a peripheral device is shown in
wherein network is the four-byte network address, node is the six-byte card address, and port is two bytes identifying the program or process. Accordingly, creating a socket binds an object (i.e., the processor or peripheral device) to an address that is used for communicating with the object. These addresses enable objects connected to the network to be referenced as network “nodes.”
Sockets may generally be created via operating system 19 and/or communication drivers for processor and any peripheral devices that are to be accessed via the internal network in the system. In addition, some peripheral devices may automatically create a socket when they are initially powered up.
In a block 94, a connection is established between the processor and the peripheral device using an appropriate network transmission protocol, such as TCP/IP or UDP, or any other standard network transmission protocols, each of which are well-known in the art. Once a connection has been established, messages can be sent between the processor and the peripheral device using the selected network transmission protocol.
Another advantage of the present architecture is that built-in network facilities, such as security measures, may be used without requiring such facilities to be built into applications or into the peripheral devices themselves. Accordingly, such network security measures may optionally be applied to the connection, as provided by a block 98. At the conclusion of the communication between the processor and the peripheral device the channel preferably is closed in a block 100.
With reference to
The above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. Accordingly, it is not intended that the scope of the invention in any way be limited by the above description, but instead be determined entirely by reference to the claims that follow.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6009480 *||Sep 12, 1997||Dec 28, 1999||Telxon Corporation||Integrated device driver wherein the peripheral downloads the device driver via an I/O device after it is determined that the I/O device has the resources to support the peripheral device|
|US6067407 *||Jun 30, 1995||May 23, 2000||Canon Information Systems, Inc.||Remote diagnosis of network device over a local area network|
|US6311165 *||Jan 12, 1999||Oct 30, 2001||Ncr Corporation||Transaction processing systems|
|US6324608 *||Oct 1, 1997||Nov 27, 2001||Micron Electronics||Method for hot swapping of network components|
|US6370599 *||Sep 7, 2000||Apr 9, 2002||Microsoft Corporation||System for ascertaining task off-load capabilities of a device and enabling selected capabilities and when needed selectively and dynamically requesting the device to perform the task|
|US6456632 *||Aug 27, 1998||Sep 24, 2002||Robert T. Baum||Protocol separation in packet communication|
|US6529978 *||Feb 23, 2000||Mar 4, 2003||International Business Machines Corporation||Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings|
|US20020004898 *||Apr 24, 2001||Jan 10, 2002||Droge John C.||System and method for highly secure data communications|
|US20020083228 *||Dec 21, 2000||Jun 27, 2002||Chiloyan John H.||Method and system to access software pertinent to an electronic peripheral device at an address based on a peripheral device identifier|
|US20030067884 *||Nov 13, 2002||Apr 10, 2003||Abler Joseph Michael||Dynamic detection of LAN network protocol|
|US20040008709 *||Feb 4, 1999||Jan 15, 2004||Saul Joseph Einbinder||Port prioritizing device|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7903642 *||Dec 4, 2007||Mar 8, 2011||Nokia Corporation||Multi-processor architecture for a device|
|US7921046||Apr 5, 2011||Exegy Incorporated||High speed processing of financial information using FPGA devices|
|US7954114||Jan 26, 2006||May 31, 2011||Exegy Incorporated||Firmware socket module for FPGA-based pipeline processing|
|US8407122||Mar 31, 2011||Mar 26, 2013||Exegy Incorporated||High speed processing of financial information using FPGA devices|
|US8458081||Mar 31, 2011||Jun 4, 2013||Exegy Incorporated||High speed processing of financial information using FPGA devices|
|US8478680||Mar 31, 2011||Jul 2, 2013||Exegy Incorporated||High speed processing of financial information using FPGA devices|
|US8595104||Mar 31, 2011||Nov 26, 2013||Ip Reservoir, Llc||High speed processing of financial information using FPGA devices|
|US8600856||Mar 31, 2011||Dec 3, 2013||Ip Reservoir, Llc||High speed processing of financial information using FPGA devices|
|US8626624||Mar 31, 2011||Jan 7, 2014||Ip Reservoir, Llc||High speed processing of financial information using FPGA devices|
|US8655764||Mar 31, 2011||Feb 18, 2014||Ip Reservoir, Llc||High speed processing of financial information using FPGA devices|
|US8751452||Jan 6, 2012||Jun 10, 2014||Ip Reservoir, Llc||Intelligent data storage and processing using FPGA devices|
|US8762249||Jun 7, 2011||Jun 24, 2014||Ip Reservoir, Llc||Method and apparatus for high-speed processing of financial market depth data|
|US8768805||Jun 7, 2011||Jul 1, 2014||Ip Reservoir, Llc||Method and apparatus for high-speed processing of financial market depth data|
|US8768888||Jan 6, 2012||Jul 1, 2014||Ip Reservoir, Llc||Intelligent data storage and processing using FPGA devices|
|US8776050 *||Oct 25, 2004||Jul 8, 2014||Oracle International Corporation||Distributed virtual machine monitor for managing multiple virtual resources across multiple physical nodes|
|US9047243||Apr 5, 2012||Jun 2, 2015||Ip Reservoir, Llc||Method and apparatus for low latency data distribution|
|US9176775||Jun 26, 2014||Nov 3, 2015||Ip Reservoir, Llc||Intelligent data storage and processing using FPGA devices|
|US20050044301 *||Apr 26, 2004||Feb 24, 2005||Vasilevsky Alexander David||Method and apparatus for providing virtual computing services|
|US20050120160 *||Oct 25, 2004||Jun 2, 2005||Jerry Plouffe||System and method for managing virtual servers|
|US20090141654 *||Dec 4, 2007||Jun 4, 2009||Nokia Corporation||Multi-Processor architecture for a device|
|US20100098081 *||Sep 24, 2009||Apr 22, 2010||Sarang Dharmapurikar||Longest prefix matching for network address lookups using bloom filters|
|US20100257247 *||Apr 7, 2010||Oct 7, 2010||Global Velocity, Inc.||Real time content matching|
|U.S. Classification||710/100, 370/352, 710/301, 710/302, 709/250, 710/305, 710/303, 710/304|
|International Classification||G06F13/00, G06F13/40, G06F13/38, H04L29/06|
|Cooperative Classification||H04L69/16, H04L69/162, H04L63/10|
|European Classification||H04L29/06J3S, H04L63/10, H04L29/06J|
|Dec 27, 2000||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VASUDEVAN, ANIL;REEL/FRAME:011411/0709
Effective date: 20001227
|Mar 31, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Mar 20, 2014||FPAY||Fee payment|
Year of fee payment: 8