|Publication number||US7350015 B2|
|Application number||US 10/285,046|
|Publication date||Mar 25, 2008|
|Filing date||Oct 31, 2002|
|Priority date||Oct 31, 2001|
|Also published as||DE50114373D1, EP1308846A1, EP1308846B1, US20030084226|
|Publication number||10285046, 285046, US 7350015 B2, US 7350015B2, US-B2-7350015, US7350015 B2, US7350015B2|
|Inventors||Jens Barrenscheen, Gunther Fenzl, Peter Rohm|
|Original Assignee||Infineon Technologies Ag|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (39), Referenced by (4), Classifications (13), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a data transmission device that forwards data, which have been received from a first device, to a second device.
Such data transmission devices are, by way of example, DMA controllers or bus bridges contained, by way of example, in program-controlled units such as microprocessors, microcontrollers, signal processors, etc.
DMA controllers and bus bridges are devices connected to a data bus (DMA controllers) and devices provided between two data buses (bus bridges) which provide efficient transfer of data between further devices connected to the bus or to the buses, more precisely transfer of data which takes place without any relatively high level of loading on a CPU of a program-controlled unit.
The configuration, operation and advantages of use of DMA controllers and bus bridges are known, and therefore there is no need to describe further details.
The fact that modern program-controlled units require transmission of ever greater volumes of data in ever shorter times via the data buses connecting the components of the program-controlled unit to one another results in that, even if DMA controllers and bus bridges are provided, increasingly great difficulties arise in transmitting the data to be transferred with a low level of involvement quickly, easily and efficiently.
To be able to transfer relatively large volumes of data efficiently, in particular with the lowest possible level of loading on the CPU, it is possible to:
These measures require a high level of involvement, however, and also result in the chip in question becoming large and expensive.
It is accordingly an object of the invention to provide a data transmission device that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which transmits large volumes of data quickly and efficiently with a low level of involvement.
With the foregoing and other objects in view there is provided, in accordance with the invention, a data transmission apparatus for forwarding data received from a first device, intended for a second device, to the second device. The data transmission apparatus contains a data transmission device for receiving and outputting the data. The data transmission device has connections for connecting to at least two data buses, including a first data bus and a second data bus. The data transmission device outputs the data received from the first data bus onto the first data bus or the second data bus immediately or later in time.
In accordance with an added feature of the invention, the data transmission device operates such that the data intended for the second device are selectively only partially forwarded to the second device or not forwarded to the second device.
In accordance with an additional feature of the invention, the data transmission device changes the data intended for the second device before the data are forwarded to the second device.
In accordance with another feature of the invention, the data transmission device operates such that, instead of the data intended for the second device, other data are output to the second device.
In accordance with a further feature of the invention, the data transmission device operates such that the data intended for the second device are forwarded to a further device and to the second device.
In accordance with another added feature of the invention, the data transmission device operates such that a reception of the data from the first device, a fetching of the data from the first device, and/or the forwarding of the data to the second device are ended if the data contain particular data or a particular data sequence.
In accordance with an another additional feature of the invention, the data transmission device operates such that a size of units of the data received and fetched from the first device and a size of units of the data which the data transmission device forwards to the second device can be stipulated independently of one another.
In accordance with another further feature of the invention, the data transmission device is configured to forward to the second device the data output by the first device following an appropriate request from the data transmission device and the data output by the first device is done under an influence of the first device.
In accordance with a concomitant feature of the invention, the data transmission device operates such that the data intended for the second device are forwarded only to a further device.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a data transmission device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
The data transmission device described below is part of a microcontroller in the example under consideration. Alternatively, it could be part of another program-controlled unit, such as a microprocessor or a signal processor, and could also be part of any other device or could be an independent unit without any further parts.
In the example under consideration, the microcontroller, part of which is the data transmission device, contains, besides the data transmission device, one or more CPUs, one or more memories and one or more peripheral units, such as an A/D converter, a D/A converter, a timer, a CAN controller, a USB controller, an OCDS module, etc. For the sake of completeness, it will be noted that the microcontroller can also contain more, fewer or any other components.
The components of the microcontroller are connected to one another via one or more buses. As described in more detail below, the data transmission device can be connected to one or more buses and can be used as a DMA controller or as a bus bridge, or can be used simultaneously or alternately as a DMA controller and as a bus bridge, and can additionally even undertake other tasks which will be discussed in even more detail at a later point.
Referring now to the figures of the drawing in detail and first, particularly, to
In the configuration shown in
In the configuration shown in
When the data transmission device DTU is used as a DMA controller, it can transmit data from one of the devices connected to the bus BUS1 to another of the devices connected to the bus BUS1 or to a device connected to the bus BUS2 autonomously, i.e. particularly without the assistance of the CPU, upon an appropriate request by one of the components of the microcontroller, or can transmit data from one of the devices connected to the BUS2 to another of the devices connected to the bus BUS2 or to a device connected to the bus BUS1. An example of this is shown in
When the data transmission device DTU is used as a bus bridge, it can transfer data that a device connected to one of the buses outputs onto one bus from one bus to the other bus in order to transmit the data to a device connected to the other bus. An example of this is shown in
It ought to be clear that the data transmission device can also be connected to more than two buses.
In the configuration shown in
The text below describes the configuration of the data transmission device DTU shown in
In line with
The task of the data transmission device DTU is to forward data that are received from a first device and are intended for a second device to the second device.
The data which the data transmission device DTU needs to transmit between devices connected to the buses are read in via one of the bus interfaces BIx and are immediately or later (following buffer-storage in the buffer store IM) output via the same or a different bus interface BIx. Data are written to the buffer store IM, and data stored in the buffer store IM are read, under the control of the buffer-store control device IMCx, which is associated with the bus interface BIx which receives the data to be transferred from the associated bus, and the buffer-store control device IMCy, which is associated with the bus interface BIy which outputs the data to be transferred onto the associated bus.
Each bus interface BI1 to BI4 and/or the buffer-store control devices IMC1 to IMC4 associated therewith are also able to undertake further functions. In the example under consideration, these functions involve:
The bus interfaces BI1 to BI4 and/or the buffer-store control devices IMC1 to IMC4 can be configured by the central control unit CCU on the basis of the respective data transfer to be performed. The configuration data used for the configuration are stored in the configuration data memory CDM and are read therefrom when required by the central control unit CCU, and/or supplied to the data transmission device DTU externally (via one of the buses, for example), and/or generated by the central control unit CCU itself.
The configuration data memory CDM stores a plurality of configuration data records for configuring the bus interfaces BI1 to BI4 and/or the buffer-store control devices IMC1 to IMC4. The configuration data record that is to be used for configuration is selected on the basis of the respective data transfer to be performed. The configuration data record to be used is selected, and the data transmission device components to be configured are configured, by the central control unit CCU. This unit reads the configuration data record to be used from the configuration data memory CDM and configures the data transmission device components to be configured using these data.
Each configuration data record contains the configuration data that need to be used to configure the bus interface BI1 to BI4 and the buffer-store control devices IMC1 to IMC4 so that the respective data transfer to be performed is performed correctly. In the example under consideration, each configuration data record stipulates:
It ought to be clear and require no further explanation that the stipulations made by the configuration data can also cover more, fewer and/or other stipulations or combinations of those mentioned above.
In the example under consideration, the buffer store IM is a first-in-first-out (FIFO) memory, but can in principle also be a memory organized in any other way.
The arbitration logic AL is connected to input connections TR1 to TR32 on the data transmission device DTU which are used to signal to the data transmission device DTU that a particular DMA transfer needs to be performed, and the arbitration logic decides the order in which the requested DMA transfers are performed.
When required, the interrupt generation device IGU generates an interrupt request signal that signals particular circumstances, such as, in particular, when a requested DMA transfer has been performed or an error that has occurred.
As already mentioned above, the data transmission device DTU can be used selectively, alternately or simultaneously as a DMA controller and/or as a bus bridge.
The text below first describes the use of the data transmission device DTU as a DMA controller.
When one of the components in the microcontroller wishes to prompt a DMA transfer, it signals this to the data transmission device DTU by transmitting a signal which has a particular level and is referred to as a transfer request signal below to one of the input connections TR1 to TR32 on the data transmission device DTU.
The transfer request signal passes from the input connection to which it is supplied into the arbitration logic AL, which uses information which is stored in it and can be changed from outside of the data transmission device DTU in order to ascertain the priority of the requested transfer request and, on the basis of this, stipulates which of the DMA transfers which have already been requested but which have not yet been performed needs to be performed next. The transfer request having the highest associated priority, more precisely a transfer request number that indicates which of the input connections TR1 to TR32 was used to request the transfer request in question, is forwarded to the central control unit CCU. The central control unit CCU reads the configuration data record associated with the transfer request number from the configuration data memory CDM and uses the data to configure the data transmission device components that need to be configured.
It is then possible to start performing the requested DMA request. To this end, the data transmission device DTU first requests allocation of the bus or buses that it needs in order to perform a DMA request. When the data transmission device DTU has been allocated the necessary bus or buses, it executes the DMA request to be executed in the manner prescribed by the preceding configuration.
Provision can also be made for the data transmission device DTU first to request, read in and buffer-store only the data which are to be transferred, but not to start forwarding them until external signaling has indicated to it that it may do so.
If various buses (and hence also various bus interfaces BIx) are required for a plurality of DMA transfers, this plurality of DMA transfers can also be executed simultaneously.
Particularly when there is a relatively large number of DMA transfers which have been requested but not yet executed, it may be found to be advantageous if the DMA transfers are at least temporarily executed not strictly in accordance with the order of their associated priorities, but rather while merely or additionally taking into account the criterion that the greatest possible number of DMA transfers is executed simultaneously in each case.
As can be seen from the above explanations, a single data transmission device of the type described above can execute DMA transfers between any components in the microcontroller, particularly including between those connected to different buses.
If it were desirable to achieve this using conventional DMA controllers, a total of four DMA controllers (1 DMA controller per bus) would need to be provided in the example under consideration, and also the plurality of buses would need to be connected via bus bridges or the like, to which end, if each bus needs to be connected to every other bus via a bus bridge, a total of six bus bridges would need to be provided.
The data transmission device DTU described is therefore found to be advantageous when it is configured or used “just” for carrying out DMA transfers.
For the sake of completeness, it will be noted that the transfer request signal and/or the configuration data to be used for the DMA transfer could also be written to appropriate function registers in the data transmission device DTU.
If the data transmission device DTU is additionally to be used as a bus bridge, it performs the actions described below. Before continuing, it will be pointed out that the data transmission device can also be used exclusively as a bus bridge; in this case, the input connections TR1 to TR32 and the arbitration logic AL can be dispensed with.
When the data transmission device DTU is used as a bus bridge the data transmission device DTU continually evaluates the data transmitted via the buses BUS1 to BUS4 in order to check whether a device which is connected to one of the buses BUS1 to BUS4 currently wishes to transmit data to a device which is connected,to another bus, and if this is the case, it transfers the data to be transmitted from one bus to the other bus.
The check on whether a device connected to one of the buses BUS1 to BUS4 currently wishes to transmit data to a device connected to another bus is made by the central control unit CCU. This unit receives from the bus interfaces BI1 to BI4 the data transferred via the buses BUS1 to BUS4 and can establish therefrom whether a device connected to one of the buses BUS1 to BUS4 currently wishes to transmit data to a device connected to another bus.
The check is made by checking whether the address of the device to which data need to be transmitted is the address of a device that is not connected to the same bus as the device outputting the data. To this end, the data transmission device DTU stores the addresses of the devices that are associated with the devices connected to the respective buses. These addresses can be written to the data transmission device DTU, or changed as desired, from outside the data transmission device DTU, more precisely by the CPU or another component in the microcontroller.
If the data transmission device DTU establishes that the device outputting the data and the device for which these data are intended are connected to different buses, it ascertains to which buses the devices in question are connected and configures the bus interfaces BIx connected to these buses and/or the buffer-store control devices IMCx associated with the bus interfaces such that the data to be transferred are forwarded correctly from one bus to the other bus.
The data used to configure the bus interfaces BIx and/or the buffer-store control devices IMCx associated therewith are read from the configuration data memory CDM taking into account the devices or the buses between which data need to be transferred, or are generated by the central control unit CCU itself.
When the bus interfaces BIx and/or the buffer-store control devices IMCx associated therewith have been configured, the data originating from the device outputting the data are accepted from one of the bus interfaces and are immediately or later (following buffer-storage in the buffer store IM) forwarded by the other bus interface to the device for which the data are intended; before the data are forwarded, the bus interface forwarding the data needs to request and be allocated the bus associated with it.
If devices connected to different buses simultaneously wish to transmit data to devices which are connected to various other buses, the data transmission device DTU can transfer the data from one respective bus to the other respective bus simultaneously as well. This makes it possible, for example, for the data transmission device to transfer data from a first bus to a second bus and simultaneously to transfer data from a third bus to a fourth bus, or to transfer data from a first bus to a second bus and simultaneously to read in and buffer-store data to be transferred to the first bus from a third bus, or to output data which have previously been read in and buffer-stored from the third bus onto the first bus, and simultaneously to transfer data from a third bus to a fourth bus.
As explained above, a single data transmission device of the type described above can replace a plurality of bus bridges; if the four buses BUS1 to BUS4 to which the data transmission device shown in
The data transmission device described can also simultaneously be active as a bus bridge and as a DMA controller. This makes it possible, by way of example, for the data transmission device to act as a bus bridge between a first bus and a second bus (to transfer data between these buses) and simultaneously to perform a DMA transfer between two devices connected to a third bus.
The fact that the data transmission device described can simultaneously or alternately transfer data between components of the microcontroller which are connected to the same bus and data between components of the microcontroller which are connected to different buses makes it an extremely simple matter to distribute the components of the microcontroller which are to be connected to one another over a plurality of buses without putting up with drawbacks.
The large number of ways in which it is possible to match the data transmission device to the particular features of the buses connected thereto allow the buses to be operated entirely independently of one another. In particular, they can have different data transmission rates and can operate using different data transmission protocols.
Connecting the components of the microcontroller that are to be connected to one another via a plurality of buses makes it possible for the volume of data which needs to be transferred via each individual bus to be smaller than would be the case if the components of the microcontroller were connected to one another via a single bus, which results in that the time (the latency) which a component needing the bus needs to wait before it can use the bus becomes shorter, and for each of the buses to be able to be relatively short, which results in that they can use a higher data transmission rate than would be the case if the components of the microcontroller were connected to one another just via a single bus.
In this case, provision can also be made for the data transmission device to be the only unit on one or more buses that is able to be bus master on the bus or buses in question.
On the basis of all of this, the data transmission device described is found to be advantageous in a wide variety of respects.
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|U.S. Classification||710/311, 710/316, 710/308, 710/27, 710/310, 710/106|
|International Classification||G06F13/28, G06F13/36, G06F13/40|
|Cooperative Classification||G06F13/28, G06F13/4027|
|European Classification||G06F13/40D5, G06F13/28|
|Dec 24, 2007||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BARRENSCHEEN, JENS;FENZL, GUNTHER;ROHM, PETER;REEL/FRAME:020286/0166
Effective date: 20021113
|Sep 12, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Sep 9, 2015||FPAY||Fee payment|
Year of fee payment: 8