Hillsboro, Ore.—Lattice Semiconductor promotes its ispPAC-POWR1220AT8, the first chip in its second generation Power Manager II devices, as a complete power management solution that provides an optimized set of programmable digital and analog functions for Advanced Telecom Computing Architecture (ATCA) applications and the like.
"Our Power Manager devices were introduced in 2003,"
said Stan Kopec, vice president of corporate marketing.
"Our second generation Power Manager II devices (which add power supply margining, trimming and sequencing), in addition to integrating all power supply management functions into one chip, provide more precise monitoring and more accurate voltage control, and that improves system reliability. For example, the1220AT8 device can act as a coprocessor to an IPMC (intelligent platform management controller) in an AdvancedTCA FRU (field replaceable unit). The sequence control intelligence built into the on-chip CPLD can interrupt the processor under fault conditions, reducing the processing load on the IPMC."
The ruggedized POWR1220AT8 integrates a 48 macrocell complex programmable logic device (CPLD), dual precision voltage monitoring comparators with an accuracy of 0.5 percent, 10-bit A/D converter for voltage measurements, and eight 8-bit D/A converters for trimming power supplies. The chip's integrated I2C interface enables a microcontroller to read the status of all the comparators (inputs and outputs) as well as control the power supply voltage level across its entire operating range. Additionally, the controller can measure both locally generated voltages and current levels. Analog features such as input comparator thresholds and digital functions such as supply control sequences are programmed into non-volatile E2CMOS elements using an IEEE1149.1 protocol.
The ispPAC POWR1220AT8 device margin-and-trim block (MTB) provides a flexible mechanism for both setting and maintaining the output voltage of a power supply to within 1 percent of its set value for trimming as well as the ability to vary a power supply voltage to ±5 percent of its target value for margining. The MTB consists of eight TrimCells to simultaneously control the power supply voltages of up to eight supplies. Each TrimCell has an 8-bit DAC and six DAC registers for margining and trimming flexibility. A digital closed-loop circuit maintains tight accuracy of the trimmed voltage across operating temperature, load, and age of the power supply. The TrimCell also can store 4 different DAC code settings or configurations that can easily be selected using hardware pins dedicated to selecting the voltage profile.
Users implement ispPAC-POWR1220AT8 designs with the company's Windows-based PAC-Designer Software version 4.0. Its embedded LogiBuilder software module supports the implementation of multiple control sequence algorithms: For example, microcontroller command response, and Payload power management and AMC management required in ATCA applications. The margin-and-trim macro embedded in PAC-Designer 4.0 automatically determines the resistor network for a given power supply based on the required output voltage. The package has an intuitive design flow, and users can learn its operation and complete designs in minutes.
The device datasheet can be secured by clicking here. The ispPAC-POWR1220AT8, in a 100-pin TQFP package, is priced at $5.50 each in 10k pieces. Samples are available now. The PAC-Designer 4.0 software is available as a download free of charge from the company website.
Lattice Semiconductor Corporation, 1-503-268-8000, www.latticesemi.com