|Publication number||US7676775 B2|
|Application number||US 11/754,947|
|Publication date||Mar 9, 2010|
|Filing date||May 29, 2007|
|Priority date||May 29, 2007|
|Also published as||US20080301597|
|Publication number||11754947, 754947, US 7676775 B2, US 7676775B2, US-B2-7676775, US7676775 B2, US7676775B2|
|Inventors||Howard Chen, Katherine V. Hawkins, Fook-Luen Heng, Louis Hsu, Xu Ouyang|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (12), Classifications (14), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to testing of semiconductor circuits. More particularly, the present invention relates to a method and system of determining the root causes of fail patterns by utilizing the spatial correlation information of fail patterns and the layout information of the circuits.
One of the main methods of improving circuit yield during the development or manufacturing of integrated circuits is to study the fail patterns uncovered by a tester used to test a given integrated circuit. If fail patterns could be used to disclose important information about their root causes or the nature of the defects, corrective actions could then be taken to improve the yield, based on the knowledge of such defects gained from such analysis, either from the process side or the design side.
Existing methods for analyzing semiconductor fail patterns are developed from the memory bit fail maps. Unlike logic circuits, memory chips can easily provide the exact X, Y coordinates of each memory cell. Therefore, memory chips have been used more extensively in fail pattern analysis than logic circuits. One example of a yield analysis tool is disclosed in U.S. Pat. No. 6,564,346. Although fail patterns from the tester data of memory circuits are searched, classified and analyzed, each fail pattern is classified individually without regard to the local correlation among the fail patterns.
The present invention is directed to a method for determining the root causes of fail patterns in integrated circuit chips. Initially for a given integrated circuit chip layout, a plurality of potential defects are identified in the given integrated circuit chip layout, and a plurality of potential fail patterns are identified in the given integrated circuit chip layout. Identification of the plurality of potential defects includes using layout connectivity information from the integrated circuit chip layout to identify the potential defects. Correlations between the identified potential defects and identified potential fail patterns are identified, and these correlations are used to identify groupings of potential fail patterns and potential defects. Each grouping includes one potential defect and one or more potential fail patterns. For an actual integrated circuit chip that is to be tested, actual fail patterns are identified in the integrated circuit chip. These actual fail patterns are compared to the identified groupings of potential fail patterns and potential defects to identify actual defects in the integrated circuit chip.
In one embodiment, identification of the plurality of potential fail patterns includes determining fail patterns that can be caused by the identified plurality of potential defects. Identification of the correlations between potential defects and potential fail patterns includes associating each potential fail pattern with all potential defects that are potential root causes of that potential fail pattern. Use of the correlations to identify groupings of potential fail patterns includes identifying potential fail patterns that can result from the same defect. Identification of actual fail patterns includes searching bit fail maps associated with the integrated circuit chip.
In one embodiment, use of the groupings of potential fail patterns and potential defects to identify actual defects includes grouping the actual fail patterns according to spatial correlations across the integrated circuit chip, matching the groupings of actual fail patterns to the groupings of fail patterns and potential defects and identifying potential defects associated with the groupings of potential fail patterns and potential defects to which the groupings of actual defects are matched. In one embodiment, the spatial correlations include areas of the integrated circuit chip. In one embodiment, the spatial correlations correspond to the entire integrated circuit chip.
In one embodiment, the method also includes determining a total number of each potential defect that can occur in the integrated circuit chip arrangement, and using the total numbers to calculate a probability of occurrence of each potential failure pattern. In one embodiment, the potential defects include breaks or short circuits within the circuitry of the integrated circuit chip arrangement.
Systems and methods in accordance with the present invention correlate fail patterns in an integrated circuit chip or wafer with defect locations in that chip or wafer to identify the root cause of such fail patterns and to improve integrated circuit manufacturing yield. Referring initially to
The identified defects are the roots causes of the fail patterns. Stated another way, the fail patterns are the functional manifestations of the underlying defects in the integrated circuit chip. Therefore, identification of fail patterns is used to identify actual defects in the integrated circuit chip. In order to use the fail patterns to derive the defects, correspondences between fail patterns and defects are required. In one embodiment, the desired correspondences are obtained by identifying correspondences between the identified potential defects and the identified potential fail patterns in the integrated circuit chip layout 108. A given fail pattern can result from different defects. In addition, a given defect in an integrated circuit chip can manifest as one or more fail patterns. In one embodiment, potential defects are grouped by the common failure patterns associated with the defects. Preferably, the potential fail patterns are grouped according to a common defect 110.
A given grouping of potential fail patterns and the associated common potential defect that is the root cause of the all of the fail patterns in the group is associated with the integrated circuit chip layout from which the potential fail patterns and potential defect were derived. Each integrated circuit chip layout can have a plurality of associated groupings of potential fail patterns. Therefore, all potential fail patterns that can result from a given defect are grouped together. In one embodiment, these groups are saved to a persistent storage location to be used any time that an integrated circuit chip is created in accordance with the integrated circuit chip layout. The groupings are used to determine the likely root causes, i.e., the defects, associated with observed fail patterns in actual integrated circuit chip wafers that are tested. Fail patterns with common potential root causes will show local correlation if their common root causes are the dominant failure mechanisms in a related technology or product.
Having established groupings of potential fail patterns and common potential defects for an integrated circuit chip layout, these groupings are used in the testing and analysis of actual integrated circuit chips manufactured in accordance with the layout. A production integrated circuit chip 112 is placed in a suitable tester 114 that analyzes the wafer and produces fail data 116. Suitable testers and resulting fail data are known and available in the art. For example, a programmable tester can be used to perform the functional and parametric testing of dynamic random access memory (DRAM), static random access memory (SRAM), video random access memory (VRAM) and single in-line memory module (SIMM) devices. Memory cells that failed a specific test are shown as black squares on a bit fail map, while memory cells that passed the test are shown as white squares (402 in
The groupings of the actual fail patterns are compared to the potential fail pattern groupings 122, and matches are identified. From the potential fail pattern groupings that match the actual fail pattern groupings, defects, i.e., underlying root causes, for the actual fail patterns are obtained 124. In particular, the identified defects are the potential defects associated with the potential fail pattern groupings with which the actual fail patterns are matched. Therefore, systems and methods in accordance with the present invention provide for a more accurate identification of defects in integrated circuit chips than existing systems that do not consider the correlation of fail patterns. In one embodiment, the steps of actual fail pattern recognition, actual fail pattern grouping, comparison of actual groupings to potential groupings and the identification of defects are performed by the tester. Alternatively, a separate dedicated or general purpose computing system is used to handle the analysis.
Yield analysis and physical failure analysis (PFA) in a 45 nm-technology silicon on insulator static random access memory (SOI SRAM) was performed using methods for the determination of root causes of fail patterns in accordance with the present invention. Initially, an extensive SRAM layout analysis was performed to determine the potential defect-related failure mechanisms, i.e., defects, on all active and metal interconnect layers and to determine potential SRAM fail patterns that might be induced by the potential failure mechanisms. Referring to
By counting the number of contacts corresponding to the occurrence of each one of the fail patterns in the entire SRAM design, the failing probability of each fail pattern is calculated. In addition, ratios of probabilities of occurrence of each one of the failing patterns associated with a given defect are calculated. As illustrated, the fail probability ratio of an SCF failure pattern occurrence to a VP failure pattern occurrence is 2:3 for the SRAM layout illustrated. In one embodiment, this ratio of SCF failure pattern occurrence to a VP failure pattern occurrence is used to identify the root cause of such failures when the chip-level correlation of SCF to VP in the actual chip also yields a 2:3 ratio (
Having established potential defects and groupings of potential fail patterns associated with these root causes as illustrated in
In one embodiment, the local correlations of fail patterns are extended to the chip level for further yield analysis or confirmation of the results found in local regions. Referring to
While the present invention has been particularly described in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the present description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
Methods and systems in accordance with exemplary embodiments of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software and microcode. In addition, exemplary methods and systems can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer, logical processing unit or any instruction execution system. For the purposes of this description, a computer-usable or computer-readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. Suitable computer-usable or computer readable mediums include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems (or apparatuses or devices) or propagation mediums. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk—read only memory (CD-ROM), compact disk—read/write (CD-R/W) and DVD.
Suitable data processing systems for storing and/or executing program code include, but are not limited to, at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements include local memory employed during actual execution of the program code, bulk storage, and cache memories, which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices, including but not limited to keyboards, displays and pointing devices, can be coupled to the system either directly or through intervening I/O controllers. Exemplary embodiments of the methods and systems in accordance with the present invention also include network adapters coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Suitable currently available types of network adapters include, but are not limited to, modems, cable modems, DSL modems, Ethernet cards and combinations thereof.
In one embodiment, the present invention is directed to a machine-readable or computer-readable medium containing a machine-executable or computer-executable code that when read by a machine or computer causes the machine or computer to perform a method for determining root causes of fail patterns in integrated circuit chips in accordance with exemplary embodiments of the present invention and to the computer-executable code itself. The machine-readable or computer-readable code can be any type of code or language capable of being read and executed by the machine or computer and can be expressed in any suitable language or syntax known and available in the art including machine languages, assembler languages, higher level languages, object oriented languages and scripting languages. The computer-executable code can be stored on any suitable storage medium or database, including databases disposed within, in communication with and accessible by computer networks utilized by systems in accordance with the present invention and can be executed on any suitable hardware platform as are known and available in the art including the control systems used to control the presentations of the present invention.
While it is apparent that the illustrative embodiments of the invention disclosed herein fulfill the objectives of the present invention, it is appreciated that numerous modifications and other embodiments may be devised by those skilled in the art. Additionally, feature(s) and/or element(s) from any embodiment may be used singly or in combination with other embodiment(s) and steps or elements from methods in accordance with the present invention can be executed or performed in any suitable order. Therefore, it will be understood that the appended claims are intended to cover all such modifications and embodiments, which would come within the spirit and scope of the present invention.
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|Cooperative Classification||G11C29/56008, G01R31/31718, G11C29/10, G01R31/2894, G01R31/318314, G11C29/56|
|European Classification||G11C29/56B, G11C29/10, G11C29/56, G01R31/3183B, G01R31/317L, G01R31/28G7|
|Dec 12, 2007||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, HOWARD;HAWKINS, KATHERINE V.;HENG, FOOK-LUEN;AND OTHERS;REEL/FRAME:020232/0863;SIGNING DATES FROM 20071109 TO 20071126
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION,NEW YO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, HOWARD;HAWKINS, KATHERINE V.;HENG, FOOK-LUEN;AND OTHERS;SIGNING DATES FROM 20071109 TO 20071126;REEL/FRAME:020232/0863
|Oct 18, 2013||REMI||Maintenance fee reminder mailed|
|Mar 9, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Apr 29, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140309