|Publication number||US8074159 B2|
|Application number||US 12/823,347|
|Publication date||Dec 6, 2011|
|Filing date||Jun 25, 2010|
|Priority date||Jul 21, 2005|
|Also published as||US7747933, US8296639, US8489975, US8739011, US20070033512, US20100262872, US20120079358, US20130013985, US20130305128|
|Publication number||12823347, 823347, US 8074159 B2, US 8074159B2, US-B2-8074159, US8074159 B2, US8074159B2|
|Inventors||Christopher S. Johnson|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (19), Non-Patent Citations (1), Referenced by (2), Classifications (10), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 11/186,713, filed Jul. 21, 2005, now U.S. Pat. No. 7,747,933, issued Jun. 29, 2010. The disclosure of the previously referenced U.S. patent application is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits and, in particular, to error detection and remedial measures in the context of integrated circuits transmitting and receiving multi-bit address and data information.
2. Description of Related Art
Encoders and Decoders for detection and correction of data errors have long been used in integrated circuits, particularly in Dynamic Random Access Memories (DRAMs), which may be susceptible to data storage errors. Methods of parity generation, storage, and checking have often been implemented in an attempt to discover where and when storage errors occur. Generally, parity is defined as the calculation of a number of asserted signals, or bits, in a collection of signals generally referred to as a bus. Typically, a “1” is considered the asserted state. In a characteristic application, a data byte containing 8 bits may be used as the base collection. As an example, if the data byte has the value “1100 1011” five bits contain the value of “1” and three bits contain the value of “0.” To track the parity of a data byte, an additional bit may be added to the byte to indicate the parity of the byte. In this case, if odd parity is desired, the parity bit is placed in the appropriate state to make the total number of asserted bits in the collection of bits including the data byte and the parity bit an odd number. Therefore, for the case of five asserted bits in the data byte, the parity bit is de-asserted to keep the total number of asserted bits odd. If, as another example, the data byte contains two asserted bits, the odd parity bit is asserted to make the total number of asserted bits in the combination of the data byte and the parity bit an odd number, namely three in this case. Parity may also be generated and checked as even parity. In even parity, the parity bit is asserted or de-asserted to make the total number of asserted bits in the collection of the data byte and parity bit equal to an even number.
In many conventional memory systems containing parity for the detection of storage errors, the additional parity bit is stored in memory along with the data byte requiring 9 bits of memory storage for each byte of data. With this extra storage bit, if the data byte and parity are stored with odd parity, when the read occurs a check is performed to verify that odd parity is present on the read data. If not, then an error has occurred in either storage or retrieval of the data.
Additionally, systems have been developed to check that an address, or other signals, communicated from a transmitter to a receiver are received correctly. In the case of address signals, detecting and possibly attempting to correct address errors is important to prevent data from being read or written to the wrong storage location. In these address fault detection systems error detection is desired for the transmission of signals, not storage. Therefore, there is no need to store the parity bit(s). Instead valid parity is generated at the transmission end, the parity and data signals are transmitted, and a check is performed to ensure that valid parity is still present at the receiving end. In addition, using additional bits beyond the parity bit, error correction codes can be combined with the parity bit. The error correction codes accompany the transmission of data and parity, allowing correction of certain errors at the receiving end that may occur in transmission. One approach to dealing with this problem of signal transmission errors and correction techniques is seen in U.S. Pat. No. 5,173,905 to Parkinson et al.
As the need for higher speed and bandwidth to memory increases, engineers push closer to the speed and signaling boundaries where transmission errors may occur. Signals between modern semiconductor devices may have very low voltage swings or may be configured as current mode signals. The smaller voltage swings reduce the acceptable margin of error even with more precise input signal level sensors. Also, pushing the signal transmissions to higher speeds means that a shorter time period exists when the signal is in a steady state of a high or a low when it can be sensed before the signal makes a transition to the next state. Computer graphics controllers and the graphics DRAMs used in graphics memory systems are particularly high consumers of memory bandwidth and therefore vulnerable to signal transmission errors.
As a result, there is a need for simple low cost detection of signal transmission and reception errors on high speed buses, particularly graphics buses, to allow for remedial measures to be taken. Additionally, there is a need to perform this operation without adding additional Input/Output (IO) signals to devices already under severe signal count constraints.
One embodiment of the invention comprises a semiconductor memory comprising at least one multi-mode reporting signal, a state register, and a parity detector for determining if a set of signals received on a communication bus contains a desired parity. The multi-mode reporting signal enables reporting of communication faults without adding additional signals to the semiconductor memory. The multi-mode reporting signal may be configured in a normal operational mode, or it may be configured in a fault reporting mode for signaling the communication fault to an external device. An external device, such as a memory controller or graphics memory controller, may place the multi-mode reporting signal in the fault reporting mode by writing to an enable unit within the semiconductor memory.
Additionally, the state register enables the storing of received values from the communication bus. This storing of received values allows an external memory controller to read the state register to determine which signals were received incorrectly. With the state register, an external device may determine what type of signal patterns are received correctly and what type of signal patterns may fail. In this error detection system, parity may be defined as even or odd. Also, parity may be generated based on various signal collections depending upon the type of signals present on the communication bus and the desired data patterns to be placed on the bus.
Another embodiment of the invention comprises a system including a memory controller and at least one semiconductor memory. In this embodiment, the memory controller may generate the proper parity for the set of signals on the communication bus and transmit the signals and parity to the at least one semiconductor memory. The at least one semiconductor memory then checks for expected parity and stores the received signal values in the state register. If a parity fault is detected and the at least one semiconductor memory is configured to report the fault, the fault is indicated to the memory controller. The memory controller may then read the state register in the at least one semiconductor memory to determine which signal was not received correctly. As a result of the determination, the memory controller may then attempt to modify various transmission characteristics in an attempt to remedy the faulty communication.
Yet another embodiment of the invention comprises a computing system including a processor, at least one input device, at least one output device, the memory controller, and at least one semiconductor memory. In this embodiment, the memory controller may physically be separate from the processor or may be on the same semiconductor device as the processor.
In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention:
In one embodiment of the invention, depicted in
For detecting the communication faults, a parity detector 110 is connected to the communication bus 200. A parity fault may be reported if the received parity does not match a desired parity. The desired parity may be configured as even or odd parity. As described previously, parity is defined as the calculation of a number of asserted signals, or bits, in a collection of signals generally referred to as a bus. In a characteristic application, a data byte containing 8 bits may be used as the base collection. As previously noted, if the data byte has the value “1100 1011” five bits contain the value of “1” and three bits contain the value of “0.” For odd parity, the parity bit is de-asserted to make the total number of asserted signal in the combination of the data byte and parity bit equal to an odd number. On the other hand, for even parity, the parity bit is asserted to make the total number of asserted signal in the combination of the data byte and parity bit equal to an even number. This is a simple example of a typical parity implementation for a single data byte. The present invention comprises many more signals in more flexible parity arrangements.
In this straightforward partitioning, it may be desirable to separate each of the four data bytes (211, 212, 213, and 214) into separate parity checking collections. The parity bit associated with each data byte (211, 212, 213, and 214), while in the parity checking mode may be, for example, the write enable signals 218 for each byte, denoted in
Many other collections are contemplated within the scope of the invention. For example, the data bytes (211, 212, 213, and 214) may be organized into 16 bit words with one parity bit. In this configuration, as an example, WDQS0 may be associated with the 16 bit word containing data byte zero 211 and data byte one 212. WDQS2 may be associated with the 16 bit word containing data byte two 213 and data byte three 214. In another configuration for the data portion, the entire data bus may be configured with a single data parity bit such as WDQS0. Similarly, the address portion 220 may contain additional signals such as the bank addresses BA0-1. In this address portion 220 configuration it may be desirable to designate BA0 as one address parity bit 228 and BA1 as an additional address parity bit 228. The address bus may then be split into two portions, such as A0-A5 as one portion with BA0 as a first address parity bit 228 and A6-A11 as the other portion with BA1 as a second address parity bit 228. Yet another configuration may move the Data Mask signals DM0-3, from the control portion 230 to the data portion 210 either as data bits or possibly as data parity bits. It will be clear to a person skilled in the art that many different combinations are possible. Additionally, allowing configuration in different modes is desirable for flexibility in analysis of communication faults.
Reporting the communication fault is performed by at least one multi-mode reporting signal 240. In the exemplary embodiment shown in
Communication fault reporting may be disabled. When communication fault reporting is disabled, by writing to a control register in the graphics DRAM 100′, the multi-mode reporting signal 240 is configured to perform its normal operational function. Additionally, when the system is configured to operate in a normal, non-parity mode, the address, data, and control signals designated as parity bits may be configured, in the memory controller 300, to perform normal operational functions rather than performing the parity bit function.
However, if detection of communication faults is desired, the multi-mode reporting signal 240 may be placed in a fault reporting mode whereby the multi-mode reporting signal 240 is asserted whenever a communication event contains a parity error. As long as communication events are received with proper parity, the multi-mode reporting signal 240 will remain de-asserted. The assertion level of the multi-mode reporting signal 240 in the fault reporting mode may be defined as high or low depending on the system application and requirements of the memory controller 300.
To track where and when a communication fault occurs, a state register 120 (
If communication event errors are detected, they may be reported to a memory controller 300. The memory controller 300, as shown in
If desired, the system comprising a memory controller 300 and semiconductor memory 100 may be configured to attempt remedial measures for repairing communication errors by modifying various transmission characteristics of the communication bus 200. Memory controllers 300 and semiconductor memories 100 typically contain components for modifying the impedance levels of output drivers. Adjusting these impedance levels may help reduce signaling problems such as ringing and overshoot. Some memory buses are configured with current mode outputs. In these systems, in addition to adjusting output impedance, the communication bus 200 may have termination resistors on the signals of the communication bus 200. Adjusting the value of these resistors may reduce signaling problems. Input pins are often configured to sense the switch from a high to low, or low to high, at a specific voltage level supplied by the system. Adjusting this voltage level may reduce communication errors.
Finally, various timing adjustments are possible, such as when various outputs are triggered to switch state. For example, the switching of a plurality of outputs may be staggered such that not all the outputs of the plurality switch at the same time. Also, the various signal types (e.g., data, control, address) may be varied slightly in when they switch relative to each other to assist in timing issues such as input setup and hold problems. Other timing relationships and methods to modify signal transmission characteristics are also within the scope of the present invention.
Another embodiment of the invention, as shown in
Although this invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent apparatuses and methods that operate according to the principles of the invention as described.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4639917||Jun 22, 1984||Jan 27, 1987||Mitsubishi Denki Kabushiki Kaisha||Fault determining apparatus for data transmission system|
|US5155735||Mar 31, 1988||Oct 13, 1992||Wang Laboratories, Inc.||Parity checking apparatus with bus for connecting parity devices and non-parity devices|
|US5173905||Mar 29, 1990||Dec 22, 1992||Micron Technology, Inc.||Parity and error correction coding on integrated circuit addresses|
|US5339322||Mar 29, 1991||Aug 16, 1994||Sgs-Thomson Microelectronics, Inc.||Cache tag parity detect circuit|
|US5355377||Nov 23, 1993||Oct 11, 1994||Tetra Assoc. Inc.||Auto-selectable self-parity generator|
|US5606662||Mar 24, 1995||Feb 25, 1997||Advanced Micro Devices, Inc.||Auto DRAM parity enable/disable mechanism|
|US5719890||Jun 1, 1995||Feb 17, 1998||Micron Technology, Inc.||Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM|
|US5778007||Mar 11, 1997||Jul 7, 1998||Micron Technology, Inc.||Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM|
|US5872802||May 3, 1996||Feb 16, 1999||Cypress Semiconductor Corp.||Parity generation and check circuit and method in read data path|
|US6125454||May 11, 1994||Sep 26, 2000||Siemens Aktiengesellschaft||Method for reliably transmitting information on a bus|
|US6125466||Nov 28, 1994||Sep 26, 2000||Cabletron Systems, Inc.||DRAM parity protection scheme|
|US6185718||Feb 27, 1998||Feb 6, 2001||International Business Machines Corporation||Memory card design with parity and ECC for non-parity and non-ECC systems|
|US6260089||Nov 25, 1998||Jul 10, 2001||International Business Machines Corporation||Method and apparatus for implementing connections with circuits|
|US6314550||Jun 9, 1998||Nov 6, 2001||Altera Corporation||Cascaded programming with multiple-purpose pins|
|US6317417||Oct 5, 1998||Nov 13, 2001||Compaq Computer Corporation||Method and apparatus for dynamic signal modification on a parallel bus|
|US6414688||Jan 29, 1999||Jul 2, 2002||Micron Technology, Inc.||Programmable graphics memory method|
|US7293221||Jan 27, 2004||Nov 6, 2007||Sun Microsystems, Inc.||Methods and systems for detecting memory address transfer errors in an address bus|
|US20020018389||Aug 8, 2001||Feb 14, 2002||Hitachi, Ltd.||Data storing method of dynamic RAM and semiconductor memory device|
|US20070033512||Jul 21, 2005||Feb 8, 2007||Johnson Christopher S||Method and apparatus for detecting communication errors on a bus|
|1||"Micron, Graphics DDR3 SDRAM," Micron Technology, Inc. , 2003, pp. 1-66.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8489975 *||Sep 14, 2012||Jul 16, 2013||Micron Technology, Inc.||Method and apparatus for detecting communication errors on a bus|
|US8739011||Jul 16, 2013||May 27, 2014||Micron Technology, Inc.||Method and apparatus for detecting communication errors on a bus|
|U.S. Classification||714/799, 714/768, 711/112|
|International Classification||G06F11/00, H03M13/00, H04L1/00, G08C25/00|
|Cooperative Classification||G06F11/1016, G06F11/10|