|Publication number||US7346878 B1|
|Application number||US 10/858,836|
|Publication date||Mar 18, 2008|
|Filing date||Jun 1, 2004|
|Priority date||Jul 2, 2003|
|Publication number||10858836, 858836, US 7346878 B1, US 7346878B1, US-B1-7346878, US7346878 B1, US7346878B1|
|Inventors||Avi Cohen, Mark Ghinovker, Michael E. Adel|
|Original Assignee||Kla-Tencor Technologies Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (97), Non-Patent Citations (15), Referenced by (36), Classifications (6), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority of U.S. Provisional Patent Application No. 60/484,627 filed 2 Jul. 2003 by Avi Cohen et al., which application is incorporated herein by reference in its entirety for all purposes.
The present invention relates generally to the field of semiconductor metrology and inspection. More specifically, it relates to techniques for providing targets for metrology and/or inspection.
Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrating circuits using semiconductor materials which are layered and patterned onto a substrate, such as silicon. Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the device must be defect free prior to shipment of the device to the end users or customers.
Typically, defects are detected within special test structures or targets, rather than the active device or die itself. By way of example, various targets are designed to measure misalignment or overlay errors between two adjacent layers. Other targets are designed for other purposes, such as measurement of critical dimension or detection of electrical faults or killer defects. There are numerous types of targets on which characteristics may be measured or which may be inspected for defects, e.g., by comparing to an ideal reference target to the target under inspection.
Although these targets are used to estimate yield or defect density within the active area, the targets are typically relegated to special test areas of the die (e.g., a test pad in the center of the die) or to the scribe line which is located between the dies. That is, the targets are not located within the same area as the functioning or active device. Conventional positioning of targets outside the active areas allows one to dedicate product space to product features. It has been undesirable to utilize active area space for nonfunctioning structures because engineers are constantly striving to maximize active feature density.
Unfortunately, a test structure positioned in the scribe line does not best represent product function or typically variations across the field of the lithography (or exposure) tool. Multiple dies are exposed in a single field of the lithography tool. Although the scribe lines may extend across the wafer, these scribe lines may not extend across the field. Accordingly, defects captured or measured within the targets may not be a good indicator of defects within the product area or die itself. In a specific case, the lithography tool usually contains aberrations in its lens system which result in feature misalignments or pattern placement errors across the field. Even if a test structure is placed in each field (such as in the center of each die or within a scribe line that extends across the field), a manufacturing process may be different for different areas of the product area, as opposed to the test area. For instance, the process may vary with feature density. By way of specific example, product feature areas may have a different density than target feature areas and, accordingly, polish differently than the target feature areas. Thus, deviations or defects which depend on feature density are not captured by placing targets in special test areas because the targets may not have a feature density that corresponds to a representative sample of the product feature densities.
Accordingly, it would be desirable to have targets which more reliably and accurately represent defects within the active or product region. Additionally, targets which capture deviations across the lithography field are desired.
Accordingly, metrology or inspection targets are provided in-chip. That is, targets are integrated within the product device or die area. In general terms, the present invention provides techniques for enabling inspection or metrology on targets within the die or active area. Said in another way, target structures are inserted within the die or active area. In one embodiment, a set of rules are provided for integrating test structures within the die. For example, these rules may be implemented by one or more design engineers or by place-and-route tools which automatically generate the die layout pattern and thereafter insert the target structures into the die layout pattern based on these rules. Location data of each target is then retained during the layout generation and provided to one or more inspection or metrology tools and/or metrology engineers so that each target may be found and then inspected or measured.
In a specific embodiment, a method of generating a semiconductor layout pattern that is representative of a semiconductor die and a plurality of target structures is disclosed. A layout pattern that is representative of a semiconductor die and that can be used to fabricate such semiconductor die is provided. A plurality of layout patterns that are representative of a plurality of target structures are integrated into the layout pattern of the die so that the target layout patterns are integrated with the die layout pattern's active regions. The target layout patterns are usable to fabricate the target structures.
In one implementation, the semiconductor die is a product device. In as specific aspect, the die layout pattern includes routing paths between features located within the die layout pattern and the target layout patterns are each integrated into the die layout pattern at locations where there is an absence of the routing paths. In a further aspect, the die layout pattern conforms to a set of layout constraint rules and the target layout patterns are integrated so as to conform to such layout constraint rules, and each target layout pattern has a particular type which must conform to a set of target rules to facilitate inspection or measurement of each fabricated target structure and the target layout patterns are integrated so as to conform to such target rules.
In a specific implementation, the target rules for each target type include a maximum spacing between each target layout pattern and a minimum spacing between each target layout pattern. Each target layout pattern is integrated so that it is at least the minimum spacing for its type to a next one of the target layout patterns having the same type and so that it is no more than the maximum spacing for its type from a next one of the target layout patterns having the same target type. In one aspect, the minimum spacing corresponds to a known process variation for fabricating the die using a particular process.
In one example, at least one of the target types is an overlay type and the target rules for each target layout pattern having the overlay type require that such overlay type target layout pattern be integrated within a first layer and a second subsequent layer so as to have a same center of symmetry.
In another embodiment, the layout constraint rules include feature size constraints and feature pitch requirements, and the target layout patterns are integrated so as to conform to the feature size constraints and the feature pitch constraints. In another aspect, the layout constraint rules include a spacing size and aspect ratio constraint based on each available space within the die pattern, and each target layout pattern is sized to conform to at least one of the available space's size and aspect ratio constraint for integration of such each target in such available space. In one implementation, the target layout patterns are selected from a library of standard target layout patterns which conform to any combination or portion of the layout constraint rules and the target rules.
In another embodiment, location and identity of each target layout pattern are stored as location data. In one aspect, the location data is transferred to a metrology or inspection tool. In another aspect, the location data is stored within a fabrication database which is accessible by a plurality of processing tools for fabricating the die and target structures from the die and target layout patterns. Preferably, the fabrication database is also accessible by a plurality of metrology tools for measuring the target structures and/or a plurality of inspection tools for inspecting the target structures. In a specific embodiment, the location data is stored in a format which allows a metrology or inspection tool to access the stored location data, such as OpenAccess format.
In one implementation, the target layout patterns are integrated automatically by a design tool configured to comply with the layout constraint rules and the target rules. In another embodiment, the target rules include requirements for placing each target layout pattern on a layer within a layer stack which allows measurement or inspection of each target structure. In another aspect, the target rules include a requirement that the layer of each target layout pattern is on a top layer or is underneath a transparent layer. In yet another aspect, the target rules include a requirement that the layer of each target layout pattern is underneath an opaque layer.
In one embodiment, the target rules include placing the target layout patterns so that they conform to a predetermined sample plan. In a further aspect, the sample plan is based on one or more of the following: a known rate of process variation, a known rate of lithography aberration, a known rate of scanning errors, a known rate of reticle write errors, and a measurement uncertainty requirement.
In one implementation, the target layout patterns are integrated within a dummy layer. In another implementation, the target layout patterns are integrated within a special layer which is excluded from the die layout pattern. In a final embodiment, the target structures are selected from a group comprising an overlay target structure, a critical dimension (CD) target structure, a film thickness target structure, a lithography focus or exposure structure, and a chemical mechanical polishing (CMP) uniformity or formed dishing and erosion structure.
In another aspect, the invention pertains to a computer system operable to generate a semiconductor layout pattern that is representative of a semiconductor die and a plurality of target structures. The computer system includes one or more processors and one or more memory configured to perform one or more of the above method operations. In yet another aspect, the invention pertains to a computer program product for generating a semiconductor layout pattern that is representative of a semiconductor die and a plurality of target structures. The computer program product includes at least one computer readable medium and computer program instructions stored within the at least one computer readable product configured to perform one or more of the above described inventive procedures.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.
Reference will now be made in detail to a specific embodiment of the invention. An example of this embodiment is illustrated in the accompanying drawings. While the invention will be described in conjunction with this specific embodiment, it will be understood that it is not intended to limit the invention to one embodiment. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
Integrating the targets within the die itself has several advantages. The integrated targets may be more reliably and accurately inspected or measured to determine whether there are any defects or whether a process is deviating out of specification, as compared with conventional targets placed within special test areas or within the scribe line. Since the targets are integrated within the die itself, the targets better represent the active region structures. For instance, the targets have a same feature density as the die features and will likely result in the same defects and process problems as the die features. Accordingly, the targets may be used to more accurately predict product yield (e.g., yield of the active structures).
An integrated circuit (IC) device and target structure may be designed using any suitable design techniques. For example, an IC designer may use preexisting schematic library blocks to form the IC device and targets using, for example, electronic design automation (EDA) tools. In some cases, the IC designer may create an entire IC device target or part of an IC device or target from scratch with the aid of any suitable design system, such as conventional computer aided design (CAD) tools. For example, the IC designer may use a schematic CAD tool to plan the logic diagrams for a particular IC device or target. Still further, the IC designer may write a description of the IC device or target or portions of the IC device or target with the aid of a hardware design language, such as VHDL.
The IC designer then typically generates a layout pattern from the IC circuit design. The layout pattern may be composed of a plurality of electronic representations of IC layers that are later converted into a plurality of reticles that are used to fabricate a plurality of physical layers of an IC device and target. Each physical layer of the fabricated IC device corresponds to one of the reticles and an associated one of the electronic representations from the layout pattern. For example, one electronic representation may correspond to a diffusion pattern on a silicon substrate, another to a gate oxide pattern, another to a gate polysilicon pattern, another to a contact pattern on an interlayer dielectric, another to a line pattern on a metallization layer, and so on. The targets may be formed from any combination of one or more layers. For example, a special layer may be reserved for the target structures, or the targets may be formed from the dummy layer. Each electronic representation is composed of a plurality of polygons or other shapes (herein, referred to as “figures”), which together define the layout or reticle pattern.
The layout pattern may be generated using any suitable technique, for example, by using EDA or CAD tools. For example, the IC designer may manually lay out the layout patterns for the IC device and targets with or without preexisting library cells. Alternatively, a synthesis tool may automatically create layout patterns for the IC device and targets from scratch or by piecing together preexisting library cells based on the schematic design.
A location and identity of each target layout pattern is also stored as location data in operation 106. The location of a particular target may be stored in any suitable format for identifying a position of the particular target. For example, the location may take the form of Cartesian or polar coordinates. The identity is generally used to distinguish between different types of targets. It may take the form of alphanumeric text which identifies the type of target, such as overlay, CD, etc., or the identity may take the form of a reference to a target image.
The location data is provided to a metrology or inspection tool in operation 108. The location data may be provided directly or indirectly through another entity, such as a database or controller. That is, the location data may be output by the CAD module and input or uploaded into a particular inspection or metrology tool. Alternatively, the location data may be stored within the fabrication database which is accessible by the various process, inspection, review, and metrology tools. The location data may be stored in a format that is readable or accessible by a particular inspection, review, or metrology tool. For example, the location data may be in OpenAccess format, which is readable by inspection and metrology tools from KLA-Tencor.
The die and targets are then fabricated based on the layout patterns of the die and targets in operation 110. Reticles are first produced using the layout patterns. Each reticle corresponds to one or more electronic representation(s) from the circuit pattern database. The reticles may be produced by any suitable pattern generator or reticle writer equipment, such as a MEBES″ 4500, commercially available from ETEC of Hayward, Calif.
After the die and targets are at least partially fabricated, the targets and/or reticles may then be inspected or measured using the location data in operation 112. Any suitable inspection, review, or metrology tool may be utilized during any stage of the fabrication. Each tool may take the form of an optical system, such as a bright field or dark field optical system. The tool may also utilize both bright field and dark field modes. Examples of bright field systems include the 2350, 2351, 2360, and 2370 from KLA-Tencor, Corp. of San Jose, Calif. Examples of dark field system include the AIT II, AIT XP, Fusion, Fusion UV, and SPI PatternPro available from KLA-Tencor, Corp. of San Jose, Calif. The KLA 301 or 351 Reticle Inspection Tool may be used to inspect reticles. Each tool may also take the form of an electron beam (ebeam) system, such as a scanning, snapshot, or step-and-repeat type ebeam system. Examples of ebeam systems include the eV300 and eS20XP available from KLA Tencor, Corp. of San Jose, Calif. A tool may be designed to detect special types of defects, such as macro defects across a large area of the sample, defects on a bare substrate, or defects within solder burns (e.g., ball grid array bumps). Each tool may also be stand alone or integrated within a processing tool.
The CAD module 154 is generally configured to generate a layout pattern either automatically or via input from a design engineer. Several suitable CAD products for designing IC products are available from Cadence of San Jose, Calif. and Mentor Graphics of Wilsonville, Oreg. The layout pattern 156 is then checked by a design rule check (DRC) module 158. The DRC module is generally configured to determine whether the layout 156 conforms to a set of layout constraints. A feedback pathway 160 is provided to CAD module 154 for modification of the layout pattern 156 when the layout pattern fails to conform to the DRC. For example, the DRC module may indicate a number of nonconforming layout regions which may the be modified to comply with the design rules. As shown, the CAD module and DRC module are contained within the same computer system 152. Of course, the CAD module and DRC module may be implemented in any suitable combination of hardware and software.
Referring back to
Location data 172 for each target is also provided to the inspection or metrology tools 168 so that the targets may be found by the tool. In one specific embodiment, the location data is retained in fabrication database 170, which is accessible by the inspection or metrology tools 168. Alternatively, the location data may be directly provided or transferred to the inspection or metrology tools 168.
As shown in
Each target layout pattern is also placed so as to conform to layout constraint rules in operation 304. Layout constraint rules generally include design rules which must be followed to likely achieve a functioning device given the current process parameters. For example, current processes cannot form a structure having a line width below a particular minimum line width. Accordingly, the layout constraints include a minimum limit for line width. Other layout constraint examples are further described below.
Each target layout pattern is also placed so that it conforms to a set of target rules to facilitate inspection or measurement of the fabricated target structures in operation 306. The target may have to be formed with a particular size, shape, and orientation to allow inspection or characterization of the target. For instance, a metrology tool may not be able to measure a particular type of target's features that are smaller than a particular size. Thus, this particular target feature would have to have a size greater than the minimum required size. Further examples of target rules are outlined below.
The layout constraint rules may include any number and type of rules for likely achieving a functioning die or reducing defects. One noteworthy layout constraint is a limit on feature size and pitch. The reason for this constraint is that placement errors are typically dependent on feature size and density.
In one implementation, the distance between each target and neighboring die or target feature may also be required to be greater than a predetermined minimum distance to comply with a feature density requirement. Thus, distance 408 a between die feature 402 and target feature 404 is selected to be less than the predetermined minimum distance. Likewise, distance 408 b between target feature 404 and target feature 406 is selected to be less than the predetermined minimum distance. Accordingly, targets 404 and 406 are placed to meet these distance requirements. Density may also be specified in terms of feature area per total unit area, which is required to be less than a predetermined density value. Thus, the target features 404 and 406 may be sized and placed so that their areas plus the area of die feature 402 divided by the total area 401 is less than the predetermined maximum density value.
Each target is also sized and placed so as to fit within available spaces of the die layout pattern.
The target rules may include any number and type of rules for facilitating inspection, review, or metrology on the target structures. Particular target types are designed to detect defects or problems with one or more process or exposure tools. The targets are preferably placed so as to capture a maximum number of defects or problems without utilizing an unreasonable amount of die area for the targets. The selection of the number and density of the targets is referred to as a “sample plan.” In one implementation, the sample plan includes a minimum spacing and a maximum spacing between targets of a same type.
The sample plan may be based on any suitable type and number of known process variations.
A sample plan is then determined for the targets based on the provided known rate of process variation, known rate of lithography aberrations, known variation of scanning errors, a known rate of reticle write errors, and measurement uncertainty requirement in operation 510. For example, a minimum placement distance between targets may be selected as the minimum variation spacing of the process variations, lithography aberrations, and lithography errors. In the above examples of variations of 100 μm, 1 mm, and 1 mm, the spacing may be selected to be 100 μm. A spacing may be selected for both an x direction and a y direction (e.g., to accommodate variations both along the direction of the slit and direction of the scan). A suitable number of targets may be selected to result in a measurement uncertainty equal to or less than the required measurement uncertainty.
Any suitable technique may be used to obtain known process or lithography error variations for a sample plan of a particular target type. For example, the lithography aberration variation across the field are usually provided with the lithography tool. One may use test reticles and quantify the variation in scanning errors across the reticle. Likewise, a number of test wafers may be fabricated to quantify the variation in process errors across the wafer or field. The measurement uncertainty requirement may be obtained by independently estimating the uncertainty contributions, such as precision, tool induced shift and mark fidelity.
The techniques of the present invention may also be practiced on reticles, as well as semiconductor devices. That is, targets may be written within the active regions of one or more reticles using a reticle writer tool. These targets may then be inspected or measured on the resulting reticles. When targets are to be placed within an active regions of a reticle, a known rate of reticle write errors may also be considered as a target placement parameter. More generally, an additional consideration regarding the density of placement of the metrology or inspection targets may include the performance characteristics of the reticle write process. By way of examples, the characteristic sub-field size of the reticle write tool or the nature of the registration errors (e.g., due to sequence of the reticle patterning) may be considered during target placement.
Each target type may have a particular size, shape, and orientation which depends on the particular inspection, review, or metrology to be performed on such target. Any suitable number and type of targets may be integrated within a die layout pattern. The targets may include one or more of the following types: overlay, CD, film thickness, lithography focus or exposure, CMP polish uniformity or formed dishing and erosion, etc.
By way of example, rules may be developed for an overlay type target based on the types of measurements made on such a target type. Overlay type targets are used to measure misalignment between two different layers. Of course, misalignment may be measured between more than two layers, e.g., all the layers of the device. In a two layer example, each overlay target is formed from a first layer structure and a second subsequent layer structure. Additionally, the structures on the different layers of an overlay target would be designed to have a same center of symmetry. Thus, in a two layer target, the first layer target structures would have a same center of symmetry as the second layer target structures. Additionally, the target portions in the two different layers are preferably proximate to each other so that they may be measured together, e.g., within a single field. Although not required, the two different layer structures of each overlay target are preferably not on top of each other. In one implementation, the first layer structures are at a different rotational position with respect to the center of symmetry than the second layer structures. In another embodiment, the targets may be over the top of one another for Moiré or scatterometry measurements.
The target rules preferably include a requirement that the target be placed in a layer which is measurable or inspectable by a particular type of tool. For example, the target may have to be on a top layer or be covered with only optically transparent layers so that the target may be inspected by an optical tool. In other applications, the target may be required to be underneath an opaque layer so that the opaque layer's conformance to the underlying target may be inspected and/or measured. Additionally, each inspection, review, or metrology tool typically has a size constraint as to the measured or inspected structure. That is, structures below a particular size cannot be seen. Therefore, the targets must be sized so that they can be measured or inspected by the relevant tool.
Additionally, the die layout may be analyzed to determine whether particular portions or areas have a characteristic which negatively or positively affects metrology or inspection results, as compared with other areas of the die layout. For example, particular layout characteristics may result in more reliable or accurate metrology or inspection results. In one specific case, targets may be placed in areas which have characteristics that positively affect the metrology or inspection. In an example of such a feature characteristic, a chemical mechanical polishing (CMP) procedure is typically tuned to achieve superior accuracy with a particular feature density range. Thus, targets, such as overlay targets, may be placed in layout regions which are within the particular feature density range for an optimal CMP process.
The circuit designer may be aware of feature locations in the die layout which are most susceptible to error or defects. The designer may communicate the position of such features to the target placement software or layout engineer so that targets may be placed proximate to such problem features. This placement technique would likely result in a higher incidence of defect capture and more reliable resulting products.
As mentioned, the targets may also be placed within a dummy layer. It is common practice in semiconductor manufacturing today to include dummy structures in open areas of the circuit layout to ensure uniform pattern density. Dummy structures are generally used for optimal results in chemical mechanical polishing and other semiconductor manufacturing processes.
In order to enable targets inside the chip area, there are significant advantages in combining the functionality of the particular metrology (or inspection) target with the purpose of the dummy structures. That is, a structure which has two components that serve both purposes of a dummy structure and a metrology (or inspection) target would efficiently utilize the open spaces of the die area to increase CMP uniformity (and other dummy requirements where applicable), as well as to provide a metrology or inspection target. Additionally, a new type of metrology or inspection may be used with such combination marks. For example, a particular design pattern's fidelity may be monitored via such combination target. That is, a designer's intent regarding a particular pattern's function or structure may be verified with respect to the pattern being combined and measured or inspected in a dummy structure.
A combination target and dummy structure can be achieved in a number of different ways. In one example of a combination dummy and overlay structure, the structures can be designed on two masks such that they form interlaced periodic structures. Any suitable types of overlay structures may be used. Suitable overlay targets and techniques for determining overlay with same are described in the following U.S. patents and applications: (1) U.S. Pat. No. 6,462,818, issued 8 Oct. 2002, entitled “OVERLAY ALIGNMENT MARK DESIGN”, by Bareket, (2) U.S. Pat. No. 6,023,338, issued 8 Feb. 2000, entitled “OVERLAY ALIGNMENT MEASUREMENT OF WAFER”, by Bareket, (3) application Ser. No. 09/894,987, filed 27 Jun. 2001, entitled “OVERLAY MARKS, METHODS OF OVERLAY MARK DESIGN AND METHODS OF OVERLAY MEASUREMENTS”, by Ghinovker et al., (4) U.S. Pat. No. 6,486,954, issued 26 Nov. 2002, entitled “OVERLAY ALIGNMENT MEASUREMENT MARK” by Levy et al., (5) application Ser. No. 10/367,124, filed 13 Feb. 2004 by Mike Adel et al, and (6) application Ser. No. 10/785,396 filed 23 Feb. 2004 by Walter D. Mieher, et al. These patents and applications are all incorporated herein by reference in their entirety.
An overlay type combination and dummy structure includes two components one on a first layer or mask and one on a second layer or mask. Each component preferably complies with the requirements for a dummy structure of the process step associated with that layer or mask. A further example may be a case where these periodic structures are aligned such that the component on a first mask is symmetrically positioned with respect to the component on a second mask when the masks are correctly aligned. Also, the component on a first mask may be designed to fit into the open spaces within the component on a second mask and visa versa. As a further particular example, the periodic component on the two masks could be identical but offset by half a unit cell of the periodic structure along both x and y axes. Alternatively the component on a first mask may have a different structure than the component on a second mask but is still offset by half a unit cell of the component as above. Example overlay type combination targets are shown in
Each component may also contain an additional coarse segmentation which is periodic and is designed to improve the contrast and information content for the metrology tool as further described in the above referenced U.S. application Ser. No. 10/367,124 by Mike Adel et al.
In another technique, an array of targets may be conceptually used to fill in around actual device structures. As shown in
In these combination dummy and target examples, a signal is detected from the field of views (FOV's) as represented in
In general, rules for both dummy structures and the particular target type are followed when forming combination dummy and target structures. For instance, the dummy structure rules may require a particular pattern density or maximum open space size for ensuring a particular level of CMP uniformity. Additionally, the particular metrology or inspection procedure rules for the targets are followed. In one type of overlay metrology technique, the structures on two different layers are assessed to determine whether their centers of symmetry are where they should be (e.g., aligned) to thereby determine overlay. In this example, the structures are designed on two different layers and have a same center of symmetry or known relative centers of symmetry.
Other types of overlay metrology, such as scatterometry overlay determination, may require periodic structures which are designed to be aligned or designed with a predetermined offset since overlay is determined by assessing the phase relationship between the two layer structures. Several scatterometry overlay techniques are further described in the above referenced U.S. application Ser. No. 10/785,396 and several phase techniques are described further in U.S. Pat. No. 6,462,818, Issued 8 Oct. 2002 by Bareket and U.S. Pat. No. 6,023,338, issued 8 Feb. 2000 by Bareket, which patents are incorporated herein by reference in their entirety. For a CDSEM type measurement, the target structures are designed to replicate device features.
When an array of combination dummy and target structures is used (e.g.,
In a preferred embodiment, a list of target coordinates may be given to the metrology tool. The metrology tool then steps to each target coordinate. Since the targets are distributed across the FOV and the center is not defined, the tool does not have to center the targets in the FOV. Elimination of the target acquisition and centering operations significantly improves the efficiency of the metrology procedure. Furthermore, it eliminates the need for operator intervention at this step of the train procedure, enabling a greater level of automation in the process of metrology and inspection recipe generation.
After a die and targets are fabricated using a layer pattern having integrated active regions and targets, the targets may be inspected, reviewed, or measured in any suitable manner.
If a process is out of specification, a number of techniques may be implemented to alleviate the problem. In a first technique, a subsequent process may be adjusted to compensate for the process which is out of specification in operation 704. For example, if it is determined that the photoresist pattern is misaligned in any portion, the photoresist may then be stripped and reapplied in a corrected pattern to eliminate the misalignment. The subsequent process is then performed so as to continue fabrication of the same die in operation 706. For example, the wafer may be patterned. In a second technique, processing of the die may be halted in operation 708. The die may then be discarded in operation 710. The process which is out of specification may then be adjusted for subsequent die(s) in operation 712.
A target may be inspected, reviewed, or measured using conventional techniques. In an inspection example, an ideal baseline image of the target may be generated or “rendered” from the corresponding target layout pattern. The baseline image may be generated in any suitable manner, such as by merely directly converting the contents of the target layout pattern into an image. Alternatively, the target layout pattern may be rendered by simulating fabrication results from making a target that perfectly matches the target layout pattern. For example, the corners of a target pattern in the baseline image may be rounded to account for corner rounding that commonly occurs during fabrication of a target. The baseline image may also include simulated optical effects from retrieving an optical image of the simulated target. Such optical effects are necessarily encountered when an optical inspection technique is used to evaluate a target. Additionally, a vendor may provide the end user of the target, e.g. a fabrication facility, with the baseline image of the target and perform the above described steps of baseline generation. Alternatively, the baseline image may be generated from a target in an adjacent die in a die-to-die inspection approach. In this approach, the images of two supposedly identical targets are generated, one for a baseline image and one for a test image.
After the baseline image has been provided, the target is inspected to obtain a test image of the target. Any suitable mechanism may be implemented for obtaining the test image. For example, an optical or ebeam image be obtained. The test image is then compared to the baseline image. If a difference between the baseline and test images is greater than a predetermined threshold, it is determined that a defect exists. The defect may then be classified by comparing it to known defect types to determine a root cause of the defect. The root cause may include one or more out of specification process(es).
A further method of target layout placement could be with respect to modification of dummy structures to comply with specific metrology/inspection target design requirements. By way of example, if overlay was to be measured by scatterometry, then a layout rule could be implemented which requires that periodic dummy structures be placed above one another on subsequent layers. Furthermore, these dummy structures could be designed with specific offsets between them as disclosed in U.S. Applications: (1) application Ser. No. 10/729,838 filed 5 Dec. 2003 by Walter D. Mieher et al. and (2) application Ser. No. 10/785,396 filed 23 Feb. 2004 by Walter D. Mieher et al., which applications are herein incorporated by reference in their entirety. For example, adjacent areas could be designed to have equal but opposite offsets relative to the dummy structures on the underlying layer. Many other offset configurations could be implemented.
The techniques of the present invention may be implemented in any suitable combination of software and/or hardware system. Regardless of the system's configuration, it may employ one or more memories or memory modules configured to store data, program instructions for the general-purpose inspection operations and/or the inventive techniques described herein. The program instructions may control the operation of an operating system and/or one or more applications, for example. The memory or memories may also be configured to store layout patterns, layout constraint rules and target rules.
Because such information and program instructions may be employed to implement the systems/methods described herein, the present invention relates to machine readable media that include program instructions, state information, etc. for performing various operations described herein. Examples of machine-readable media include, but are not limited to, magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROM disks; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory devices (ROM) and random access memory (RAM). The invention may also be embodied in a carrier wave traveling over an appropriate medium such as airwaves, optical lines, electric lines, etc. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter.
Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Therefore, the described embodiments should be taken as illustrative and not restrictive, and the invention should not be limited to the details given herein but should be defined by the following claims and their full scope of equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4251160||Jul 13, 1978||Feb 17, 1981||U.S. Philips Corporation||Method and arrangement for aligning a mask pattern relative to a semiconductor substrate|
|US4475811||Apr 28, 1983||Oct 9, 1984||The Perkin-Elmer Corporation||Overlay test measurement systems|
|US4538105||Apr 28, 1983||Aug 27, 1985||The Perkin-Elmer Corporation||Overlay test wafer|
|US4703434||Apr 24, 1984||Oct 27, 1987||The Perkin-Elmer Corporation||Apparatus for measuring overlay error|
|US4714874||Nov 12, 1985||Dec 22, 1987||Miles Inc.||Test strip identification and instrument calibration|
|US4757207||Mar 3, 1987||Jul 12, 1988||International Business Machines Corporation||Measurement of registration of overlaid test patterns by the use of reflected light|
|US4757707||Mar 17, 1987||Jul 19, 1988||British Steel Corporation||Molten metal gas analysis|
|US4778275||Sep 24, 1986||Oct 18, 1988||U.S. Philips Corp.||Method of aligning a mask and a substrate relative to each other and arrangement for carrying out the method|
|US4782288||Dec 24, 1986||Nov 1, 1988||Sgs Microelettronica S.P.A.||Method for evaluating processing parameters in the manufacture of semiconductor devices|
|US4820055||Aug 25, 1986||Apr 11, 1989||Siemens Aktiengesellschaft||Apparatus for adjusting a mask with at least one adjustment mark relative to a semi-conductor wafer provided with at least one lattice structure|
|US4855253||Jan 29, 1988||Aug 8, 1989||Hewlett-Packard||Test method for random defects in electronic microstructures|
|US4929083||Mar 20, 1989||May 29, 1990||Xerox Corporation||Focus and overlay characterization and optimization for photolithographic exposure|
|US5017514||Nov 27, 1989||May 21, 1991||Nec Corporation||Method of manufacturing a semiconductor device using a main vernier pattern formed at a right angle to a subsidiary vernier pattern|
|US5100237||May 25, 1990||Mar 31, 1992||Asm Lithography||Apparatus for projecting a mask pattern on a substrate|
|US5112129||Mar 2, 1990||May 12, 1992||Kla Instruments Corporation||Method of image enhancement for the coherence probe microscope with applications to integrated circuit metrology|
|US5148214||Sep 17, 1991||Sep 15, 1992||Canon Kabushiki Kaisha||Alignment and exposure apparatus|
|US5156982||Jan 3, 1992||Oct 20, 1992||Shin-Etsu Handotai Co., Ltd.||Pattern shift measuring method|
|US5172190||Jan 11, 1991||Dec 15, 1992||Karl Suss Kg Prazisionsgerate Fur Wissenschaft Und Industrie - Gmbh & Co.||Alignment patterns for two objects to be aligned relative to each other|
|US5216257||Jul 9, 1990||Jun 1, 1993||Brueck Steven R J||Method and apparatus for alignment and overlay of submicron lithographic features|
|US5262258||Jun 12, 1991||Nov 16, 1993||Nec Corporation||Process of manufacturing semiconductor devices|
|US5296917||Jan 21, 1992||Mar 22, 1994||Mitsubishi Denki Kabushiki Kaisha||Method of monitoring accuracy with which patterns are written|
|US5383136||Mar 13, 1992||Jan 17, 1995||The United States Of America As Represented By The Secretary Of Commerce||Electrical test structure and method for measuring the relative locations of conducting features on an insulating substrate|
|US5414514||Jun 1, 1993||May 9, 1995||Massachusetts Institute Of Technology||On-axis interferometric alignment of plates using the spatial phase of interference patterns|
|US5436097||Mar 12, 1993||Jul 25, 1995||Kabushiki Kaisha Toshiba||Mask for evaluation of aligner and method of evaluating aligner using the same|
|US5438413||Mar 3, 1993||Aug 1, 1995||Kla Instruments Corporation||Process for measuring overlay misregistration during semiconductor wafer fabrication|
|US5477057||Aug 17, 1994||Dec 19, 1995||Svg Lithography Systems, Inc.||Off axis alignment system for scanning photolithography|
|US5479270||May 19, 1992||Dec 26, 1995||Eastman Kodak Company||Method and apparatus for aligning depth images|
|US5481362||May 6, 1993||Jan 2, 1996||Asm Lithography||Apparatus for projecting a mask pattern on a substrate|
|US5498501||Apr 4, 1995||Mar 12, 1996||Canon Kabushiki Kaisha||Exposure method|
|US5596413||Aug 17, 1995||Jan 21, 1997||Lucent Technologies Inc.||Sub-micron through-the-lens positioning utilizing out of phase segmented gratings|
|US5604819||Mar 15, 1993||Feb 18, 1997||Schlumberger Technologies Inc.||Determining offset between images of an IC|
|US5617340||Feb 3, 1995||Apr 1, 1997||The United States Of America As Represented By The Secretary Of Commerce||Method and reference standards for measuring overlay in multilayer structures, and for calibrating imaging equipment as used in semiconductor manufacturing|
|US5627083||May 12, 1995||May 6, 1997||Nec Corporation||Method of fabricating semiconductor device including step of forming superposition error measuring patterns|
|US5665495||Mar 7, 1995||Sep 9, 1997||Hyundai Electronics Industries Co., Ltd.||Method for fabricating a semiconductor with a photomask|
|US5674650||Aug 1, 1995||Oct 7, 1997||U.S. Philips Corporation||Method of repetitively imaging a mask pattern on a substrate, and apparatus for performing the method|
|US5699282||Jul 8, 1996||Dec 16, 1997||The United States Of America As Represented By The Secretary Of Commerce||Methods and test structures for measuring overlay in multilayer devices|
|US5701013||Jun 7, 1996||Dec 23, 1997||Mosel Viltelic, Inc.||Wafer metrology pattern integrating both overlay and critical dimension features for SEM or AFM measurements|
|US5702567||Jun 1, 1995||Dec 30, 1997||Kabushiki Kaisha Toshiba||Plurality of photolithographic alignment marks with shape, size and spacing based on circuit pattern features|
|US5703685||Jul 20, 1995||Dec 30, 1997||Kabushiki Kaisha Toshiba||Alignment method|
|US5712707||Nov 20, 1995||Jan 27, 1998||International Business Machines Corporation||Edge overlay measurement target for sub-0.5 micron ground rules|
|US5757507||Nov 20, 1995||May 26, 1998||International Business Machines Corporation||Method of measuring bias and edge overlay error for sub-0.5 micron ground rules|
|US5766809||Sep 24, 1996||Jun 16, 1998||Hyundai Electromics Industries Co., Ltd.||Method for testing overlay in a semiconductor device utilizing inclined measuring mark|
|US5783342||Dec 27, 1995||Jul 21, 1998||Matsushita Electric Industrial Co., Ltd.||Method and system for measurement of resist pattern|
|US5805290||May 2, 1996||Sep 8, 1998||International Business Machines Corporation||Method of optical metrology of unresolved pattern arrays|
|US5835196||Jan 5, 1995||Nov 10, 1998||Texas Instruments Incorporated||System and method for alignment of integrated circuits multiple layers|
|US5857258||May 12, 1994||Jan 12, 1999||The United States Of America As Represented By The Secretary Of Commerce||Electrical test structure and method for measuring the relative locations of conductive features on an insulating substrate|
|US5863680||Oct 10, 1996||Jan 26, 1999||Nikon Corporation||Exposure method utilizing alignment of superimposed layers|
|US5872042||Aug 22, 1996||Feb 16, 1999||Taiwan Semiconductor Manufacturing Company, Ltd.||Method for alignment mark regeneration|
|US5877036||Feb 26, 1997||Mar 2, 1999||Nec Corporation||Overlay measuring method using correlation function|
|US5877861||Nov 14, 1997||Mar 2, 1999||International Business Machines Corporation||Method for overlay control system|
|US5902703||Mar 27, 1997||May 11, 1999||Vlsi Technology, Inc.||Method for measuring dimensional anomalies in photolithographed integrated circuits using overlay metrology, and masks therefor|
|US5912983||Jul 25, 1997||Jun 15, 1999||Oki Electric Industry Co., Ltd||Overlay accuracy measuring method|
|US5923041||Apr 25, 1995||Jul 13, 1999||Us Commerce||Overlay target and measurement procedure to enable self-correction for wafer-induced tool-induced shift by imaging sensor means|
|US5939226||Jan 8, 1997||Aug 17, 1999||Mitsubishi Denki Kabushiki Kaisha||Aberration estimation reticle for determining overlay error|
|US5949145||Feb 27, 1997||Sep 7, 1999||Nec Corporation||Semiconductor device including alignment marks|
|US5960125||Nov 21, 1996||Sep 28, 1999||Cognex Corporation||Nonfeedback-based machine vision method for determining a calibration relationship between a camera and a moveable object|
|US5968693||Feb 9, 1999||Oct 19, 1999||Lucent Technologies Inc.||Lithography tool adjustment utilizing latent imagery|
|US6020966||Sep 23, 1998||Feb 1, 2000||International Business Machines Corporation||Enhanced optical detection of minimum features using depolarization|
|US6023338||Jul 12, 1996||Feb 8, 2000||Bareket; Noah||Overlay alignment measurement of wafers|
|US6037671||Nov 3, 1998||Mar 14, 2000||Advanced Micro Devices, Inc.||Stepper alignment mark structure for maintaining alignment integrity|
|US6061606||Aug 25, 1998||May 9, 2000||International Business Machines Corporation||Geometric phase analysis for mask alignment|
|US6077756||Apr 24, 1998||Jun 20, 2000||Vanguard International Semiconductor||Overlay target pattern and algorithm for layer-to-layer overlay metrology for semiconductor processing|
|US6079256||Dec 7, 1998||Jun 27, 2000||Kla Instruments Corporation||Overlay alignment measurement of wafers|
|US6084679||Apr 2, 1999||Jul 4, 2000||Advanced Micro Devices, Inc.||Universal alignment marks for semiconductor defect capture and analysis|
|US6118185||Mar 4, 1999||Sep 12, 2000||Taiwan Semiconductor Manufacturing Company||Segmented box-in-box for improving back end overlay measurement|
|US6128089||Jul 28, 1998||Oct 3, 2000||International Business Machines Corporation||Combined segmented and nonsegmented bar-in-bar targets|
|US6130750||Aug 28, 1997||Oct 10, 2000||International Business Machines Corporation||Optical metrology tool and method of using same|
|US6137578||Jul 28, 1998||Oct 24, 2000||International Business Machines Corporation||Segmented bar-in-bar target|
|US6140217||Jul 16, 1998||Oct 31, 2000||International Business Machines Corporation||Technique for extending the limits of photolithography|
|US6146910||Feb 2, 1999||Nov 14, 2000||The United States Of America, As Represented By The Secretary Of Commerce||Target configuration and method for extraction of overlay vectors from targets having concealed features|
|US6160622||Jun 18, 1998||Dec 12, 2000||Asm Lithography, B.V.||Alignment device and lithographic apparatus comprising such a device|
|US6165656||Apr 20, 1999||Dec 26, 2000||Mitsubishi Denki Kabushiki Kaisha||Overlay error determination mark considering influence of aberration|
|US6384899||Feb 2, 2000||May 7, 2002||Asm Lithography B.V.||Lithographic projection apparatus|
|US6405096||Aug 10, 1999||Jun 11, 2002||Advanced Micro Devices, Inc.||Method and apparatus for run-to-run controlling of overlay registration|
|US6462818||Jun 22, 2000||Oct 8, 2002||Kla-Tencor Corporation||Overlay alignment mark design|
|US6612159||Aug 25, 2000||Sep 2, 2003||Schlumberger Technologies, Inc.||Overlay registration error measurement made simultaneously for more than two semiconductor wafer layers|
|US6664121||May 20, 2002||Dec 16, 2003||Nikon Precision, Inc.||Method and apparatus for position measurement of a pattern formed by a lithographic exposure tool|
|US6675053||Sep 11, 2002||Jan 6, 2004||Micron Technology, Inc.||Layout for measurement of overlay error|
|US6734549 *||Jul 2, 2002||May 11, 2004||Matsushita Electric Industrial Co., Ltd.||Semiconductor device having a device for testing the semiconductor|
|US6734971||Jun 26, 2001||May 11, 2004||Lael Instruments||Method and apparatus for self-referenced wafer stage positional error mapping|
|US6753120||May 21, 2002||Jun 22, 2004||Samsung Electronics Co., Ltd.||Alignment measuring method of photolithography process|
|US6921916||Jun 26, 2002||Jul 26, 2005||Kla -Tenocor Technologies Corporation||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US6985618||Jun 26, 2002||Jan 10, 2006||Kla-Tencor Technologies Corporation||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US7068833||Jun 27, 2001||Jun 27, 2006||Kla-Tencor Corporation||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US20010055720||Jun 7, 2001||Dec 27, 2001||Kabushiki Kaisha Toshiba||Alignment method, overlay deviation inspection method and photomask|
|US20030021465||Jun 26, 2002||Jan 30, 2003||Michael Adel||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US20030021466||Jun 26, 2002||Jan 30, 2003||Michael Adel||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US20030021467||Jun 26, 2002||Jan 30, 2003||Michael Adel||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US20030026471||Jun 26, 2002||Feb 6, 2003||Michael Adel||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US20030102440||Jun 7, 2002||Jun 5, 2003||Taek-Soo Sohn||Method of aligning a wafer in a photolithography process|
|US20050173634||Mar 2, 2005||Aug 11, 2005||Alan Wong||Optical metrology target design for simultaneous measurement of multiple periodic structures|
|US20060039595||Jul 11, 2005||Feb 23, 2006||Kla-Tencor Technologies Corporation||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US20060177120||Mar 30, 2006||Aug 10, 2006||Kla-Tencor Corporation||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|US20060204073||May 12, 2006||Sep 14, 2006||Kla-Tencor Corporation||Overlay marks, methods of overlay mark design and methods of overlay measurements|
|EP0818814A2||Jul 9, 1997||Jan 14, 1998||Kla Instruments Corp.||Overlay alignment measurement of semiconductor wafers|
|EP0947828A2||Mar 31, 1999||Oct 6, 1999||International Business Machines Corporation||Method and apparatus for improved inspection measurements|
|JPH1167631A||Title not available|
|1||Adel, et al., "Overlay Metrology and Control Method", U.S. Appl. No. 10/367,124, filed Feb. 13, 2003.|
|2||Bishop, et al, "The OMAG3 Reticle Set," Jul. 31, 2003, International SEMATECH, Technology Transfer #3074417A-ENG, pp. 1-26.|
|3||Claims from U.S. Appl. No. 10/950,172, filed Sep. 23, 2004.|
|4||Dirksen, et al., "Novel aberration monitor for optical lithography", Part of the SPIE Conference on Optical Microlithography XII, Santa Clara, CA Mar. 1999, SPIE vol. 3676, p. 77-86.|
|5||Farrar et al., "In-situ measurement of lens aberrations", Mar. 2000 Proceedings of SPIE vo. 4000, Optical Microlithography XIII.|
|6||Ghinovker, et al., "Overlay Marks, Methods of Overlay Mark Design and Methods of Overlay Measurements", U.S. Appl. No. 09/894,987, filed Jun. 27, 2001.|
|7||Hsu et al., "Characterizing lens distortion to overlay accuracy by using fine measurement pattern", Mar. 1999, SPIE vol. 3677.|
|8||International Search Report from related PCT application No. PCT/US03/04471, dated May 22, 2003 (5 pgs). [KLA1P081.WO].|
|9||Levinson et al., "Minimization of Total Overlay Errors on Product Wafers Using an Advanced Optimization Scheme", SPIE vol. 3051 (1997) p. 362-373.|
|10||Levinson, "Lithography Process Control", Tutorial Texts in Optical Engineering, vol. TT28, Chapter 5, pp. 96-107.|
|11||Normura, "Measurement of Wave-Front Aberrations in Lithography Lenses with an Overlay Inspection Tool", Optical Review No. 8, vol. 4 (2001) p. 227-234.|
|12||Rivera et al., "Overlay Performance on Tungsten CMP Layers Using the ATHENA Alignment System".|
|13||U.S. Appl. No. 10/367,124, filed Feb. 13, 2003; Office Action mailed Apr. 23, 2007 [KLA1P081].|
|14||U.S. Appl. No. 10/367,124, filed Feb. 13, 2003; Office Action mailed Oct. 4, 2007 [KLA1P081].|
|15||U.S. Office Action dated Oct. 10, 2006, U.S. Appl. No. 10/950,172.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7721248 *||May 23, 2007||May 18, 2010||International Business Machines Corporation||Circuit element function matching despite auto-generated dummy shapes|
|US7804994||Feb 13, 2003||Sep 28, 2010||Kla-Tencor Technologies Corporation||Overlay metrology and control method|
|US7808643||Dec 19, 2008||Oct 5, 2010||Nanometrics Incorporated||Determining overlay error using an in-chip overlay target|
|US7873504||May 7, 2007||Jan 18, 2011||Kla-Tencor Technologies Corp.||Computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout|
|US7876438||Jan 25, 2011||Kla-Tencor Technologies Corporation||Apparatus and methods for determining overlay and uses of same|
|US7876439 *||Jan 25, 2011||International Business Machines Corporation||Multi layer alignment and overlay target and measurement method|
|US7915907 *||Jun 25, 2007||Mar 29, 2011||Spansion Llc||Faulty dangling metal route detection|
|US7925486 *||Apr 12, 2011||Kla-Tencor Technologies Corp.||Computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout|
|US7970485 *||May 20, 2009||Jun 28, 2011||Winbond Electronics Corp.||Systems and methods for determining width/space limits for a mask layout|
|US8004315 *||Aug 23, 2011||Pdf Solutions, Inc.||Process for making and designing an IC with pattern controlled layout regions|
|US8107079||Jan 31, 2012||International Business Machines Corporation||Multi layer alignment and overlay target and measurement method|
|US8214771 *||Jan 8, 2009||Jul 3, 2012||Kla-Tencor Corporation||Scatterometry metrology target design optimization|
|US8243273||Jun 4, 2009||Aug 14, 2012||Kla-Tencor Corporation||Enhanced OVL dummy field enabling “on-the-fly” OVL measurement methods|
|US8339605||Nov 30, 2010||Dec 25, 2012||International Business Machines Corporation||Multilayer alignment and overlay target and measurement method|
|US8390808||Jul 13, 2012||Mar 5, 2013||Kla-Tencor Corporation||Enhanced OVL dummy field enabling “on-the-fly” OVL measurement methods|
|US8525993||Jan 29, 2010||Sep 3, 2013||Nanometrics Incorporated||Scatterometry measurement of asymmetric structures|
|US8829518||Sep 13, 2011||Sep 9, 2014||International Business Machines Corporation||Test structure and calibration method|
|US9182680||Feb 28, 2012||Nov 10, 2015||Kla-Tencor Corporation||Apparatus and methods for determining overlay of structures having rotational or mirror symmetry|
|US20030223630 *||Feb 13, 2003||Dec 4, 2003||Kla-Tencor Corporation||Overlay metrology and control method|
|US20070190811 *||Jan 19, 2007||Aug 16, 2007||Sung-Gyu Park||Method of forming patterns and/or pattern data for controlling pattern density of semiconductor devices and pattern density controlled semiconductor devices|
|US20070276634 *||Mar 13, 2007||Nov 29, 2007||Mark Smith||Computer-implemented methods, carrier media, and systems for creating a metrology target structure design for a reticle layout|
|US20080022248 *||May 23, 2007||Jan 24, 2008||Landis Howard S||Circuit element function matching despite auto-generated dummy shapes|
|US20080259334 *||Jun 23, 2008||Oct 23, 2008||International Business Machines Corporation||Multi layer alignment and overlay target and measurement method|
|US20080315906 *||Jun 25, 2007||Dec 25, 2008||Spansion Llc||Faulty dangling metal route detection|
|US20090116014 *||Dec 19, 2008||May 7, 2009||Nanometrics Incorporated||Determining Overlay Error Using an In-chip Overlay Target|
|US20090225295 *||May 20, 2009||Sep 10, 2009||Li-Ming Wang||Systems and methods for determining width/space limits for a mask layout|
|US20090303482 *||Jun 4, 2009||Dec 10, 2009||Vladimir Levinski||Enhanced Ovl dummy field enabling "on-the-fly" ovl measurement methods|
|US20100005442 *||Sep 15, 2009||Jan 7, 2010||Kla-Tencor Technologies Corporation||Apparatus and Methods for Determining Overlay and Uses of Same|
|US20100175033 *||Jan 8, 2009||Jul 8, 2010||Kla-Tencor Corporation||Scatterometry metrology target design optimization|
|US20110058170 *||Nov 9, 2010||Mar 10, 2011||International Business Machines Corporation||Multi layer alignment and overlay target and measurement method|
|US20110069314 *||Mar 24, 2011||International Business Machines Corporation||Multilayer alignment and overlay target and measurement method|
|US20110080585 *||Apr 7, 2011||Nanometrics Incorporated||Scatterometry Measurement of Asymmetric Structures|
|USRE45245||May 1, 2013||Nov 18, 2014||Kla-Tencor Corporation||Apparatus and methods for determining overlay of structures having rotational or mirror symmetry|
|WO2011043930A1 *||Sep 22, 2010||Apr 14, 2011||Nanometrics Incorporated||Scatterometry measurement of asymmetric structures|
|WO2016030255A3 *||Aug 19, 2015||Apr 21, 2016||Asml Netherlands B.V.||Metrology method, target and substrate|
|WO2016054581A1 *||Oct 2, 2015||Apr 7, 2016||Kla-Tencor Corporation||Verification metrology targets and their design|
|Cooperative Classification||G06F2217/12, G06F17/5068, Y02P90/265|
|Sep 20, 2004||AS||Assignment|
Owner name: KLA-TENCOR TECHNOLOGIES CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:COHEN, AVI;GHINOVKER, MARK;ADEL, MICHAEL E.;REEL/FRAME:015807/0074;SIGNING DATES FROM 20040810 TO 20040830
|Sep 19, 2011||FPAY||Fee payment|
Year of fee payment: 4
|Sep 18, 2015||FPAY||Fee payment|
Year of fee payment: 8