|Publication number||US7863708 B2|
|Application number||US 12/425,326|
|Publication date||Jan 4, 2011|
|Filing date||Apr 16, 2009|
|Priority date||Mar 31, 2006|
|Also published as||CN101461065A, CN101461065B, DE112007000802T5, US7521773, US8063442, US20070228518, US20090200606, US20110089488, WO2007117954A2, WO2007117954A3|
|Publication number||12425326, 425326, US 7863708 B2, US 7863708B2, US-B2-7863708, US7863708 B2, US7863708B2|
|Inventors||Hamza Yilmaz, Daniel Calafut|
|Original Assignee||Fairchild Semiconductor Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Non-Patent Citations (7), Referenced by (2), Classifications (19), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. application Ser. No. 11/396,362, filed Mar. 31, 2006 now U.S. Pat. No. 7,521,773, which is incorporated herein by reference in its entirety for all purposes.
The commonly assigned U.S. application Ser. No. 11/026,276, filed Dec. 29, 2004 is incorporated herein by reference in its entirety for all purposes.
The present invention relates to power device technology, and more particularly to improved edge termination for charge balance power devices.
The charge balance concept is a promising evolution in the power device technology. Some of the defining performance characteristics for the power switch are its on-resistance, breakdown voltage and switching speed. Depending on the requirements of a particular application, a different emphasis may be placed on each of these performance criteria. For example, in the mid to high voltage range (i.e., 60 to 2,000 volts), a conventional device suffers from high resistivity, since the drift region needs to be lightly doped in order for the device to sustain high voltages during the blocking state. The high resistivity of the drift region results in higher source-to-drain on-resistance RDSon, which in turn results in high power losses. Because of the inverse relationship between RDSon, and the breakdown voltage, improving the breakdown voltage performance of the device while maintaining a low RDSon poses a challenge.
Various charge balancing structures in the device drift region, including buried electrodes, opposite polarity pillars and floating regions, have been developed to address this challenge with varying degrees of success. The charge balancing techniques aim to maintain a substantially uniform electric field within the drift region in order to increase the breakdown voltage of the device. Thus, for the same breakdown voltage, the drift region can be higher doped thereby reducing RDSon.
However, one problem with the design of charge balance devices is the edge termination area. It is a challenge to achieve charge balance at the interface between the active region and the termination region since an opposing junction to couple to the last active cell can be difficult to implement. If all the active cells are identically charge balanced except at the active to termination interface region, then this interface region becomes the limiting factor in achieving high breakdown voltage. The edge termination breakdown at low current levels does not hinder device performance however, during high current avalanche events such as unclamped inductive load (UIL) switching, the limited area of the termination region relative to the active array cannot handle the power losses. This detrimentally impacts the safe operating area (SOA) of the device.
Thus, what is desirable is a structure and method that enable a high device blocking capability, low on-resistance, and high current handling capability, particularly the capability to sustain high avalanche current in the active to termination interface region.
In accordance with an embodiment of the invention, a field effect transistor (FET) includes a source electrode for receiving an externally-provided source voltage. The FET further includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region. During operation, one end of the resistive element is biased to the source voltage.
In one embodiment, the termination region includes a termination well of a first conductivity type extending to a first depth within a drift region of a second conductivity type, and the active region includes an active well of the first conductivity type extending to a second depth within the drift region, the first depth being deeper than the second depth.
In another embodiment, the termination well forms the other end of the resistive element.
In another embodiment, the termination well forms a ring surrounding the active region. The termination well includes a plurality of discontinuous well contact regions intermittently placed around the active region. The plurality of well contact regions are of the first conductivity type.
In another embodiment, a first interconnect layer extends over the active region and a portion of the termination region. A second interconnect layer, having a lower conductivity than the first interconnect layer, is configured to electrically connect the termination well to the first interconnect layer.
In yet another embodiment, an interconnect layer has a first portion extending over the active region and a second portion extending over the termination region. A dielectric layer partially insulates the first and second portions of the interconnect layer from one another, wherein the second portion of the interconnect layer forms a part of the resistive element.
In yet another embodiment, the second portion of the interconnect layer serves as a filed plate extending over the termination region.
A further understanding of the nature and the advantages of the invention disclosed herein may be realized by reference to the remaining portions of the specification and the attached drawings.
Embodiments of the present invention address the above problems and other problems by providing structures and methods that limit the current in the termination area during a UIL switching event. A resistive voltage division technique is employed in the termination region which reduces the amount of current that flows through the edge termination region during a high avalanche current event by progressively shifting an increasing percentage of the avalanche current from the edge termination region to the active cells. This technique minimizes power dissipation during UIL switching at the edge termination region and improves the SOA performance.
Trench 110 includes a gate electrode 122, and underlying shield electrode 114. In one embodiment, gate electrode 122 and shield electrode comprise polysilicon. Shield electrode 114 is insulated from adjacent regions by a shield dielectric 112, and gate electrode 122 is insulated from adjacent regions by gate dielectric 120. The gate and shield electrodes are insulated from each other by a dielectric layer 116 commonly referred to as an inter-poly dielectric or IPD. A metal layer 126 serves as a source contact to electrically contact source regions 108 and body region 104 via heavy body regions 106. A dielectric dome 124 over gate electrode 122 insulates source metal 126 from gate electrode 122.
The breakdown voltage of the MOSFET is typically limited by the cylindrical or spherical shape of the depletion region which is formed around the last diffusion junction at the edge of the die during the blocking state. Since this cylindrical or spherical breakdown voltage is lower than the parallel plane breakdown voltage in the active region of the device, the active region of the device is terminated so as to achieve a breakdown voltage for the device that is close to the active region breakdown voltage. Different termination techniques have been developed to spread the field more uniformly across the edge termination width in order to raise the breakdown voltage in the termination region to that of the active region. These include field plates, field rings, junction termination extension (JTE) and different combinations of these techniques.
A dielectric material 224 insulates source interconnect portions 226 and 227 from the gate electrode in trench 210. Dielectric material 224 also serves to partially insulate source interconnect portions 226 and 227 from one another. That is, source interconnect portions 226 and 227 are in part insulated from one another by dielectric 224, but are electrically connected together along a third dimension (not shown). By partially insulating source interconnect portions 226 and 227 from one another a high resistance path (depicted by resistor 228) is created. In one embodiment, source interconnect portions 226 and 227 are both from metal. In another embodiment, source interconnect portion 227 comprises polysilicon in order to obtain a higher resistance path. A number of other implementations for resistor 228 are discussed further below in reference to
In conventional termination designs, because all of the current during high current avalanche events flows through the p-isolation region, the termination structure is designed so as to minimize the resistance in the path from the p-isolation region through the source interconnect to the external source electrode. This is typically achieved by inclusion of a heavy body region in the P-isolation region where the source interconnect contacts the p-isolation region, and by use of wide contact openings for source interconnect to p-isolation contact. Further, the source interconnect portion contacting the p-isolation region is directly connected to the source interconnect portion in the active region. That is, unlike the gap created by insulation material 224 between the source interconnect portions 226 and 227 in
In direct contrast to conventional designs, embodiments of the invention significantly increase (rather than decrease) the resistance in the path from the p-isolation region through the source interconnect to the external source electrode (not shown). In one embodiment, the resistance in this path is several orders of magnitude higher than that in conventional designs. The higher resistance is shown symbolically by resistor symbol 228 in
Since the resistor value can be easily controlled, it is possible to tailor it to particular operating conditions and die sizes. A suitable metal or polysilicon (doped or un-doped) may be chosen for source interconnect portion 227 according to the resistive properties and resistance values desired. In one embodiment, in addition to other features, the size of the contact opening over the p-isolation region 204 and/or the doping concentration in the heavy body region 206 in p-isolation region 204 are adjusted to obtain the desired resistance. In yet another embodiment wherein the p-isolation well forms a ring around the active region, its inner heavy body region 206 is intermittently formed around the active region (i.e., is not a single continuous ring). The discontinuities create resistive paths within the p-isolation well 204. In one embodiment, a resistance value of 500 kΩ*μm per unit area of the termination region has shown optimal results as discussed below with respect to
As can be seen in
As can be seen in
In conventional designs where resistor 228 is absent, all of the avalanche current, even at high current levels, flows through the p-isolation region. However, during UIL switching events, since the energy of the inductive load (given by ½ I2L, where I stands for current and L stands for inductance) is finite, resistor 228 effectively distributes the energy between the termination region and the active cells, thus decreasing the likelihood that there would be a failure in the active cell region (i.e., latch-up) or in the termination region (i.e., current crowding and excessive heating). A significantly improved SOA performance is thus achieved. The amount of current shifting or division is set by the resistance value, which can be easily and accurately adjusted by modifying the various components and physical features in the path through the termination to the external source electrode.
In general, active interconnect 526 is made of highly conductive material. By coupling termination interconnect rings 527 to active interconnect 526 through thin interconnect links 532, a higher resistive path is created between the termination region and the active interconnect 526. In one embodiment, termination interconnect ring 527 is from the same highly conductive material as active interconnect 526, and interconnect links 532 are made of more resistive conductors thus forming part of the resistive path. In other embodiments, one or both of the termination interconnect ring 527 and interconnect links 532 are made of more resistive conductors such as low conductivity metallic compounds or polysilicon (doped or undoped) depending on the desired resistance value.
While the above provides a complete description of the preferred embodiments of the invention, many alternatives, modifications, and equivalents are possible. For example, the charge balanced structures described herein in the context of a MOSFET and in particular a shielded gate trench MOSFET. Those skilled in the art will appreciate that the same techniques can apply to other types of MOSFETs and power devices such as IGBTs and lateral gate MOSFETS, and more broadly to any power device which can benefit from limiting the current levels in the edge termination region. For this and other reasons, therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|U.S. Classification||257/551, 257/174, 257/154|
|Cooperative Classification||H01L29/41741, H01L29/7803, H01L29/0653, H01L29/7808, H01L29/7811, H01L29/0646, H01L29/456, H01L29/402, H01L29/407, H01L29/1095, H01L29/7813|
|European Classification||H01L29/78B2E, H01L29/78B2T, H01L29/78B2A, H01L29/78B2A6|