Slide 63 of 89
Operations are carried out in the eight S scalar registers and 8 64-word Vector registers. Vector length is specified in a register and a mask determines which operands participate in a vector operation. Address arithmetic is carried out in the 8 A registers.
Two sets of 64 temporary registers store scalars and addresses to minimize access time.
Instructions are buffered in 4 groups of 64 x16 bits.
It is remarkably similar to the 6600… and extended for vectors.
In addition to operations that operate on fixed strides, a scatter-gather mode is used such that each operand is pointed to by an address.
This basic vector architecture has been implemented in numerous other architectures, including Japan and minisupercomputers. About a dozen manufacturers have copied the “Cray-style’ vector architecture.