|Publication number||US6057205 A|
|Application number||US 09/014,862|
|Publication date||May 2, 2000|
|Filing date||Jan 28, 1998|
|Priority date||Jan 28, 1998|
|Publication number||014862, 09014862, US 6057205 A, US 6057205A, US-A-6057205, US6057205 A, US6057205A|
|Original Assignee||Texas Instruments - Acer Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (12), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a method to form the ragged poly-silicon (poly-Si) structure for the DRAM cell, and more particularly, to a method for making a ragged poly-Si capacitor in the high density DRAM-cell.
2. Description of the Prior Art
Each semiconductor's memory cell consists typically of a storage capacitor and an access transistor. Since the basic element in the semiconductor's Dynamic Random Access Memory (DRAM) device is the memory cell, the manufacture of the memory-cell is essential to the DRAM. In fact, a memory-cell is provided for each bit stored by a DRAM-device. Either the source or the drain of the access transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor-gate-electrode are connected respectively to the external connecting-lines called a bit-line and a word-line. The other terminal of the capacitor is connected to a reference-voltage.
With the advent of Ultra Large Scale Integrated (ULSI) DRAM devices, the size of the memory cells has become smaller and smaller such that the area available for a single memory cell has become very small. The manufacture of a DRAM memory cell includes the fabrication of a transistor, a capacitor and contacts to periphery circuits. The devices of small area in the DRAM cell are thus most important for the designer. The planar capacitor is widely used in DRAM memory cells because the planar capacitor is relatively simple to fabricate yet the area of the planar capacitance is too big for the large-scale semiconductor device. Planar capacitors have been traditionally used due to their ease of manufacture, but as the memory cells decrease in size, the area of the planar capacitance also decreases. For very small size memory cells, it is not suitable to use the planar capacitance. Specifically, as the size of the capacitor decreases, the capacitance of the planar capacitor also decreases and the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to α particle interference.
Additionally, as the capacitance decreases, the charge held by the storage capacitor must be refreshed often. A simple stacked capacitor can not provide sufficient capacitance, even though high dielectric Ta2 O5 is used as the insulator between the plates of the capacitor. Also, when the trench capacitor is used, the "gated diode leakage" resulting in the loss of the charge stored in the capacitor will make the capacitor fail to hold the charge, and then the logic level is missed. By reducing the thickness of the dielectric layer, the capacitance of the capacitor can also be improved. Yet, the problems related with using very thin dielectric materials and the yield have limited the usage. The stacked capacitor and the trench capacitor are developed to overcome the aforementioned problems.
If a better structure that can increase the capacitance of the capacitor is utilized, even though there may be a loss of charge, the sufficient charges in the capacitor can still be kept in the proper logic level. Moreover, once a better capacitor structure is proposed, its capacitance can be further improved by either using a thinner dielectric insulator or by selecting an insulator having a higher dielectric constant. Thus, a cylindrical capacitor using the Hemispherical Grained Si has been proposed (see "A NEW CYLIDRICAL CAPACITOR USING HEMISPHERICAL GRAINED Si FOR 256 Mb DRAMs", H. Watanabe et al., Tech Dig, December 1992, pp.259-262).
The structure of the capacitor over bit line (COB) cell with a hemispherical grain (HSG--Si) poly-silicon storage node has been developed (see "CAPACITOR-OVER-BIT LINE CELL WITH HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs", M. Sakao et al., Microelectronics Research Laboratories, NEC Corporation. In IEDM Tech Dig., December 1990,pp. 655-658). This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufactured by optical delineation. The HSG--Si used to increase the effective area of the electrode of the capacitor is deposited by low-pressure chemical vapor deposition method at the transition temperature from amorphous Si to the polycrystalline Si. The HSG--Si storage node can be fabricated by addition of two process steps, i.e. HSG--Si deposition and an etchback. A HSG--Si electrode node has been proposed (see "A NEW CYLINDRICAL CAPACITOR USING HEMISPHERICAL GRAIN Si FOR 256 Mb DRAMs", H. Watanabe et al., Microelectronics Research Laboratories, NEC Corporation). After the electrode structure is formed, a native oxide on the electrode surface is removed by a diluted HF solution. HSG--Si appears on the silicon surface by using the seeding method.
To increase the effective area of the simple storage node of a capacitor, a method for fabricating a capacitor on a semiconductor device is disclosed herein. The semiconductor has a bit line and the capacitor is located over the bit line. The method mentioned above including the following steps:
First, a first dielectric layer is form on the semiconductor device, in which the semiconductor device has a substrate. Next, a second dielectric layer is formed on the first dielectric layer. Sequentially, the first dielectric layer, the second dielectric layer and the semiconductor device are etched and a hole contacting the substrate is thus formed.
Next, a first conductive layer is formed in the hole and on the second dielectric layer. Sequentially, the first conductive layer is patterned to form a bottom electric electrode of the capacitor. Next, a third dielectric layer is formed on the first conductive layer to make a portion of the first conductive layer that is not covered by the third dielectric layer. The third dielectric layer and the first conductive layer are successively oxidized to form a silicon dioxide layer. The successive step is to remove the silicon dioxide layer. Thus, the third dielectric layer and the portion of the first conductive layer are etched untill the third dielectric layer on the top surface of the first conductive layer is removed. The silicon dioxide layer is removed by using HF solution as an etchant, which has an etching selectivity between oxide and poly-silicon of about 100 to 1. Next, a dielectric film on the third dielectric layer is patterned to form the dielectric film of the capacitor. Finally, a second conductive layer is patterned on the dielectric film to fabricate a top electric electrode of the capacitor.
The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which:
FIG. 1 illustrates a cross-sectional view of the semiconductor device having a substrate, a bit line, a MOSFET, and a word line;
FIG. 2 illustrates a cross-sectional view of the semiconductor device with two dielectric layers formed on the semiconductor device;
FIG. 3 shows a storage node defined in and on the semiconductor device to be the bottom electrode of the capacitor;
FIG. 4 shows a HemiSpherical Grain poly-silicon (HSG--Si) formed on the storage node and the semiconductor device;
FIG. 5 shows a silicon dioxide layer formed on the surface of the HSG--Si and the surface of the storage node;
FIG. 6 shows the silicon dioxide layer formed on the surface of the HSG--Si and the surface of the storage node removed;
FIG. 7 shows the HSG--Si on the top surface of the storage node removed; and
FIG. 8 shows a dielectric film is formed on the surface of the storage node as the dielectric film of the capacitor, and a second conductive layer formed on the surface of the dielectric film as the top electrode of the capacitor.
To increase the charge stored in the memory cell, the ragged poly-Si structure is used in enlarging the effective area of the capacitor in the memory cell without enlarging the area of the DRAM. A method for forming the ragged poly-silicon (poly-Si) structure in a high density DRAM cell is disclosed herein. The structure of the capacitor including the ragged poly-silicon structure includes (1) a ragged poly-silicon bottom storage node (2) a dielectric layer and (3) a top storage node. For those mentioned above, the capacitance of the memory cell is significantly increased as compared to the conventional stacked capacitor. The dielectric layer is formed along the surface of the ragged poly-silicon (poly-Si) bottom storage node.
In the preferred embodiment of the present invention, a single crystal silicon substrate with a crystallographic orientation of <100> is provided, and the thick field oxide (FOX) region formed in a conventional process provides isolation between devices on the silicon substrate.
Sequentially, a silicon dioxide layer is formed on the top surface of the substrate to serve as the gate oxide for subsequently forming the Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The silicon dioxide layer is formed by using an oxygen ambient, at a temperature of about 700-1100° C. in one embodiment. In the other embodiment, the oxide layer may be formed using any suitable oxide chemical procedures, the thickness of the FOX is about 3000-8000 angstroms and the thickness of the silicon dioxide layer is approximately 15-200 angstroms.
The following step is to form a doped poly-silicon layer over the FOX region and a silicon dioxide layer by a Low Pressure Chemical Vapor Deposition (LPCVD) process. In this embodiment, the first poly-silicon layer is about 500-2000 angstroms in thickness. The silicide layer, such as tungsten silicide, is then formed on the first poly-silicon layer. Next, standard photolithography and the etching steps are used to form a gate structure and a local interconnection. Subsequently, the active regions (i.e., the source and the drain electrodes of the MOSFETs) are formed by a well-known process such as implanting appropriate impurities. After forming a metal layer on the substrate, well known patterning and etch processes are used to etching the metal layer to form a bit line. The fabrication of the ragged poly-Si capacitor described herein includes many steps that are well known in the art. The Widely used processes such as photolithography masking and etching are well known in the art and are used extensively herein without a related discussion of these well-known technologies. The cross-sectional view of the wafer being processed by aforementioned steps is shown in FIG. 1, which shows the bit line 90, the word line 92, the MOSFET 94 and the first dielectric layer 96. The first dielectric layer 96 is preferably formed by borophosphosilicate glass (BPSG) or TEOS-oxide. The other cross-sectional view is shown in FIG. 2, in which the second dielectric layer 98 is formed on the first dielectric layer 96, and the third dielectric layer 99 is formed on the second dielectric layer 98. The second dielectric layer 98 is preferably the CVD (Chemical Vapor Deposition) oxide, and the third dielectric layer is preferably formed of silicon nitride. The thickness of the third dielectric layer 99 is preferably about 500-2000 angstroms.
The next step is to utilize the widely used processes, such as the photolithography masking and etching, to define the capacitor-over-bit line (COB) storage node. Referring to FIG. 3, a contact hole 100 is formed in the first dielectric layer 96, the second dielectric layer 98 and the third dielectric layer 99 by patterning and etching. A first conductive layer 105 is formed over and in the contact hole 100 and on the third dielectric layer 99. The first conductive layer 105 is preferably formed using conventional LPCVD process. The thickness of the first conductive layer 105 as measured over the third dielectric layer 99 is preferably in the range of 300-1000 angstroms. The first conductive layer 105 is preferably the doped polysilicon. A photoresist is patterned on the first conductive layer 105 and then an etching process is utilized, by using the photoresist as an etching mask to etch the first conductive layer 105. The following step is to strip the photoresist, and then the storage node is formed.
Turning now to FIG. 4, an undoped HemiSpherical Grains silicon (HSG--Si) layer 120 is formed on the first conductive layer 105 and the third dielectric layer 99. The next step is to slightly etch the first conductive layer 105 and the HSG--Si layer 120, then a low temperature wet oxidation in oxygen ambient is used to form the thermal oxide on the surface of the first conductive layer 105 and the HSG--Si layer 120. In this embodiment, the oxidation temperature is about 700-950° C. and the oxidation process preferably continues for 5-120 minutes. Referring to FIG. 5, the oxide layer 124 on the surface of the first conductive layer 105 is thicker than that of the HSG--Si layer 120, due to the difference oxidation rate between the doped poly-silicon and the undoped HSG--Si. The diluted HF solution is used to remove the oxide layer 124. As shown in FIG. 6, the oxide layer 124 is removed, and a plurality of grooves 130 are created in the first conductive layer 105. The high etching selectivity between oxide and polysilicon (the relative susceptibility is about 100 to 1) is used to achieve this end. This procedure causes grooves 130 to be formed in the polysilicon, and the grooves 130 have a depth of the order of 100-1000 angstroms. The residual HSG--Si islands are left on the paysilicon layer and the silicon nitride layer after the procedure. Because the diluted HF solution cannot etch silicon nitride, there is not a groove in the third dielectric layer 99. The next step is to etch back the HSG--Si layer 120 by dry etching. The portions of the first conductive layer 105 without the coverage of the HSG--Si layer 120 are etched. Referring to FIG. 7, the HSG--Si layer 120 on the top surface of the first conductive layer 105 and the third dielectric layer 99 is removed, meanwhile, the depth of the grooves 130 is increased by the dry etching. The HSG--Si layer 120 on the vertical surface of the first conductive layer 105 can be remain because a portion of the grains of the HSG--Si layer 120 on the vertical surface acts as a mask. The etchant of the aforementioned dry etching process can be SiCl4 /Cl2, SF6, HBr/O2, or BCl3 /Cl2.
Turning next to FIG. 8, the dielectric film 140 is deposited and patterned on the surface of the first conductive layer 105 and the third dielectric layer 99. The third dielectric layer 99, if utilized, is preferably removed by wet etching. In the preferred embodiment, the etchant is preferably hot phosphoric acid, which dissolves the third dielectric layer 99 but not layer 98. A dielectric film 140 is then deposited on the exposed surface of the first conductive layer 105. The dielectric film 140 is preferably formed of either a double film of nitride/oxide film, a triple film of oxide/nitride/oxide or any other high dielectric film including tantalum oxide (Ta2 O5),BST, PZT, etc. If Ta2 O5, BST, or PZT are used as the dielectric film 140, then a composition layer which is composed of barrier metal layer/metal layer must be formed on the first conductive layer 105 before the dielectric film 140 is formed. This is because these dielectric films must be used in a metal-insulator-metal (MIM) structure. Further, if the third dielectric layer 99 is utilized and dissolved, as is preferred, then the dielectric wraps around the gouged-out surface and under much of the lower surface of conductive layer 105, thereby increasing further the surface area of the first plate of this capacitor which is being formed. After the dielectric film 140 is deposited, a second conductive layer 145 is deposited by using a conventional LPCVD process over the dielectric film 140. The second conductive layer 145 provides a top storage electrode and is formed of doped polysilicon, in-situ doped polysilicon, aluminum, copper, tungsten or titanium. In addition, if Ta2 O5, BST, PZT, or PLZT are used to serve as the dielectric film 140, then the second conductive layer 145 must be metal to form a metal-insulator-metal (MIM) structure. Thus, a semiconductor capacitor, which comprises a second conductive layer 145 as its top storage electrode, a dielectric 140, and a first conductive layer 105 as the bottom storage electrode is formed. Thus, the cell plate of the DRAM cell is fabricated.
Therefore, the present invention improves the performance of the capacitor. As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention is illustrative of the present invention rather than being limiting on the present invention. Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modification may be made without departing from the spirit which is intended to be limited solely by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5670405 *||Jan 30, 1997||Sep 23, 1997||Vanguard International Semiconductor Corporation||Method of making a tooth shaped capacitor using ion implantation|
|US5696014 *||Mar 11, 1994||Dec 9, 1997||Micron Semiconductor, Inc.||Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch|
|US5723373 *||Nov 18, 1996||Mar 3, 1998||Powerchip Semiconductor Corp.||Method of making porous-Si capacitors for high density drams cell|
|US5817544 *||Jan 16, 1996||Oct 6, 1998||Olin Corporation||Enhanced wire-bondable leadframe|
|US5840606 *||Nov 25, 1997||Nov 24, 1998||United Semiconductor Corp.||Method for manufacturing a comb-shaped lower electrode for a DRAM capacitor|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6127221 *||Sep 10, 1998||Oct 3, 2000||Vanguard International Semiconductor Corporation||In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application|
|US6174766 *||Jun 17, 1998||Jan 16, 2001||Nec Corporation||Semiconductor device and method of manufacturing the semiconductor device|
|US6274428 *||May 12, 1999||Aug 14, 2001||Acer Semiconductor Manufacturing Inc.||Method for forming a ragged polysilicon crown-shaped capacitor for a memory cell|
|US6433378||Feb 11, 2000||Aug 13, 2002||Micron Technology, Inc.||Integrated circuits having material within structural gaps|
|US6451650||Apr 20, 2001||Sep 17, 2002||Taiwan Semiconductor Manufacturing Company||Low thermal budget method for forming MIM capacitor|
|US6500730||Nov 17, 2000||Dec 31, 2002||Micron Technology, Inc.||Method for filling structural gaps and integrated circuitry|
|US6706591||Jan 22, 2002||Mar 16, 2004||Taiwan Semiconductor Manufacturing Company||Method of forming a stacked capacitor structure with increased surface area for a DRAM device|
|US6787877||Dec 27, 2002||Sep 7, 2004||Micron Technology, Inc.||Method for filling structural gaps and integrated circuitry|
|US7023042||Jan 12, 2004||Apr 4, 2006||Taiwan Semiconductor Manufacturing Company, Ltd.||Method of forming a stacked capacitor structure with increased surface area for a DRAM device|
|US20040142531 *||Jan 12, 2004||Jul 22, 2004||Taiwan Semiconductor Manufacturing Company||Method of forming a stacked capacitor structure with increased surface area for a DRAM device|
|WO2002045131A2 *||Nov 28, 2001||Jun 6, 2002||Infineon Technologies North America Corp.||Process flow for capacitance enhancement in a dram trench|
|WO2002045131A3 *||Nov 28, 2001||May 15, 2003||Infineon Technologies Corp||Process flow for capacitance enhancement in a dram trench|
|U.S. Classification||438/398, 257/E21.648, 257/E21.013, 438/255|
|International Classification||H01L21/02, H01L21/8242|
|Cooperative Classification||H01L27/10852, H01L28/84|
|Jan 26, 1998||AS||Assignment|
Owner name: TEXAS INSTRUMENTS - ACER INCORPORATED, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WU, SHYE-LIN;REEL/FRAME:008982/0275
Effective date: 19971231
|Sep 6, 2000||AS||Assignment|
Owner name: TSMC-ACER SEMICONDUCTOR MANUFACTURING CORPORATION,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ACER SEMICONDUCTOR MANUFACTURING INC.;REEL/FRAME:011087/0473
Effective date: 20000630
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TSMC-ACER SEMICONDUCTOR MANUFACTURING CORPORATION;REEL/FRAME:011122/0153
Effective date: 20000630
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