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hw-breakpoints: Separate constraint space for data and instruction br…
…eakpoints There are two outstanding fashions for archs to implement hardware breakpoints. The first is to separate breakpoint address pattern definition space between data and instruction breakpoints. We then have typically distinct instruction address breakpoint registers and data address breakpoint registers, delivered with separate control registers for data and instruction breakpoints as well. This is the case of PowerPc and ARM for example. The second consists in having merged breakpoint address space definition between data and instruction breakpoint. Address registers can host either instruction or data address and the access mode for the breakpoint is defined in a control register. This is the case of x86 and Super H. This patch adds a new CONFIG_HAVE_MIXED_BREAKPOINTS_REGS config that archs can select if they belong to the second case. Those will have their slot allocation merged for instructions and data breakpoints. The others will have a separate slot tracking between data and instruction breakpoints. Signed-off-by: Frederic Weisbecker <email@example.com> Acked-by: Paul Mundt <firstname.lastname@example.org> Cc: Will Deacon <email@example.com> Cc: Mahesh Salgaonkar <firstname.lastname@example.org> Cc: K. Prasad <email@example.com> Cc: Benjamin Herrenschmidt <firstname.lastname@example.org> Cc: Paul Mackerras <email@example.com> Cc: Ingo Molnar <firstname.lastname@example.org>
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