c-d.hailfinger.devel.2006 at gmx.net
Wed Jun 20 17:15:17 CEST 2007
can you look at the mail below?
can you apply the attached patch and then post a LB boot log on
a GA-M57SLI with BIOS_DEBUG or BIOS_SPEW and additionally dmasg and
lspci -vvvnx from the same boot? This would help greatly to clear
up the resource confusion.
On 23.05.2007 00:22, Carl-Daniel Hailfinger wrote:
> On 08.05.2007 22:45, ST wrote:
>> Hi Carl-Daniel
>>> could someone with a GA-M57SLI please post a lspci -vvvnx to the
>>> list, preferably both under LB and factory BIOS? I'm trying to
>>> verify some code I wrote.
>> Sorry for the delay, but i somehow missed your message.
>> Attached to this mail you will find the output of lspci -vvvnx under the
>> original bios version f8 and under linuxbios updated from today (2007-05-08).
> Verifying a LB port is very interesting work and leads to lots of
> head scratching.
> Here is a list of more problems, some really serious.
>> -00:06.0 0604: 10de:0370 (rev a2) (prog-if 01 [Subtractive decode])
>> +00:06.0 0604: 10de:0370 (rev a2) (prog-if 00 [Normal decode])
> Does changed decode mean anything?
>> - Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
>> + Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
> SERR- changed to SERR+.
>> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
>> Latency: 0
>> - Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
>> + Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> sec-latency=32 probably had a reason in the vendor BIOS. Why change?
>> - I/O behind bridge: 00008000-00008fff
>> + I/O behind bridge: 0000f000-00000fff
> The LinuxBIOS I/O range is backwards (end before start) and has
> a different size. Same for other I/O ranges.
>> - Memory behind bridge: fb000000-fcffffff
>> + Memory behind bridge: fff00000-000fffff
> The LinuxBIOS memory range is backwards and has a different size.
> Same for other mem ranges.
>> - Prefetchable memory behind bridge: 50000000-500fffff
>> + Prefetchable memory behind bridge: fff00000-000fffff
> Same here.
>> Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-
>> - BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
>> + BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
> Parity- changed to Parity+.
> Other devices had the same classes of problems. I'd like to get
> an explanation for all of the above to be able to correct some
> of the differences.
> I have at least one patch for the GA-M57SLI lined up, answering
> the above questions will lead to more of them.
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