|Publication number||US7426148 B2|
|Application number||US 11/294,861|
|Publication date||Sep 16, 2008|
|Filing date||Dec 5, 2005|
|Priority date||Jan 26, 2004|
|Also published as||US6992939, US20050162915, US20060083090|
|Publication number||11294861, 294861, US 7426148 B2, US 7426148B2, US-B2-7426148, US7426148 B2, US7426148B2|
|Inventors||Stephen R. Porter|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (66), Classifications (12), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 10/764,675, filed on Jan. 26, 2004, now U.S. Pat. No. 6,992,939.
1. Field of the Invention
This present invention relates generally to the field of integrated circuit design and, more specifically, to a memory device design that facilitates detection of short circuits between bitlines in a memory device.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Memory devices, such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”), may include arrays of memory cells that each store a bit or element of data. Each data bit or element may represent a logical low (“0”) or a logical high (“1”), which may correspond to a voltage level of a circuit element disposed within the memory cell. As an example, a voltage level close to ground may be representative a logical low or “0” and a voltage level close to a supply voltage for the memory device may be representative of a logical high or “1.” The electrical paths that carry the voltage representing a bit or element of data to and from memory cells may be referred to as a data line, a bitline or a digit line. A DRAM device may additionally include wordlines, which enable a plurality of bitlines to be accessed so that data may be written to or read from corresponding memory cells.
Some memory devices have complementary bitlines for each memory cell. The complementary bitlines are designed so that they are always in opposite logic states. In other words, when the data stored in the memory cell corresponds to a logical “0”, the data on the complimentary bit line for that cell will be a logical “1” and vice versa. Sense amplifier circuits may be coupled between complimentary bitlines to improve access to data stored in the memory cell. A sense amplifier amplifies a signal corresponding to the difference between two voltage levels. The output of a sense amplifier provides an early indication of whether the logic level of a given memory cell is going to change or remain unchanged.
As integrated circuit feature sizes continue to get smaller, distances between adjacent bitlines continue to decrease as well. Accordingly, there is an increasing possibility that adjacent device features, such as bitlines, may be short circuited to each other. In other words, adjacent bitlines may be unintentionally connected to each other during manufacture. If a short circuit develops between adjacent bitlines, the DRAM device may produce erroneous data when installed in an electronic device such as a computer system or the like. The electronic device in which the defective DRAM is installed may experience performance problems or may not function at all.
Advantages of the invention may become apparent upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
The system 10 may include a power supply 14, which may comprise a battery or batteries, an AC power adapter and/or a DC power adapter. Various other devices may be coupled to the processor 12 depending on the functions that the system 10 performs. For example, an input device 16 may be coupled to the processor 12 to receive input from a user. The input device 16 may comprise a user interface and may include buttons, switches, a keyboard, a light pen, a mouse, a digitizer and/or a voice recognition system or the like. An audio or video display 18 may also be coupled to the processor 12 to provide information to the user.
A communications port 22 may be adapted to provide a communication interface between the electronic device 10 and peripheral devices 24. The peripheral 24 may include a docking station, expansion bay or other external component. Furthermore, an RF sub-system/baseband processor 20 may be coupled to the processor 12 to provide wireless communication capability.
The processor 12, the non-volatile memory 28 and the volatile memory 26 may be implemented as one or more integrated circuit components. Also, the processor 12, the non-volatile memory 28, and the volatile memory 26 are examples of integrated circuit components that may include sense amplifier circuits constructed in accordance with embodiments of the present invention.
In the first bank 201 of sense amplifiers, the sense amplifier 202 is connected to a digit line 216 and a complementary digit line 218. The sense amplifier 204 is connected to a digit line 220 and a complementary digit line 222. The sense amplifier 206 is connected to a digit line 224 and a complementary digit line 226. In
In the second bank 203 of sense amplifiers, the sense amplifier 208 is connected to a digit line 228 and a complementary digit line 230. The sense amplifier 210 is connected to a digit line 232 and a complementary digit line 234. The sense amplifier 212 is connected to a digit line 236 and a complementary digit line 238.
Embodiments of the present invention may be employed to determine whether a short exists between adjacent digit lines. A short 214, shown as a dashed line in
In the normal operation of the DRAM device 200, the sense amplifiers in the first bank 201 and the second bank 203 would typically be fired simultaneously. The simultaneous firing of both banks of sense amplifiers results in reduced capacitive coupling between digit lines and helps to increase operational speed of the DRAM device 200. However, the simultaneous firing of all sense amplifiers may mask the presence of short circuits such as the short 214. To assist in identifying the short 214, the memory cells associated with the first bank 201 of sense amplifiers and digit lines may be programmed to contain the same data value. The memory cells associated with the second bank 203 of sense amplifiers and digit lines may be programmed to contain the opposite or complementary data value. For example,
Instead of being fired simultaneously, the first bank 201 of sense amplifiers may be fired prior to the second bank 203 of sense amplifiers. The time delay between the firing of the first bank 201 of sense amplifiers and the second bank 203 of sense amplifiers may be in the range of 2 to 15 nanoseconds. This process may be applied to the DRAM device 200 as part of a test mode during their manufacture.
When the first bank 201 of sense amplifiers is fired, a short between adjacent lines (such as the short 214) will cause the digit line associated with the second bank 203 of sense amplifiers to be pulled in the direction of the data value on the digit line associated with the first bank 201 of sense amplifiers. For example, the short 214 will cause the data value on the digit line 228 (a logical “1”) to be pulled in the direction of the value of the data on the digit line 216 (a logical “0”). This biasing of the data value on the digit line associated with the second bank 203 of sense amplifiers will cause the expected data value (i.e. the value to which that digit line was initially programmed) to be incorrect. Thus, the short 214 can be identified and possibly corrected during the manufacturing process.
At block 404, the memory cells associated with the first bank of sense amplifiers and digit lines is programmed to a known data value. The first bank of sense amplifiers may correspond to the first bank 201 of sense amplifiers illustrated in
At block 408, the first bank of sense amplifiers is fired or activated. As shown at blocks 410 and 412, a delay is interposed between the firing of the first bank of sense amplifiers and the firing of the second bank of sense amplifiers. This delay allows data on the digit lines associated with the second bank of sense amplifiers to be pulled away from its true value if one of those digit lines is shorted to an adjacent digit line associated with the first bank of sense amplifiers. Thus, the delay will cause the data on the digit line associated with the second bank of sense amplifiers to be misread.
At block 414, the presence of short circuits between digit lines associated with the first and second banks of sense amplifiers is determined. This determination may be made by reading the data from the digit lines associated with the second bank of sense amplifiers and comparing that data to an expected value (i.e. the value to which the digit line was initially programmed). If any of the digit lines associated with the second bank of sense amplifiers does not produce the expected value of data, it is likely that that digit line is shorted to the adjacent digit line associated with the first bank of sense amplifiers. The short circuit may then be corrected. If the defect cannot be corrected, the device in which the short circuit occurred may be scrapped before being incorporated into a product. At block 416, the process ends.
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4692900 *||Mar 25, 1985||Sep 8, 1987||Fujitsu Limited||Semiconductor memory device having block pairs|
|US5144583 *||Jan 4, 1990||Sep 1, 1992||Kabushiki Kaisha Toshiba||Dynamic semiconductor memory device with twisted bit-line structure|
|US5253207 *||Nov 18, 1991||Oct 12, 1993||Fujitsu Limited||Semiconductor memory device having dual ports|
|US5274276||Jun 26, 1992||Dec 28, 1993||Micron Technology, Inc.||Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit|
|US5289416 *||Jan 14, 1992||Feb 22, 1994||Hitachi, Ltd.||Semiconductor integrated device and wiring correction arrangement therefor|
|US5297087||Apr 29, 1993||Mar 22, 1994||Micron Semiconductor, Inc.||Methods and devices for accelerating failure of marginally defective dielectric layers|
|US5304506||Mar 10, 1993||Apr 19, 1994||Micron Semiconductor, Inc.||On chip decoupling capacitor|
|US5331594||Oct 10, 1991||Jul 19, 1994||Sharp Kabushiki Kaisha||Semiconductor memory device having word line and bit line test circuits|
|US5369317||Dec 11, 1992||Nov 29, 1994||Micron Technology, Inc.||Circuit and method for controlling the potential of a digit line and in limiting said potential to a maximum value|
|US5428621 *||Sep 21, 1992||Jun 27, 1995||Sundisk Corporation||Latent defect handling in EEPROM devices|
|US5440516||Jan 27, 1994||Aug 8, 1995||Sgs-Thomson Microelectronics, Inc.||Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same|
|US5606528 *||Nov 6, 1995||Feb 25, 1997||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device allowing data rewriting electrically|
|US5673231 *||Jun 21, 1996||Sep 30, 1997||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device in which leakage current from defective memory cell can be suppressed during standby|
|US5754486 *||Feb 28, 1997||May 19, 1998||Micron Technology, Inc.||Self-test circuit for memory integrated circuits|
|US5793686||Nov 25, 1996||Aug 11, 1998||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output|
|US5892720||Oct 27, 1997||Apr 6, 1999||Micron Technology, Inc.||Semiconductor memory with test circuit|
|US5901078||Jun 19, 1997||May 4, 1999||Micron Technology, Inc.||Variable voltage isolation gate and method|
|US5903502||Nov 25, 1997||May 11, 1999||Micron Technology, Inc.||Variable equilibrate voltage circuit for paired digit lines|
|US5917767 *||Dec 18, 1997||Jun 29, 1999||Sharp Kabushiki Kaisha||Semiconductor storage device|
|US5963485 *||Aug 19, 1998||Oct 5, 1999||Stmicroelectronics, Inc.||Method and apparatus for bit line recovery in dynamic random access memory|
|US5963867 *||Aug 16, 1995||Oct 5, 1999||Qualcomm Inc.||Graphic tools for interactively planning a wireless network|
|US5982672 *||Oct 18, 1996||Nov 9, 1999||Samsung Electronics Co., Ltd.||Simultaneous data transfer through read and write buffers of a DMA controller|
|US5982682 *||Mar 12, 1998||Nov 9, 1999||Micron Technology, Inc.||Self-test circuit for memory integrated circuits|
|US6002623||Jan 22, 1999||Dec 14, 1999||Micron Technology, Inc.||Semiconductor memory with test circuit|
|US6021072 *||Jul 27, 1998||Feb 1, 2000||Motorola, Inc.||Method and apparatus for precharging bitlines in a nonvolatile memory|
|US6026042 *||Apr 10, 1998||Feb 15, 2000||Micron Technology, Inc.||Method and apparatus for enhancing the performance of semiconductor memory devices|
|US6046931 *||Sep 9, 1998||Apr 4, 2000||Evsx, Inc.||Method and apparatus for a RAM circuit having N-nary output interface|
|US6114878||Feb 13, 1998||Sep 5, 2000||Micron Technology, Inc.||Circuit for contact pad isolation|
|US6141272||Sep 2, 1999||Oct 31, 2000||Micron Technology, Inc.||Method and apparatus for programmable control signal generation for a semiconductor device|
|US6219293||Sep 1, 1999||Apr 17, 2001||Micron Technology Inc.||Method and apparatus for supplying regulated power to memory device components|
|US6249468||Oct 5, 1999||Jun 19, 2001||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device with switching element for isolating bit lines during testing|
|US6266287||Feb 23, 2000||Jul 24, 2001||Micron Technology, Inc.||Variable equilibrate voltage circuit for paired digit lines|
|US6269037||Feb 23, 2000||Jul 31, 2001||Micron Technology, Inc.||Variable equilibrate voltage circuit for paired digit lines|
|US6275409||Apr 16, 1999||Aug 14, 2001||Micron Technology, Inc.||Methods of operating a dynamic random access memory|
|US6297998||Oct 5, 2000||Oct 2, 2001||Micron Technology, Inc.||Method and apparatus for programmable control signal generation for a semiconductor device|
|US6297999 *||Feb 16, 2001||Oct 2, 2001||Fujitsu Limited||Semiconductor memory device and method for setting stress voltage|
|US6337820 *||Oct 12, 2000||Jan 8, 2002||Fujitsu Limited||Dynamic memory device performing stress testing|
|US6351425||Dec 7, 2000||Feb 26, 2002||Micron Technology, Inc.||Method and circuit for high voltage programming of antifuses, and memory device and computer system using same|
|US6355508||Apr 12, 1999||Mar 12, 2002||Micron Technology, Inc.||Method for forming electrostatic discharge protection device having a graded junction|
|US6365937||May 12, 1999||Apr 2, 2002||Micron Technology, Inc.||Electrostatic discharge protection device having a graded junction|
|US6385098||Apr 17, 2001||May 7, 2002||Micron Technology, Inc.||Method and apparatus for supplying regulated power to memory device components|
|US6396300||Dec 17, 1999||May 28, 2002||Micron Technology, Inc.||Circuit and method for contact pad isolation|
|US6434065 *||Jul 25, 2001||Aug 13, 2002||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device of low power consumption|
|US6438049||Feb 24, 1999||Aug 20, 2002||Micron Technology, Inc.||Variable equilibrate voltage circuit for paired digit lines|
|US6445610||Aug 14, 2001||Sep 3, 2002||Micron Technology, Inc.||Variable voltage isolation gate and method|
|US6483760 *||Apr 13, 2001||Nov 19, 2002||Samsung Electronics Co., Ltd.||Semiconductor memory integrated circuit operating at different test modes|
|US6496421||Aug 31, 2000||Dec 17, 2002||Micron Technology, Inc.||Distributed cell plate and/or digit equilibrate voltage generator|
|US6501674 *||Aug 31, 2001||Dec 31, 2002||Oki Electric Industry Co., Ltd.||Semiconductor memory and its driving method|
|US6515923||Nov 15, 2001||Feb 4, 2003||Matrix Semiconductor, Inc.||Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays|
|US6515925||Mar 15, 2001||Feb 4, 2003||Micron Technology, Inc.||Balanced sense amplifier control for open digit line architecture memory devices|
|US6535412 *||Apr 24, 2000||Mar 18, 2003||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device capable of switching output data width|
|US6576960||Mar 11, 2002||Jun 10, 2003||Micron Technology, Inc.||Electrostatic discharge protection device having a graded junction and method for forming the same|
|US6593218||Aug 9, 2001||Jul 15, 2003||Micron Technology, Inc.||Electrostatic discharge protection device having a graded junction and method for forming the same|
|US6628144||Mar 28, 2002||Sep 30, 2003||Micron Technology, Inc.||Circuit and method for contact pad isolation|
|US6704238||Aug 20, 2002||Mar 9, 2004||Renesas Technology Corp.||Semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading|
|US6735133 *||Jun 12, 2003||May 11, 2004||Renesas Technology Corp.||Semiconductor memory circuit having normal operation mode and burn-in test mode|
|US6753133 *||Mar 7, 2002||Jun 22, 2004||Elpida Memory, Inc.||Method and manufacturing a semiconductor device having a ruthenium or a ruthenium oxide|
|US6781897||Aug 1, 2002||Aug 24, 2004||Infineon Technologies Flash Ltd.||Defects detection|
|US6781902 *||Jul 9, 2003||Aug 24, 2004||Renesas Technology Corp.||Semiconductor memory device and method of testing short circuits between word lines and bit lines|
|US6922939 *||Jul 25, 2003||Aug 2, 2005||John Richard Moorhouse||Fishing lure|
|US6992939 *||Jan 26, 2004||Jan 31, 2006||Micron Technology, Inc.||Method and apparatus for identifying short circuits in an integrated circuit device|
|JP2001195900A||Title not available|
|JP2001243794A *||Title not available|
|JP2003281891A *||Title not available|
|JPH02244485A *||Title not available|
|JPS63281293A *||Title not available|
|U.S. Classification||365/201, 714/724, 365/205, 365/206|
|International Classification||G11C11/34, G11C7/00, G11C29/02|
|Cooperative Classification||G11C11/401, G11C29/025, G11C29/02|
|European Classification||G11C29/02E, G11C29/02|