|Publication number||US7118389 B2|
|Application number||US 10/871,330|
|Publication date||Oct 10, 2006|
|Filing date||Jun 18, 2004|
|Priority date||Jun 18, 2004|
|Also published as||CN1722535A, CN1722535B, US20050282411|
|Publication number||10871330, 871330, US 7118389 B2, US 7118389B2, US-B2-7118389, US7118389 B2, US7118389B2|
|Inventors||David K. Fork, Jurgen Daniel|
|Original Assignee||Palo Alto Research Center Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (3), Referenced by (34), Classifications (42), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to integrated circuit (IC) devices, and more particularly to structures for connecting IC devices to host systems.
Electronic packages are interconnectable housings for integrated circuit (IC) devices. Packaging is performed after a semiconductor wafer has been fabricated according to known semiconductor processing techniques, and then “diced” (i.e., cut) into individual IC “chips”. Typically, packaging involves placing one or more IC chips into a package housing, electrically connecting the IC chip to contact pads formed on the housing, e.g., by wire bonding these contact pads to corresponding input/output (I/O) die bonding pads formed on the IC chip(s), and then covering the IC chip and wire bonds for protection. The housings typically include multiple leads, pins, or bumps that are connected by conductive traces to the contact pads, and are arranged in a predetermined pattern such that the packaged IC chip can be tested by applying test signals to the leads/pins/bumps using a test fixture. Faulty IC chips are thus identified and discarded, while IC chips that pass this testing process are subsequently mounted (e.g., soldered) onto a corresponding contact site of another host system printed circuit board (PCB). If a packaged IC subsequently fails, the faulty IC can be removed from the host system by heating the solder to remove the faulty IC, cleaning the PCB contact site, and then resoldering a new packaged IC onto the contact site.
A problem associated with the conventional practice of packaging IC chips prior to testing is that the process of packaging damaged or otherwise non-functional IC chips significantly increases overall production costs. Currently, there are few chip-scale socket solutions capable of testing IC chips prior to packaging. Instead, most IC test socket technology consists of zero insertion force (ZIF) sockets, which are designed to facilitate the insertion and removal of a dual in-line package or pin grid array package without special tools. As such, these conventional ZIF socket solutions require packaging of each IC chip before they can be used, which increases overall manufacturing costs and thus reduces profitability.
Therefore, compliant, reworkable IC chip connections are a highly desired technology for testing and burning in the IC chips prior to packaging. In addition to making assembly and rework simpler and faster, such connections could facilitate the circumvention of tariffs on imported computer parts (e.g., lap top computers can be shipped separately from their processors, and hence get taxed as parts rather than as completed computer systems).
Flip-chip technology is growing in popularity because of its high input/output density capability, increased chip-packaging density, and excellent electrical performance. Solder-bumped, flip-chip technology has been well established since IBM developed the C4 process. In this process, solder bumps were formed on under-bump metallurgy (UBM) pads on the chip and joined to matching metal pads on the substrate by a reflow process. Because the established technique involves difficult and expensive processes to implement, new low-cost techniques for flip chip connections were sought.
Recently, the stud-bump bonding (SBB) technology, which is based on the wire-bonding technology, has been developed as a very attractive solution for a low-cost flip-chip technology. With SBB technology, gold stud bumps are placed on the die bond pads of IC chips through a modification of the “ball bonding” process used in conventional wire bonding. In ball bonding, the tip of the gold bond wire is melted to form a sphere. The wire-bonding tool presses this sphere against the aluminum bond pad, applying mechanical force, heat, and ultrasonic energy to create a metallic connection. The wire-bonding tool next extends the gold wire to the connection pad on the board, substrate, or lead frame, and makes a “stitch” bond to that pad, finishing by breaking off the bond wire to begin another cycle. For gold stud bumping, the first ball bond is made as described, but the wire is then broken close above the ball. The resulting gold ball with truncated wire, or “stud bump”, remains on the bond pad to provide a permanent, reliable connection through the aluminum oxide to the underlying metal. This technology has several advantages: UBM process is not necessary, bumping cost is low, and fine-pitch and chip-level bumping is possible.
Gold stud bump flip chip technology offers several advantages over conventional IC packaging. The bumping equipment, a wire bonder or dedicated stud bumper, is widely available and well characterized. Since stud bumps are formed by wire bonders, they can be placed anywhere a wire bond might be placed. They can easily achieve pitches of less than 100 microns and be placed on pads of less than 75 microns. Since stud bumping can be done on a wire bonder, it does not require wafers or under-bump metallization (UBM). Single, off-the-shelf die can be bumped and flipped without pre-processing. This makes the stud bump flip chip model fast, efficient, and flexible for product development, prototyping and low to medium volume production, while easy to scale up to high volume wafer-based production with automated equipment.
Although stud bumping is fairly well developed, what is not yet established is a connection socket that can receive stud bumps in a reliable and reworkable manner.
Therefore, what is needed is a compliant and reworkable connection socket for electrically connecting stud bumped IC devices to a host system (e.g., a testing system, or a PCB of an electronic device).
The present invention is directed to a socket that facilitates solderless connection of an electronic device (e.g., an integrated circuit (IC) chip) to a host system (e.g., a printed circuit “motherboard” of an electronic system such as a digital computer, or a printed circuit test board of a testing system). In particular, the present invention is directed to a socket that provides a reliable, reworkable electrical connection to a stud bump (or other metal wire column or similar metal structure extending from the electronic device) when the electronic device is mounted onto the host system. The present invention is also directed to an assembly including the electronic device and host system, and to an array of sockets arranged to receive a corresponding array of stud bumps.
According to an aspect of the invention, the socket includes a three-dimensional (e.g., cylindrical or cubical) hollow metal frame that is either supported by an underlying structure or free-standing that is formed by plating metal over a patterned template structure. The metal frame includes side walls that extend away from the underlying host substrate, and a contact structure located at the upper (i.e., free) end of the side walls. The contact structure defines an opening through which a stud bump can be inserted into a central chamber of the metal frame, which is surrounded by the side walls of the metal frame. The side walls and/or the contact structure are formed such that when the tip end of the stud bump is inserted into the central chamber, at least one of the base structure and the sidewall of the stud bump abuts the contact structure at two or more contact points, thereby ensuring that if one contact point has an intermittent loss of contact or increase in resistance, the other contact point(s) continue to handle the electrical load. Accordingly, the present invention provides a mechanism for electrically and mechanically connecting a “stud bumped” electronic device to a host system without solder, and with compliance that accommodates thermal expansivity mismatch, mechanical imperfections, and in a manner that adsorbs mechanical shock. In addition, the present invention facilitates reworking a packaged integrated circuit without having to heat the part, clean, and resolder.
According to an aspect of the present invention, socket fabrication includes forming a layer of negative-acting resist material (e.g., a negative, epoxy-based photoresist material such as SU-8, which is produced, for example, by MicroChem Corp. of Newton Mass., USA) adjacent to a contact pad exposed on a surface of the host system substrate (e.g., PCB), and then masking the upper surface of the negative-acting resist material layer such that a predetermined pattern of the resist material is exposed through the mask. The exposed negative-acting resist material is then illuminated through the patterned opening, thereby developing a region of the negative-acting material that corresponds to a desired patterned template structure. The developed regions of the negative-acting resist material exhibits reentrant sidewalls (i.e., such that the cross-section of the sidewall at the lower end is thinner than at the upper end). The non-exposed portion of the negative-acting resist material is then removed using known techniques, thereby exposing the patterned template structure. The metal frame is then plated over the exposed surface of the patterned template structure using known electroplating or electroless plating techniques. Thus, in this embodiment, the resulting socket utilizes a metal frame to provide electrical contact between the stud bump and the host system, and the patterned template structure to support the metal frame. According to an alternative embodiment, the patterned template structure is formed using an elastomeric material, such as Silicone (poly-dimethylsiloxane (PDMS)).
According to another embodiment, a socket includes a substantially cylindrical, relatively thick main wall surrounding a central cavity, and several relatively narrow, flexible membranes extending from the main wall into the central cavity. In one embodiment, the main wall and membranes are formed by fabricating a nonconductive, patterned template structure using, e.g., SU-8, and then made conductive by forming an external metal shell (frame) by electroplating or electroless plating. During subsequent use, the tip end of the stud bump enters the central chamber and contacts one or more of the membranes, causing the contacted membranes to bend toward the main wall. The lateral positioning accuracy of the stud bump can be more relaxed in this embodiment because of the relatively high flexibility of the membranes.
According to an alternative embodiment of the present invention, the patterned template structure is removed (e.g., dissolved or etched) after the metal frame is formed. In particular, a portion of the plating mask is formed on the patterned template structure to produce an opening that exposes the patterned template material after the plating process is completed. The patterned template material is then removed through this opening to produce a socket structure that includes only a free-standing metal frame on the host substrate, which provides a connector having less stress and more flexibility than the retained structure. In one exemplary embodiment, the free-standing metal frame includes dual, coaxial side walls that are separated by a groove, and the contact structure of the socket is provided by upper edges of the inner side wall. In other embodiments, the metal frame includes one or more contiguous vertical side walls surrounding a hollow central cavity, and a horizontal upper wall that defines several cantilevered contact structures having fixed ends connected to the side walls, and free ends extending over the central cavity. Slits or other openings are defined between the cantilevered contact structures, through which the sacrificial patterned template material is removed, e.g., by dissolution or plasma etching. During subsequent use, the tip end of the stud bump enters the central cavity by pressing downward against one or more of the cantilevered contact structures, causing the contacted structures to bend downward into the central cavity.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:
According to an aspect of the present invention that is described below in additional detail, contact structure 115 is formed such that when tip 157 of stud bump 150 is inserted into central chamber 125, base section 151 and/or elongated body 152 of stud bump 150 abut contact structure 115 at multiple contact points. This multiple contact objective is achieved by providing several contact protrusions 116 that extend from side wall 112 toward opening 117. In particular, contact structure 115 is formed such that opening 117 defines a clover-like shape, with contact protrusions 116 forming convex portions of the clover shape that extend relatively close to central axis X, and concave portions 118 of contact structure 115 being located relatively far from central axis X. By providing multiple contact protrusions 116 arrayed around opening 117 in this manner, socket 100 ensures reliable electrical contact between stud bump 150 and socket 100, even if one contact point experiences an intermittent loss of contact, or increase in resistance.
Referring to the upper portion of
Socket 100 includes a patterned template structure 120 formed on an upper surface 231 of host system 230, and metal frame 110 comprises a metal layer formed (e.g., plated) over an outer surface of patterned template structure 120. As described in additional detail below, patterned template structure 120 is formed from a negative-acting photoresist material, and in the present embodiment comprises a continuous wall structure (i.e., a generally annular wall or a contiguous set of wall sections) surrounding central chamber 125. Note that central chamber 125 is substantially symmetrical around and defines central axis X, which in turn extends substantially perpendicular to surface 231 of host system 230. Metal frame 110 includes an outer base portion 111 formed on surface 231, an outer side wall 112-1 formed on an outside surface of template structure 120 and extending between lower end portion 111 and an upper end 114, an upper wall (contact structure) 115 extending over an upper end of patterned template structure 120, an inner side wall 112-2 formed on an inside surface of template structure 120 and extending downward from an inner edge of upper wall 115, and an inner base portion 119 connected to a lower edge of inner side wall 112-2 and formed on surface 231. Upper wall 115 defines clover shaped opening 117, as shown in
Note that host system 230 includes one or more contact pads (e.g., outer contact pad 232 and inner contact pad 233) exposed on upper surface 231 and contacted by at least one of outer base portion 111 and inner base portion 119 of metal frame 110. Host system 230 is constructed according to known printed circuit board (PCB) techniques to include a series of conductors 234 that are embedded in an insulating material 235 (e.g., CR4) for transmitting electrical signals between socket 100 and selected system electronics (not shown). In one embodiment, these system electronics include test equipment that is configured to transmit and/or receive test signals utilized by electronic device 210 according to known techniques.
In accordance with an embodiment of the present invention, patterned template structure 120 is formed from a negative acting photoresist material (e.g., SU-8) in the manner described in detail below. When such a negative acting material is used, the resulting wall structure exhibits a relatively narrow thickness W1 adjacent to its lower end (i.e., adjacent to upper surface 231 of host system 230), and a relative wide thickness W2 adjacent to its upper end (i.e., adjacent upper wall 115). This reentrant wall shape makes the overall size of socket 100 wider near upper end 114 than adjacent to base portion 111, which, in combination with the tapered shape of stud bump 150, allows stud bump 150 to center to socket 100 as stud bump 150 is inserted into central chamber 125, thus allowing contact pressure on stud bump 150 to develop as well.
In an alternative embodiment (not shown), the patterned template structure can be formed using an elastomeric material, such as Silicone (poly-dimethylsiloxane (PDMS)), but such a patterned structure may not provide the advantages of the reentrant wall shape described above.
In one embodiment, stud bump 150 is approximately 25 microns in length, and adjacent stud bumps in the predetermined pattern are separated by approximately 100 to 500 microns. In one embodiment, the depth of central chamber 125 of each socket 100 (i.e., measured along central axis X; see
In an exemplary embodiment, the area of each socket 100 of array 300 is approximately 150 by 150 microns. The realizable pitch of such an array would be on the order of several hundred microns. For area array interconnect this would be able to accommodate approximately one thousand sockets 100 on a 1 cm×1 cm die, although the present inventors envision the use of their invention on dies considerably smaller than 1 cm2. For example, many components in handheld devices (e.g., personal digital assistants) are on the order of a fraction to a few square millimeters.
Preliminary calculations suggest that the assembly connections between the stud bumps (pins) and sockets would be highly reliable and substantially shock resistant. Assuming a coefficient of friction of 0.5, and four contact points per pin/socket connection, the insertion force for a 30 pin/socket array would be about 12 grams. The mass of the silicon die for such a part is only on the order of a few milligrams. A rudimentary model of the device is summarized below in Table 1. The computed properties indicate that it would take a shock of hundreds or thousands of g's to dislodge the IC chip from the host system, thereby indicating that socket array 300 provides a highly reliable connection structure. Note that one could always include a simple retaining clip or some corner bonds on the part (IC) or host to further improve the shock resistance of the socketed part, while still keeping it fairly easy to replace a failed part if needed.
Rudimentary Socket Mechanical Model
Height: 200 um
Spring Constant: 0.04 gm/um
Width: 50 um
Contact Force: 0.20 gm
Thickness: 10 um
Insertion Force: 12.0 gm
Deformation: 5 um
Contacts per pin: 4
Pin Spacing: 258 microns
Chip Area: 2 mm2
Chip Mass: 0.00233 gm
Number of Pins: 30
Dislodge acceleration: 5132 g's
Chip Thickness: 0.5 mm
Material Modulus: 250 GPa
Friction Coefficient: 0.5
Si density: 2.33 gm/cm3
In addition to providing a highly reliable and shock-resistant solderless connection structure, socket array 300 accommodates thermal expansivity mismatch and mechanical imperfections of the associated stud bump pattern, thereby facilitating repeatable connections between electronic device 210 and host system 230 under a variety of conditions, some of which are described below with reference to
An exemplary manufacturing process for producing socket 100 (described above) will now be described with reference to
As indicated in
Placing resist onto a high aspect, reentrant structure, such as the various socket structures proposed herein, might be considered problematic. Spray coated resist could be considered as one option. Recent discussions have revealed, however, that equipment has been developed for reliably and inexpensively coating parts with electrodeposited resist. In this process, photoresist coats any metal surface that is electrically connected to the cathode of the resist depositing system.
There are a couple of ways that sockets of the present invention could be used for test or burn-in for purposes of verifying an IC chip, and then producing a complete metallurgical contact through soldering. One possible method involves tinning either the stud bump, the socket, or both the stud bump and socket with plated solder, and then reflowing the solder once the IC chip performance is verified.
Sockets produced in accordance with the present invention are fairly scalable to smaller dimensions and higher density than those of the exemplary embodiments discussed above. For example, the stud bumps could be replaced with plated columns, and the lateral dimensions of the socket could be scaled down. The limit on scaling may stem from the tolerances of the components, and the placement accuracy of the tool that brings the parts together.
Further, while the exemplary embodiments described above are directed to sockets having clover-shaped openings, other socket structures may be produced that incorporate the spirit and scope of the present invention. Several such alternative socket structures are introduced below with reference to
Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention. For example, while several sockets are described above with specific reference to cylindrical side walls, those skilled in the art will recognize that such side walls can be replaced with other contiguous wall arrangements such as oval walls and a contiguous series of straight walls arranged, for example, to form a square, pentagonal, or hexagonal structure. In addition, the specific contact structure geometries indicated in
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|International Classification||H05K3/32, H01R12/00|
|Cooperative Classification||H01L2224/81899, H01L2224/81193, G01R31/2863, H05K2201/0367, H01L2924/014, H01L24/11, H01L2224/81052, H01L2224/16, H01L2924/01013, H01L2924/01079, H01R12/718, H01L24/81, H01L24/90, H01L2224/81801, H05K3/326, H01L2924/01078, H01L2224/13144, H01L2924/01004, H01L2924/01043, H01L2924/01005, G01R1/0466, H01L2924/01082, H01L2224/1134, H01L2924/00013, H01L2924/01002, H05K2201/0969, H01L2924/01033, H01L2924/0105, H01L2924/14, H01L2924/01015, H05K2201/10734, H01L2924/01006, H01L2924/10253|
|European Classification||H01L24/11, H01L24/90, H01L24/81, H01R23/72K3, H05K3/32C2, G01R1/04S3D3|
|Jun 18, 2004||AS||Assignment|
Owner name: PALO ALTO RESEARCH CENTER INCORPORATED, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FORK, DAVID K.;DANIEL, JURGEN;REEL/FRAME:015496/0619
Effective date: 20040616
|May 1, 2007||CC||Certificate of correction|
|Feb 18, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Mar 21, 2014||FPAY||Fee payment|
Year of fee payment: 8