|Below is a simple block
diagram of the frequency counter.
The switch is shut for 1 second and then opened.
The number of pulses occuring in that 1 second are counted and displayed as the frequency.
|More detail is shown below.
The unknown frequency is applied to one input of the AND gate.
The other input is taken high for 1 second.
The number of pulses which appear at the output of the gate in that 1 second are counted and displayed as the frequency of the input signal.
The signal to be measured is usually squared and then amplified or attenuated as required.
|The binary counters count
from zero up to 9 and then reset to zero.
As the first counter (which counts UNITS) resets on the count of 9, a CARRY pulse is sent to the next counter (which counts TENS).
When the count reaches 99 both counters reset to zero and a carry pulse is sent out from the second counter to a HUNDREDS counter, if required.
As the counter outputs are in binary form they must be converted to a form suitable for driving the 7 segment displays.
This is done by BCD to 7 segment decoders.(BCD = binary coded decimal).
|At the end of the
1 second count the result is to be stored ready for display in LATCHES.
The latches are enabled by a pulse which occurs at the end of the 1 second count pulse and the count is stored in the latches and appears on the display.
Once the data has been stored and displayed the counters are reset to zero ready for the next count.
This is done by a RESET pulse which occurs immediately after the latch enable pulse.
|The next diagram shows how a delayed pulse is obtained from a previous pulse by a process of differentiation, inversion and clipping.|
|The last diagram shows a
crystal oscillator and logic control unit which generates the gating pulses.
The pulses can be of selectable width enabling the frequency to be displayed in Hz, kHz or MHz.
The logic control unit also provides latch enable and counter rest signals.
It also selects the decimal point position.
Copyright Graham Knott 2004