Image Number 5 for United States Patent #5049998.
A circuit and method for improving picture quality by interpolation in a digital video camera or in an image processing system. A preferred embodiment performs interpolation of a video signal from a CCD image pickup device. The circuit includes a first pitch (pixel) delay circuit 20, a 2-decimation circuit, a second pitch delay circuit 30 and a third pitch delay circuit 40. The circuit further includes a first adder and multiplier 50 connected to the outputs of the second pitch delay circuit and the 2-decimation circuit, a second adder and multiplier 60 connected to an output of the third pitch delay circuit and an output of the 2-decimation circuit and an adder 70 for combining the output of circuits 10, 50 and 60 to a clock signal. The adder 70 also samples the combined signal in response to the clock signal and holds the sampled signal for output of a picture signal of improve quality.