|Publication number||US6385253 B1|
|Application number||US 09/459,755|
|Publication date||May 7, 2002|
|Filing date||Dec 10, 1999|
|Priority date||Dec 10, 1999|
|Also published as||CA2393165A1, EP1236323A1, WO2001043383A1|
|Publication number||09459755, 459755, US 6385253 B1, US 6385253B1, US-B1-6385253, US6385253 B1, US6385253B1|
|Inventors||James L. Swisher|
|Original Assignee||Next Level Communications|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (19), Classifications (20), Legal Events (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The advent of the Internet and the demand for bandwidth has created the need for telecommunications systems which are able to provide high speed digital connections to and from a subscriber's residences. Because of the large amount of twisted wire pair cables which have been deployed for telephone service over many decades, there is a tremendous incentive to reuse these cables to provide high speed data services in addition to telephone services.
A number of techniques have been developed for transmitting high speed digital data signals over twisted wire pairs and include Integrated Digital Services Network (ISDN) technologies, Asymmetric Digital Subscriber Line (ADSL) technologies, Rate Adaptive Digital Subscriber Line (RADSL) technologies and Very High Speed Digital Subscriber Line (VDSL) technologies.
Of these technologies, VDSL provides the highest data rates to and from the subscriber, and can potentially provide data rates of 52 Mb/s over loop lengths of 3,000 ft. However, in transmitting such high speed signals over twisted wire pair, the loss is quite substantial and is not equal over the frequency range in which the signals are transmitted.
In addition, the loss depends heavily on the loop length, and it is not possible to use a constant slope amplifier to equalize the VDSL signal. Furthermore, the circuit that performs the equalization is typically located at the subscriber side of the network, and cannot easily be accessed by the network operator.
For the foregoing reasons, there is a need for a method and apparatus which provides for equalization and reliable reception of a VDSL signal.
In the present invention a Very High Speed Digital Subscriber Line (VDSL) signal is received from a twisted wire pair drop cable, and an equalization circuit provides additional gain in the high end of the VDSL band in order to compensate for the higher losses on the twisted wire pair at those frequencies.
In a preferred embodiment, the additional amplification is realized through the use of a resonator circuit. The resonator circuit can be switched in and out of the gain block using a field effect transistor.
In a preferred embodiment, a determination can be made as to whether the equalization is necessary, and the circuit selectively switched in or out depending on the results of the determination.
In a preferred embodiment the total power received is measured and a determination is made that the higher frequencies have been severely attenuated.
These and other features and objects of the invention will be more fully understood from the following detailed description of the preferred embodiments which should be read in light of the accompanying drawings.
The accompanying drawings, which are incorporated in and form a part of the specification, illustrate the embodiments of the present invention and, together with the description serve to explain the principles of the invention.
In the drawings:
FIG. 1 illustrates a Very High Speed Digital Subscriber Line (VDSL) transmission system;
FIG. 2 illustrates a VDSL spectral allocation;
FIG. 3 illustrates a block diagram of the Analog Front End (AFE);
FIG. 4 illustrates a slope amplifier circuit of the AFE of FIG. 3;
FIG. 5 illustrates the various operating modes of the AFE slope amplificater circuit;
FIGS. 6A, 6B, 6C and 6D illustrate the frequency roll-off for different loop lengths;
FIG. 7 illustrates the transfer function of the AFE slope amplifier circuit; and
FIG. 8 illustrates the result of slope amplification applied to a received VDSL signal.
In describing a preferred embodiment of the invention illustrated in the drawings, specific terminology will be used for the sake of clarity. However, the invention is not intended to be limited to the specific terms so selected, and it is to be understood that each specific term includes all technical equivalents which operate in a similar manner to accomplish a similar purpose.
With reference to the drawings, in general, and FIGS. 1 through 8 in particular, the apparatus of the present invention is disclosed.
FIG. 1 shows a Very High-Speed Digital Subscriber line (VDSL) transmission system. The VDSL transmission system can be part of a broadband transmission. FIG. 1 illustrates the VDSL transmission system as part of a full service access system. A Broadband Digital Terminal (BDT) 100, which is typically located in a central office, may also be placed in a remote location. The BDT 100 interfaces voice services from a Public Switched Telecommunications Network (PSTN) as well as video and data services from an Asynchronous Transfer Mode (ATM) network through its network interface unit (NIU), which is not illustrated. Voice, video and data services are transported to a Universal Service Access Multiplexor (USAM) 110 using an optical fiber link 120. An Optical Distribution Unit (ODU) 105 provides the connectivity between the BDT 10 and the USAM 110.
The USAM 100 can be located in the field as part of the central office configuration or in the customer premises, typically in an apartment building. The USAM 100 includes a VDSL Transceiver Unit (VTU) modem 115, which is referred to as a VTU-C modem. The VTU-C modem 115 supports both analog phone services and high speed data by multiplexing both signals into the same transmission medium, which is a twisted wire pair 130.
At the residence, the Network Interface Device (NID) 150, which contains a filter, separates the voice signal from the data signal. The voice signal is distributed within the home on the in-home telephone wiring to the telephone set 174, while the data signal can be sent to a residential gateway (RG) 172, which can support video 176, computer 178 or voice services.
FIG. 2 shows one embodiment of a VDSL spectral allocation. The twisted wire pair spectrum is divided into sub-bands with each sub-band carrying a particular service. The lower band 200 is reserved for the Plain Old Telephone Service (POTS) and occupies the spectrum from 0 to 3 kHz. Next to the POTS spectrum is an Integrated Services Digital Network (ISDN) band 210 which can provide data services at a basic rate of 144 kbps.
The upstream link 220 ranges from approximately 317 kHz to 965 kHz centered at 641.25 kHz. In a preferred embodiment, the symbol rate in the upstream link 220 is fixed at 540 kbaud with three possible bit rates of 1.08 Mbps, 2.16 Mbps and 3.24 Mbps using QPSK, 16-QAM and 64-QAM modulation, respectively. The downstream link 230 ranges from approximately 1.5 MHz to 9.3 MHz allowing bit rates from 9.72 Mbps to 25.92 Mbps.
FIG. 3 illustrates a block diagram of an Analog Front End (AFE) of a VDSL network interface present in the RG 172. The RG 172 includes a VTU modem 115, known as a VTU-R modem. The AFE is part of the VTU-R modem 115 and interfaces the twisted wire pair 130. For downstream signal reception, the VDSL signal passes through a POTS separation High Pass Filter (HPF) 345 so as to filter out Direct Current (DC), ringing and voice band signals from the VDSL signal. The filtered signal then passes through a line protection 343 and a line isolation transformer 340 before being presented to a diplexer 330. The diplexer 330 performs upstream and downstream frequency separation. A line receiver 317 will pass or amplify the received signal with slope compensation, depending on the line condition. This operation is controlled by a gain/slope control 316 which will be described in further detail with respect to FIG. 4. In a preferred embodiment, the gain/slope control 316 receives commands from a micro-controller to control the amplification.
The output of the line receiver 317 is filtered by a Band Pass Filter (BPF) 315 to prevent out of band energy from affecting the dynamic range of an Automatin Gain Controller (AGC) Amp 313 and to prevent aliasing. In a preferred embodiment, the bandpass filtering is carried out by high-pass and then low-pass filtering the signal. The AGC Amp 313 boosts the signal to maximize the dynamic range at an Analog to Digital Converter (ADC) 310, such as a BCM 6010 manufactired by Broadcom. A Group Delay Equalizer (GDE) 311 corrects the phase distortion of the amplified signal before it reaches the ADC 310 for conversion into a digital signal.
In a preferred embodiment, a micro-controller (not illustrated), such as the MPC860, can be used along with the ADC 310 in setting the operating mode of the gain slope control 316 based on the received power. The use of the micro-controller with the ADC 310 will be described with respect to the power measurement method.
In the upstream direction a Digital to Analog Converter (DAC) 300, such as a BCM 6010 manufactured by Broadcom, converts the digital signal into an analog one. A buffer 301 converts the differential signal into a single ended signal. In a preferred embodiment, the output of the GDE 311 is passed to the transmit Low Pass Filter (LPF) 303 which is part of a diplexer with transition frequency at 1.2 MHz. The transmit LPF 303 is used as an anti-aliasing filter. A line driver 305 amplifies the upstream signal to approximately 0 dBm and converts it into a differential signal.
FIG. 4 shows an AFE slope amplifier circuit. This circuit represents the gain/slope control 316 and the line receiver 317 of FIG. 3. An input stage 400 of the AFC slope amplifier circuit is composed of a Resistor and Capacitor (RC) circuit and a common emitter circuit with feedback. The input stage 400 acts as an input buffer to the AFE slope amplifier circuit. A transistor Q3 of the input stage 400 can be of the type MMBT3904LT1 or QN2222.
A first switching circuit 430 can activate a first RC network 410 depending on a binary signal RX_ATTN. A second switching circuit 440 is also controlled by the binary signal RX_ATTN. The second switching circuit 440, upon receiving a binary ‘1’ at its input port, activates a second RC network 420. In a preferred embodiment, low Resistance Drain Source (RDS) Field Effect Transistors (FETs) are used as transistors Q2 and Q9 of the first switching circuit 430 and the second switching circuit 440, respectively. These transistors can be the FDV303N manufactured by Fairchild.
In a preferred embodiment, the feedback of the common emitter of the input stage 400 includes an inductor L9 of module 415, which can be coupled to at least one RC network.
When active, the first RC network 410 couples to inductor L9 of module 415 to form a resistor, inductor and capacitor (RLC) circuit with the inductor and capacitor (LC) part determining the resonant frequency and the resistor (R) reducing both the gain and the Q factor of the circuit, when increased.
When the second RC network 420 is activated along with the first RC network 410, the second RC network 420 adds capacitance to the RLC circuit formed by the first RC network 410 and the inductor L9 of module 415, thus additionally decreasing the resonant frequency.
An output stage 450 of the AFC slope amplifier circuit is an emitter follower with unity gain. Transistor Q1 of the output stage 450 can be of the same type as transistor Q5, transistor Q10 and transistor Q3.
Table 1 presents possible values for the components used in the AFE slope amplifier circuit for it to perform amplification. However, these values are in no way intended to limit the scope of the invention. As one skilled in the art would recognize, these components can have various values or configurations, or different components may be used without departing from the scope of the current invention.
possible values of the components
The activation of the first RC network 410 and the second RC network 420 is determined by the operating mode set for the AFE slope amplifier circuit, as depicted in FIG. 5. The AFE slope amplifier circuit compensates for the frequency roll off caused by long lengths of the twisted wire pair cables as shown in FIG. 6.
FIG. 5 illustrates the four different operating modes of the AFE slope amplifier circuit. The binary control signal in column 500 contains, in a preferred embodiment, 2 bits which can be set to ‘0’ or ‘1’ to control the ON/OFF states of the first switching circuit 430 and the second switching circuit 440 listed in columns 510 and 530, respectively. The present invention can be used to provide flat gain to the input signal. In this embodiment, only circuit 410 is activated.
In a preferred embodiment of this invention, the operating mode can be determined based on a power level of the signal across the band. A power measurement is performed on the received signal and depending on the measured power level, a predetermined operating mode is selected.
In an alternative embodiment, the operating mode is determined based on the loop length. Column 550 of FIG. 5 lists the loop length corresponding to each of the four operating modes.
In an alternate embodiment, remote provisioning from a management system can be applied to set the operating mode of the AFE slope amplifier circuit.
In a preferred embodiment, the power measurement is performed using a micro-controller, such as the MPC860, running a C code or any other code supported by the micro-controller, along with the ADC 310. In this embodiment, the digital samples obtained from the ADC 310 are processed to determine the peak power of the received signal. In a preferred embodiment, the system assumes known cable and transmitter characteristics and calculates a power value which is then compared to the peak power of the received signal. This value is used to control the AGC amplifier 313 as illustrated in FIG. 3 by the connection between the ADC 310 and the AGC control 312. The micro-controller can access the registers inside the ADC 310 to read this value and send a control command to the gain/slope control 316 for setting the appropriate operating mode.
FIGS. 6A, 6B, 6C and 6D show the frequency roll-off for different loop lengths. Curve 600 in FIG. 6A shows the attenuation of a 500-ft long loop. The total attenuation across the whole band is less than 10 dB. The attenuation curve for a 1 kft long loop is depicted in curve 610 of FIG. 6B. The attenuation across the transmission band is less than 20 dB. The attenuation curves for the loop lengths of 2 kft and 3 kft are represented by curve 630 in FIG. 6C and curve 650 in FIG. 6D, respectively. The attenuation for 2 kft long loop is less than 35 dB while the attenuation for 3 kft long loop is more than 50 dB.
FIG. 7 illustrates an example slope amplifier transfer function. The example slope amplifier transfer function presents a positive slope on frequencies below the resonant frequency, which in a preferred embodiment is around 8 MHz, while the frequencies above the resonant frequency are amplified with a negative slope. Furthermore, the example slope amplifier transfer function provides no amplification at approximately 0 and 25 MHz, a positive amplification between 0 and 25 MHz, and a negative amplification below 25 MHz. In an alternative embodiment, other resonant frequencies can be obtained by adjusting the component values of the RLC circuit of FIG. 4.
FIG. 8 shows the result of the slope amplification applied on a received VDSL signal. Curve 800 is a received VDSL signal without slope amplification. The frequency roll-off results in severe attenuation at high frequency. Curve 810 is a slope amplified VDSL signal. The high end of the VDSL spectrum is more amplified than the low end of the spectrum. Also redrawn in FIG. 8, is the slope amplifier transfer function represented by curve 700.
Although this invention has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made, which clearly fall within the scope of the invention. The invention is intended to be protected broadly within the spirit and scope of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3914557 *||Apr 11, 1973||Oct 21, 1975||Bell Telephone Labor Inc||Multifrequency tone detecting arrangement|
|US4132863 *||Dec 20, 1977||Jan 2, 1979||Bell Telephone Laboratories, Incorporated||Automatic gain and return loss compensating line circuit|
|US4228323 *||Jan 31, 1979||Oct 14, 1980||Bell Telephone Laboratories, Incorporated||Variable loop length compensated barrier circuit|
|US4453037 *||Dec 28, 1981||Jun 5, 1984||Mostek Corporation||Loop length compensation circuit|
|US5929896||Jun 21, 1996||Jul 27, 1999||Inline Connection Corporation||RF broadcast system utilizing internal telephone lines|
|US5953373 *||Jul 12, 1996||Sep 14, 1999||Samsung Electronics Co., Ltd.||Equalizing circuit and method for data communication terminal equipment|
|US6069899 *||Aug 28, 1997||May 30, 2000||Broadcam Homenetworking, Inc.||Home area network system and method|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6763109 *||Oct 6, 2000||Jul 13, 2004||Advanced Fibre Access Corporation||Copper based interface system and regulated power source|
|US6775299||Oct 6, 2000||Aug 10, 2004||Advanced Fibre Access Corporation||Copper based interface system and data frame format|
|US6795538||Oct 6, 2000||Sep 21, 2004||Advanced Fibre Access Corporation||Initialization and monitoring system and method for DLC device|
|US6928581 *||Sep 14, 1999||Aug 9, 2005||International Business Machines Corporation||Innovative bypass circuit for circuit testing and modification|
|US6947529||Mar 27, 2001||Sep 20, 2005||2Wire, Inc.||DSL compatible load coil|
|US6977958||Jun 19, 2001||Dec 20, 2005||2Wire, Inc.||Differentially-driven loop extender|
|US7061857||Feb 15, 2002||Jun 13, 2006||2Wire, Inc.||System and method for fault isolation for DSL loop extenders|
|US7072385||Sep 26, 2000||Jul 4, 2006||2Wire, Inc.||Load coil and DSL repeater including same|
|US7190716||Feb 6, 2002||Mar 13, 2007||2Wire, Inc||Line powered loop extender with communications, control, and diagnostics|
|US7194023||Feb 6, 2002||Mar 20, 2007||2Wire, Inc.||Loop extender with communications, control, and diagnostics|
|US7483528||Feb 6, 2002||Jan 27, 2009||2Wire, Inc.||Loop extender with selectable line termination and equalization|
|US7583797 *||Jul 10, 2001||Sep 1, 2009||Broadcom Corporation||Single ended analog front end|
|US20020097863 *||Jul 10, 2001||Jul 25, 2002||Raphael Rahamim||Single ended analog front end|
|US20020106012 *||Feb 6, 2002||Aug 8, 2002||Norrell Andrew L.||Loop extender with communications, control, and diagnostics|
|US20020106013 *||Feb 6, 2002||Aug 8, 2002||Norrell Andrew L.||Loop extender with selectable line termination and equalization|
|US20020106076 *||Feb 6, 2002||Aug 8, 2002||Norrell Andrew L.||Line powered loop extender with communications, control, and diagnostics|
|US20020110221 *||Feb 15, 2002||Aug 15, 2002||Norrell Andrew L.||System and method for fault isolation for DSL loop extenders|
|US20030072359 *||Oct 12, 2001||Apr 17, 2003||Heikki Suonsivu||Method and apparatus for digital subscriber line transfer|
|WO2002063833A2 *||Feb 6, 2002||Aug 15, 2002||2Wire Inc||Loop extender with selectable line termination and equalization|
|U.S. Classification||375/259, 379/390.01, 375/222, 379/402, 375/229, 375/230|
|International Classification||H04L25/02, H04L25/03, H04L5/14, H04B3/06|
|Cooperative Classification||H04L25/0266, H04L25/03878, H04L25/0272, H04L5/14, H04B3/06, H04L25/0292|
|European Classification||H04B3/06, H04L25/02K9, H04L5/14, H04L25/03L|
|Mar 10, 2000||AS||Assignment|
|May 29, 2001||AS||Assignment|
|Oct 28, 2003||AS||Assignment|
|Sep 27, 2005||FPAY||Fee payment|
Year of fee payment: 4
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Year of fee payment: 8
|Dec 20, 2012||AS||Assignment|
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