Date of this Version
A nonlinear interconnection module for a corticonic network is designed and fabricated in a 0.6µm CMOS process. The module uses NMOS transistors in weak-inversion for nonlinearity. A calibration scheme is developed to compensate for the process and temperature variations of the circuit. The designed module has an area of 0.35 sq. mm2. It consumes 200mW of power, with 5V power supply. Simulation results show that the circuit is able to implement the target parametric coupling function accurately.
corticonic network, cortical patch, nonlinear interconnection
Jie Yuan, Nabil H. Farhat, and Jan Van der Spiegel, "A CMOS Monolithic Implementation of a Nonliniear Interconnection Module for a Corticonic Network", . May 2006.
Date Posted: 27 June 2007
This document has been peer reviewed.