Terascale Memory Challenges and Solutions
Modern computer architectures commonly include one or more CPUs, a cache or caches, a few DDR-based memory channels, rotational and/or solid state disks and one or more Ethernet ports.
Figure 1: System block diagram
A high percentage of CPU-based systems use DDR-based DRAM for external memory. DDR-based DRAM currently provides very favorable cost/bit while providing enough bandwidth with low enough latency to meet the application demands. Although process engineers have continued to find ways to cost effectively scale feature size, the CPU power consumed has become prohibitive.
In contrast to the previous decade, CPU clock rates are scaling slower over time due to the power constraints. However, the number of transistors per silicon area continue to increase roughly at the rate of Moore’s Law. Therefore, CPUs are being designed and built with an increasing number of cores, with each core executing one or more threads of instructions.
This puts a new kind of pressure on the memory subsystem. Though the demand for instructions and data per thread is not increasing very quickly, the rapid growth in the number of available threads puts an increasing emphasis on memory bandwidth. This article summarizes the challenges that arise for the memory subsystem associated with these terascale CPUs.
Memory Key Metrics and Fundamentals
The key metrics for examining the memory sub-systems are bandwidth, capacity, latency, power, system volume, and cost.
Bandwidth (Bytes/second, B/s or bits/second, b/s). Bandwidth is the number of Bytes transferred in a given amount of time. Bandwidth is usually the most talked-about performance metric. The bandwidth required for a system is usually market segment and application (working set size, code arrangement, and structure) dependent. Interestingly, bandwidth alone is not a very useful metric for system design decisions. Other factors must be considered such as cost, power and form factor (size/space) constraints in conjunction with bandwidth.
Capacity (Bytes or B). Capacity is the total number of bytes that can be stored in the region of memory.
Latency (seconds, sec or simply s). This is the time it takes to read a word from the region of memory. The focus is usually on read latency. Write latency is often of less interest; the time required to write to a memory is often not a factor for the performance of the application.
Power (Watts or W). Power equals the energy consumed divided by the time in which that energy is consumed.
System volume, Form Factor. This is the volume required for different technologies into a system. This is usually driven by the physical size of components and/or cooling requirements.
Cost ($). Cost usually refers to the money required to use components in a system.
Often metrics are combined. Frequently used metrics include bandwidth/Cost or Watts/bandwidth (J/bit).
Double data rate (DDR) memory has become the dominant memory technology (in terms of number of units sold). DDR-based DRAM products are optimized for high capacity and low cost, not high bandwidth, low latency or low power.
As the CPUs continue to increase in capability toward the terascale level, many of the key metrics are not scaling well and are becoming system design challenges. The metrics being stressed most are bandwidth, power and latency. As potential solutions are investigated, the other metrics of capacity and form factor become challenging as well.
The expression “hitting the memory wall” is often used. Commonly the “memory wall” has the connotation that DDR cannot supply enough bandwidth for CPUs. A more accurate statement is that based on the DDR interface and channel specifications, the bandwidth per pin cannot scale up as quickly as the compute capabilities of CPUs. Simply adding more pins in parallel is not an appealing option due to system cost reasons. The problem becomes acute when CPUs reach the TeraScale performance level. Being more precise, the rate at which bits can be moved between CPUs and DDR devices is limited by the frequency dependent loss, impedance discontinuities, the power available and cost to implement. It will be extremely challenging to push and pull data at rates that exceed 2.4 – 3.2 Gb/s per data signal across DDR channels.
The need to reduce latency and the value of reducing latency is very difficult to assess. Most systems today have put a higher value on bandwidth and choose to use forms of pipelining such as pre-fetching to hide latency. As CPUs approach the terascale range via many threads running in parallel pipeline-based methods to hide memory latency will become less effective. To keep cost and power low, more emphasis will be placed on reducing the latency for the first level of the memory hierarchy that is external to the CPU chip.
Increasing the bandwidth by adding data pins as well as reducing the read latency of DDR devices could be done while maintaining the existing architectures of both the DRAM as well as the interface. However, addressing these bandwidth and latency metrics alone is not enough since one of the greatest challenges to achieving terascale bandwidths is maintaining low power consumption.
DRAM device power is composed of three main components: power consumed by the storage array, power consumed by the datapath and power consumed by the I/O pins. Roughly 50 percent of the power consumed is in the datapath, with the other 50 percent split between I/O circuits and the array. All three areas need to be addressed to create DRAM products suitable for terascale systems.
Evolutionary DRAM Summary
In summary, the key trends for evolutionary memory sub-system scaling are:
•Bandwidth scaling for traditional DDRx-based systems will end at about 2.4 – 3.2 Gb/s per pin (bump).
•To achieve the bit rates above, each channel will likely be limited to one DIMM without extra components, such as buffer on board (motherboard).
•GDDRx gives increased bandwidth but at the cost of capacity. Pin bandwidth will be limited to 5-6 Gb/s for GDDR channels being constructed today.
•Power in the memory sub-system varies from 40-200 mW per Gb/s, translating to hundreds of Watts for a TB/s of bandwidth.
•Adding capacity to evolutionary memory sub-systems is limited to adding channels, buffer on board or other forms of buffered DIMMs.
•Latency improvements for evolutionary systems will be minimal.
Terascale Memory Challenges and Future Memory Technologies
In the following section, we describe some of those challenges facing memory architects and designers and potential solutions.
The first question we need to ask is which memory technology(s) will fill the needs of these systems. DRAM technology has long dominated the market for off-chip memory bandwidth solutions in computing systems. While non-volatile memory technologies such as NAND Flash and Phase Change Memory are vying for a share of this market, they are at a disadvantage with respect to bandwidth, latency, and power.
A holistic approach is needed to achieve the required results. The main factors that will need to be addressed to achieve the optimal solution for increased bandwidth and lower energy per bit of future terascale memory sub-systems are the channel materials, the I/O density, the memory density, and the memory device architecture. We examine the changes required in these areas.
First we look at the materials that could be used to construct channels between CPUs and memory modules.
Figure 2: Data Rate versus Trace Length for different materials
Adding complexity to the I/O circuits in the form of additional equalization, more complex clocking circuits, and possibly data coding can increase the data rate, but also increase the energy per bit moved. More complex interconnects, such as flex cabling, improved board materials, such as Rogers or high-density interconnect (HDI), and eventually, optical solutions, must be considered. The emphasis on higher bandwidth/pin, I/O density and lower energy per bit read/written will lead to selective use of new channel materials.
A DRAM technology that supports a high bandwidth per pin, high capacity and low energy per bit moved will be required. A promising solution to solve these issues is 3-D technology, based on through silicon vias (TSVs). 3-D stacked memory will provide an increase in memory density through stacking, and it will enable a wide datapath from the memory to the external pins, relaxing the per-pin bandwidth requirement in the memory array as shown in Figure 3.
Figure 3: 3-D Stacked Memory Module
This design achieves six objectives:
- A method for further scaling of DRAM density.
- A relatively wide datapath from the memory array to the memory pins, relaxing the speed constraints on the DRAM technology.
- A high density connection from the memory module to the memory controller, which makes for more efficient use of power.
- The elimination of many of the traditional interconnect components from the electrical path.
- It separates the high bandwidth I/O solution from the microprocessor and memory controller power delivery path when using the top of the package for high speed I/O.
- The increased density eliminates the need for the electrically-challenged and energy-inefficient, multi-drop DIMM bus.
A key new challenge is introduced; we need a way to move the data from the wide datapath from the memory array to the memory device pins. The general characteristics necessary for an optimal solution are the ability to efficiently multiplex the data at a rate that matches the data rate of the increased device pins (Gb/s), rather than a rate that matches the slower, wider memory datapath, at an efficient energy level (low pJ per bit) that closely matches the characteristics of the CPU generating the memory requests. The architecture, design and implementation of the data collection function will be dependent on the usage of the 3-D memory module, ranging from specialized DRAM chips to a mix of logic process chips and DRAM process chips.
Given a memory of the type we describe, we must also examine the entire memory hierarchy. For example, it may be advantageous to add a level of memory to the hierarchy.
Analyzing different memory hierarchies is a huge challenge. All the metrics mentioned previously need to be evaluated in the context of the applications of interest (see “Key Metrics”). When considering additional levels of the memory hierarchy, the key decisions are where to add a level or levels in the memory hierarchy and how the levels of memory are managed.
Memory Hierarchy — Where to Add Memory
Earlier, we concluded that to meet the needs of terascale systems, designers should investigate new architectures and manufacturing techniques for DRAM, with an emphasis on 3-D stacking with TSVs. We are confident that these techniques will lead to improved DRAM products, while maintaining a low cost per bit stored. We also realize that when the new technologies are introduced, it will take time for the price per bit to drop. Therefore, early use of 3-D stacked memory as near memory, backed up by DDR-based DRAM or other low cost per bit memory technologies, may be an appealing and cost-effective choice for designers.
The policies of what data (or instructions) are placed, where they are placed as well as what is copied and shared are the key research issues facing system designers. The simple statement that data movement must be minimized will take on additional importance as terascale CPUs are built.
Summary and Conclusions
The demand for bandwidth continues to increase. Terascale CPUs will exacerbate the challenges of the memory subsystem design, including the architecture and design of memory controllers, the memory modules and memory devices themselves. DDR-based memory and interfaces will continue to be used for the markets segments where they can, but the shift to something new will begin in next few years.
To learn more, read the Intel Technology Journal, Volume 13, Issue 4, December 2009, Addressing the Challenges of Tera-scale Computing, ISBN 978-1-934053-23-2