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NTSC/PAL TV and audio output using 14 resistors and a low pass audio filter. This design can be built in a couple minutes using parts from Radio Shack. Open Source VHDL code and EAGLE PCB design files are available.
BenL is working on a Sega Master implementation on the Papilio FPGA board. During that process he created a TV Output Wing:
"This TV output wing could be an interesting replacement for the VGA+jack outputs of the arcade kit. It's a very simple R-2R ladder 7 bit DAC for the video line, and a plain low pass filter for the audio (the DAC must be implemented through logic).
You can very easily output B/W video, and colors with some efforts :"
You should use R=115 ohms and 2R=230 ohms to get 0.3V from "010000" (black) on the input and 1.0V from "110000" (white), the remaining "001111" being left for color modulation at high luminance.
A picture of the homemade prototype :
A small demo : compile this, plug your tv_output wing in A8-A15 and enjoy 8 color bars in the middle of the screen: yellow, cyan, green,magenta,red, blue, black and white. And overscan is grey.
You can switch in main.vhd between pal and ntsc (*_video to produce the correct sync, *_encoder to transform rgb to quadrature modulated yuv)
The image is good, but far from perfect: low sat on yellow and cyan, interferences between luminance and color carrier, some dot crawl (although you might not notice it because it scrolls vertically really fast)
Click image for PDF Schematic
You need to generate sync, luminance (monochrome image) and color information. See http://www.deetc.isel.ipl.pt/Analisedesinai/sm/downloads/doc/ch08.pdf for details on the theory.
The provided encoder turns 2 bit RGB (64 colors) into YUV by a table lookup, and modulates the U/V signals by multiplying them by a square wave at the color carrier frequency (3.45MHz for NTSC, 4.62MHz for PAL) in phase (for U) and quadrature (for V). The color clok is generated from a 64MHz clock (thanks to a 21 bits accumulator), itself derived from the main 32MHz clock of the Papilio.
sync, Y, U and V are summed into the FPGA, and converted by the R-2R DAC into the corresponding voltage: the resistor values are chosen to turn the 3.3V of the Papilio output into the 0, 0.3 and 1.0V under 75 ohms that the tv requires.