Cadence University Program Member Page
University of Hawaii - Department of Electrical Engineering is a Cadence University Program Member
Cadence design tools in our curriculum
Cadence software is being used primarily in the following course(s):
Room: Holmes Hall 241
There will be an Integrated Circuit design project for this class. Cadence software products are used to design and simulate a circuit, as well as for IC layout and verification. We are using AMIS 0.5 micron CMOS process, available through MOSIS. All students individually design, simulate, layout, verify their chip designs, and provide a test plan. At the end of the semester, chips are submitted for fabrication through MOSIS.
Room: Holmes Hall 248
Cadence design tools in our research
Cadence software is used for simulations and layout for a variety of RFIC and MEMS related projects, including:
2010 0.18mm CMOS Miniature Wideband Passive Mixers
The first photograph shows the first reported resistive mixer without any passive elements. It is the smallest double-balanced resistive mixer reported to date with the active chip area of 0.05mm2. This mixer shows CL of 6.3 – 8.2 dB between frequencies of 2 – 8 GHz. The total chip size is 1.01 x 1.1 mm2.
The second photograph shows a fully integrated resistive mixer that uses baluns both for single-ended to differential conversion and impedance matching was reported. With the RF and LO baluns integrated on chip, this passive mixer exhibits low conversion loss (CL), excellent linearity, as well as good RF and IF impedance matching, without any matching circuits. The chip size is 1.4 mm x 1.3 mm2.
Both mixers were fabricated in IBM7HP 0.18 mm process. The chip layout was done using Cadence Virtuoso Layout Editor.
The photograph shows a single-ended sub-harmonic passive mixer based on a single transistor design. The fundamental operating frequency of this mixer is 750 MHz. sive Mixer. The LO frequency is one half of the fundamental frequency. Sub-harmonic mixers are particularly useful for higher frequencies where it is difficult to generate local oscillator signal using VCO's. However, Sub-harmonic mixers can also prove useful in harmonic radar systems where a harmonic tag is used to scatter back the information.
The mixer was fabricated in AMIS 0.5 um process. the die area is 1.2 mm x 1 mm. Tests are currently being performed on the mixer to evaluate its performance
This photograph shows a 2.4 GHz (ISM band) double-balanced resistive ring mixer design suitable for low power receiver, including Doppler radar cardiopulmonary sensors. This CMOS resistive ring mixer operates in the near-threshold region, achieving conversion loss of 7 dB at 3.6 GHz, with low RF insertion loss in the frequency range of 2-8 GHz. By applying a small gate bias, the conversion loss under very low LO conditions is improved tremendously. The size of the chip is 1.24 mm x 0.8 mm, and the chip was fabricated in 0.25-µm TSMC process. The chip layout was done using Cadence Virtuoso Layout Editor.
This ASIC chip measures beat-to-beat (RR) intervals and stores heart rate variability (HRV) parameters into its internal memory in real-time. A wide range of short-term and long-term ECG signals obtained from Physionet were used for testing. The system detects R peaks with millisecond accuracy, and stores up to 2 minutes of continuous RR interval data and up to 4 minutes of RR interval histogram. The prototype chip was fabricated in a 0.5 um CMOS technology on a 3x3 mm2 die area, with estimated dynamic power consumption of 0.3 uW and measured leakage current of 2.62 nA.
The design algorithm was written in VHDL. The gate level standard cell design was then generated by Synopsis Design Compiler using a 0.5um standard cell library for AMIS 0.5um CMOS process. The placement and routing were performed by Cadence Chip Encounter. The final GDS2 file was generated and checked by Cadence Virtuoso.
Heart rate variability (HRV) refers to the beat-to-beat (RR) alterations in heart rate which reflect the cardiovascular function and the dynamic response of the cardiovascular regulatory systems. The analysis of HRV has proven useful in understanding cardiovascular regulation in a range of conditions including heart failure, diabetes, hypertension, and sleep apnea. Measurement of HRV provides a non-invasive method to obtain reliable information on autonomic modulation of heart rate and has become an important tool for risk assessment to millions of patients who suffer from chronic diseases.
Our project focuses on implementation of a system on a chip for HRV monitoring and assessment. The system design applies digital techniques to measure RR intervals from ECG signals, then categorizes and stores HRV measures in an internal memory. The SoC design is enabled by use of the Cadence Virtuoso Layout Editor.
An increasing health problem in the developed world is that of chronic conditions associated with aging such as cardiovascular disease and diabetes. The analysis of heart rate variability (HRV) has proven useful in understanding cardiovascular regulation in a range of conditions, including heart failure, diabetes, hypertension, and sleep apnea. To obtain data for HRV studies, an electrocardiogram (ECG) is typically sampled with 12 or more bits of resolution at a sampling rate of 1 kHz or higher to provide a 1 ms time resolution. The digital samples are recorded and processed off-line to determine markers of beat-to-beat (R-R) interval variability in either the time or frequency domain.
We present an integrated analog signal processing (ASP) system that can process heart rate data in real time to provide beat (R-R) interval data with high level of robustness and accuracy. Such analog signal processing reduces the ADC resolution and speed requirements. This project was integrated in 0.5-µm CMOS technology with a novel peak detector that achieves high accuracy and data compression. Simulation results with pre-recorded ECG signals demonstrate accuracy on the order of 1 ms with low power consumption. The chip layout was done using Cadence Virtuoso Layout Editor.
Wide-band low-noise amplifiers play an important role in the receiver front end for telecommunication applications, such as, cable, satellite communications, and terrestrial digital video broadcasting. Recently, these wideband topologies have also been used in ultra wideband (UWB) applications, such as, video transceivers and radar sensors. Good noise performance and bandwidth have been demonstrated with amplifier configurations using submicron CMOS devices, making them good candidates for low-cost wide-band amplifiers. This project explores the performance of a CMOS inverter with inductively source degeneration and resistive shunt feedback (IWSFR) configuration for low noise and high linearity UHF applications. The prototype shown below has been realized with TSMC 0.25µm process fabricated through MOSIS. The chip layout was done using Cadence Virtuoso Layout Editor.