By Cameron Chai
At the IEEE International Electron Devices Meeting, IBM researchers have demonstrated their research that involves the incorporation of novel logic architectures and materials into wafers having a diameter of 200 mm, paving the way to innovative technologies for the integration of consumer electronics, communication and computing.
Racetrack memory has the advantages of solid-state memory and magnetic hard drives to address the issues related to memory and shrinking devices. The IBM research team has developed a racetrack memory device incorporated with CMOS technology on a 200 mm wafer, opening the door to enhance the dependability and density of racetrack memory utilizing three-dimensional architectures and magnetized racetracks. This novel innovation lays the foundation to develop an advanced data-centric computing device capable of storing large amounts of data that can be accessed within a billionth of a second.
The research team has displayed the first-of-its-kind scale carbon nanotube transistor having a channel length of sub-10 nm, with a performance far better than the existing silicon devices having these length scales. These devices having a gate length of less than 10 nm, will play a major role in future computing technology. These scaled carbon nanotube devices have also demonstrated their superior off-state behavior.
At the meeting, the IBM scientists have also displayed first-of-its-kind graphene device compatible with CMOS technology. The graphene device operates at a frequency of up to 5 GHz and demonstrates high thermal stability at temperatures up to 200° C, paving the way to develop high-frequency devices that can function under harmful radiation and temperature environments such as medical and security fields. The team designed a special embedded gate structure in place of depositing gate dielectric on the surface of inert graphene, offering high device output on 200 mm wafers.