For example the 82093AA IO-APIC has I/O redirection table registers (IOREDTBL) which have a
writeable bit specifying the trigger mode (which can be level or edge sensitive). These
registers seem to be reflected by
struct IO_APIC_route_entry in the kernel source.
Digging a bit through the 2.6.18 kernel source, one comes across a function
setup_IO_APIC_irqs(..) which loops over all IO-APICs found and over all IRQ lines for each IO-APIC and calls
io_apic_write(..) to write to the APIC's registers.
The trigger type seems to be determined by the function
MPBIOS_trigger(..) (called by
irq_trigger(..)) which in turn seems to consult a variable
mp_irqs which in turn seems to be filled in
arch/x86_64/kernel/mpparse.c. This file seems to read the a the MP configuration table conforming to the Intel MultiProcessor Specification.
Qouting from this specification:
The BIOS constructs the MP configuration data structures, presenting the
hardware in a known format to the standard device drivers or to the
hardware abstraction layer of the operating system.
So I'd say the kernel configures the interrupt trigger type based on
information provided by the BIOS.
A side comment: the Wikipedia article on Interrupts mentions that
The original PCI standard mandated shareable level-triggered interrupts.
(which seems to come from the fact that edge triggered interrupts sent by multiple devices at the same time on the same line will collide). So
IO-APIC-edge is a bit unexpected for PCI devices.