San Jose, Calif.--March 17, 1998--Cadence Design Systems, Inc. (San Jose) announced that next phase of its system-to-silicon verification strategy unites the functional verification of hardware and software (HW and SW) system components into a concurrent development cycle. Building upon its integrated system and chip approach, Cadence is introducing new technologies and an enhanced "system-in" verification flow that lets designers achieve greater efficiency throughout the development cycle and apply the optimum level of verification for increasingly complex systems-on-a-chip (SOC).
A key enabler of Cadence's coverification initiative is a strategic technology relationship with Motorola Semiconductor Products Sector (Austin, Texas). Cadence's development efforts will leverage the advanced HW and SW simulation manager product developed and currently used in production at Motorola. The companies will call upon Motorola's competency in embedded-systems design and high-performance modeling and Cadence's leadership in hardware verification to deliver a truly integrated environment for HW and SW coverification and debugging at multiple points in the design cycle.
Cadence's strategy transitions the design process from implementation to prototype. It enables the verification of a virtual system that is modeled through the integration of test benches and models across multiple levels of design abstraction for both HW and SW components. The strategy also provides for an open environment to integrate real time operating systems (RTOS); SW debuggers; and hardware solutions, including in-circuit emulators (ICE), accelerators, and traditional logic simulators.
The integration of system-level functions into complex application-specific integrated circuits (ASICs)--such as embedded microcontrollers, digital signal processors, and system interfaces--requires that designers link their system and hardware description language (HDL) verification methods with a systems-in approach to ensure consistency between these two levels of the design. This is critical as designers continue to evolve toward the mix and match of complex system chips, primarily consisting of predictable and preverified "virtual components" for both hardware and software functions.
Cadence is implementing a silicon-to-system design and verification flow that includes: system-level specification, HW and SW architectural evaluation and codesign (Felix Initiative announced in December 1997), functional coverification and debugging of HW and SW components, and logic verification of chip implementations. Additionally, Cadence noted that its strategy extends coverification into the prototype development phase, through partnerships with market-leading providers of RTOS, ICEs, hardware emulators, and accelerators. As a result, designers can "get under the hood" of a complex ASIC or advanced system chips to debug problems that appear in early silicon prototypes.
Cadence's integrated approach to coverification receives a simulation performance boost from the interleaved native compiled code architecture (INCA) of its hardware verification environment. INCA provides the critical co-execution capabilities lacking in current solutions needed to thoroughly verify both functional equivalence and HW/SW interfaces of virtual components across multiple levels of abstraction.
Cadence's coverification implementation tightly couples Verilog and VHDL co-execution for the hardware design with high-speed OMI-interfaced C-language, Verilog register transfer level (RTL), or VHDL RTL models at instruction set, bus functional, clock cycle accurate, or other levels of abstraction. It is this high-speed HW and SW coverification that maximizes simulation performance and enables system designers to realize design cycle reduction goals. Applications that require significant interaction between the HW and SW system components, such avionic and automotive electronics, will particularly benefit from Cadence's INCA-based approach to HW and SW coverification.
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