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 This invention relates generally to electronic circuits. More particularly, this invention relates to integrated electronic circuits and redundancy.
 In the fabrication of electronic circuits, one technique utilized to increase production yield is to provide redundant circuit elements on the chip to allow for replacement of key circuit elements that prove to be defective. During testing of the chip, the defective portion of the circuit is identified and the redundant circuit element, if one exists, may be activated by opening an associated fuse or similar mechanism. Redundancy is especially suited for repetitive circuits having a large number of repeating elements arranged in some form of an array, such that a redundant circuit element can replace a single defective circuit element in a collection of circuit elements. One such device is a semiconductor memory comprised primarily of memory cells. These memory cells are arranged in rows and columns wherein the redundant circuit element would be either a row or collection of rows of memory cells or a column or collection of columns of memory cells. If, for example, one cell in a given column is defective, the device would be classified as defective. A defective column, or the collection of columns containing the defective column may be replaced by a redundant column or a collection of columns and as a consequence the device would be fully operational. A memory may have, for example, 256 rows and 256 columns. One redundant column would therefore be able to replace one of the 256 columns, thus constituting an efficient use of a redundant circuit.
 An integrated circuit (IC) memory generally includes an array of memory cells arranged in rows and columns, each column of cells selected by a column address signal and each row of adjacent cells selected by a row address signal. A redundant column of memory elements may be disposed adjacent a non-redundant array and may be selectable by a predetermined column address with the redundant column memory normally inactive. When a column of memory cells in the nonredundant array is defective, the defective column is deactivated and a circuit is provided for activating the redundant column, such that the redundant column can be addressed by the predetermined column address.
 A problem that may be encountered when replacing a column or row in a semiconductor memory is maintaining address integrity; that is, the redundant column must have the same address as the defective column. This is normally implemented by providing a universal decode circuit in association with the redundant column circuitry. Appropriate fuses are included that can be opened to deactivate the defective column, activate the redundant column circuitry and also to program the universal decode circuitry for the appropriate address. The fuses must also be on pitch with the arrays. The area required for fuses and circuitry to access redundant arrays can be fairly large and is an overhead that circuit designers would like to avoid where possible. There is a need in the art for a method for removing or reducing the area required for fuses and circuitry used to access redundant arrays. In addition to the area overhead required to implement redundancy schemes, many redundancy schemes slow the access times when a redundant circuit element is used. IC's may be sorted according to their access times. IC's with shorter access times may be sold at higher prices so IC's that use redundancy schemes that increase access time may not be as valuable as IC's that don't use redundancy. There is a need in the art for a redundancy scheme that does not increase the access time of IC's when redundancy is employed.
 Redundancy through data shifting eliminates the need for unique redundant decoders, the programming of a large number of fuses to enable and encode the redundant elements, and deactivate the non-functional circuitry. The small number of fuses required to implement redundancy through data-shifting can easily fit on pitch, or can be remotely located. In addition, redundancy through data-shifting makes it possible to replace an array with a redundant array with no appreciable increase in access time.
 An embodiment of the invention provides a circuit for deselecting a plurality of arrays from a set of arrays. A set of input-buffers, where each input-buffer has a set of inputs that are input ports to the memory circuit, is connected to the set of arrays such that each output from each input-buffer is connected to a unique array selected from the set of arrays. In addition, a set of output-buffers, where each outputbuffer has a set of inputs that are ports from a set of arrays is connected such that the output from each output-buffer is connected to a unique output port of the memory circuit selected from the set of arrays. The arrays used, for example may be DRAM, SRAM, PLA, or register arrays. The method used in this invention reduces the area needed to implement redundancy as well as reducing the number of fuses needed. The fuses, when using this invention, may be located almost any where on an IC, they don't have to be on pitch as with many other redundancy schemes. In addition, the invention makes it possible to use redundant arrays on an IC with no difference in access time resulting from their use.
 Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.
 In a second configuration, arrays A(1),
 In a third configuration, arrays A(3),
 In a fourth configuration, the control signals may be set to select the third input of each input-buffer, K(1)-K(N+2). This results in the data on the third input of input-buffers K(1)-K(N+2) being passed to the inputs of the arrays, K(1)-K(N+2) respectively. The arrays, A(1),
 In a fifth configuration, arrays A(1),
 In a sixth configuration, arrays A(3),
 Data-shifting may be accomplished for both reading and writing data, by combining input-buffers and output-buffers in one circuit. The same control signals may be used to read or write an individual array. The number of arrays that may be deselected is only limited by the number of inputs to an output-buffer and the number of outputs from an input-buffer.
 The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.