Issue No.02 - Feb. (2013 vol.62)
George Michelogiannakis , Stanford University, Stanford
William J. Dally , Stanford University, Stanford
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.237
Networks-on-chip (NoCs) were developed to meet the communication requirements of large-scale systems. The majority of current NoCs spend considerable area and power for router buffers. In our past work, we have developed elastic buffer (EB) flow control which adds simple control logic in the channels to use pipeline flip-flops (FFs) as EBs with two storage locations. This way, channels act as distributed FIFOs and input buffers are no longer required. Removing buffers and virtual channels (VCs) significantly simplifies router design. Compared to VC networks with highly-efficient custom SRAM buffers, EB networks provide an up to 45 percent shorter cycle time, 16 percent more throughput per unit power, or 22 percent more throughput per unit area. EB networks provide traffic classes using duplicate physical subnetworks. However, this approach negates the cost gains or becomes infeasible for a large number of traffic classes. Therefore, in this paper we propose a hybrid EB-VC router which provides an arbitrary number of traffic classes by using an input buffer to drain flits facing severe contention or deadlock. Thus, hybrid routers operate as EB routers in the common case, and as VC routers when necessary. For this reason, the hybrid EB-VC scheme offers 21 percent more throughput per unit power than VC networks and 12 percent than EB networks.
Switches, Throughput, Radiation detectors, Latches, Routing, Pipeline processing, interconnection architectures, On-chip interconnection networks
George Michelogiannakis, William J. Dally, "Elastic Buffer Flow Control for On-Chip Networks", IEEE Transactions on Computers, vol.62, no. 2, pp. 295-309, Feb. 2013, doi:10.1109/TC.2011.237