|Home Analog Devices Feedback Subscribe Archives 简体中文 日本語|
Demystifying High-Performance Multiplexed Data-Acquisition Systems
Multiplexed Data-Acquisition System Challenges
Figure 1. Block diagram of multiplexed data-acquisition system.
Figure 2. Switching time in a typical multiplexer.
A voltage glitch or kickback occurs at the multiplexer input when it switches channels. This kickback is a function of the turn-on and turn-off times, on-resistance, and load capacitance. Large switches with low on-resistance typically result in a large output capacitance that must be charged to a new voltage each time the input is switched. If the output doesn’t settle to a new voltage, crosstalk error will occur. Therefore, the multiplexer’s bandwidth must be sufficient and a buffer amplifier or large capacitors must be used at the multiplexer input to settle a full-scale step. In addition, the leakage current flowing through the on-resistance will introduce a gain error, so both should be kept small.
Figure 3 shows a timing diagram of a multiplexed data-acquisition system when its input makes a full-scale change. The cycle time of the ADC, which consists of the conversion time plus the acquisition time (tCYC = tCONV + tACQ), is usually specified as 1/throughput rate in the data sheet. The capacitive DAC of the SAR ADC is disconnected from the inputs at the start of the conversion, and the multiplexer channel can be switched to the next channel after a small switching delay, tS. This allows the maximum time to settle the selected channel. To guarantee performance at maximum throughput, all of the components in the multiplexed system must settle at the ADC input between the time that the multiplexer switches and the end of the acquisition time. The multiplexer channel switching must be properly synchronized with the ADC conversion time. The achievable throughput rate in a multiplexed system is the single ADC throughput rate divided by the number of channels being sampled.
Figure 3. Typical timing diagram of a multiplexed data-acquisition system.
RC Filter at Inputs of Multiplexer
Multiplexed Data-Acquisition Signal Chain
Figure 4. Simplified signal chain for a multiplexed data-acquisition system.
The ADG774 quad 2:1 CMOS multiplexer offers fast switching speed (tON = 7 ns, tOFF = 4 ns), low on-resistance
Figure 5. ADG774 on-resistance vs. input voltage.
The output of the ADG774 is connected to a high-input-impedance amplifier stage. The ADA4899-1 high-speed op amp features ultralow noise (1 nV/√Hz) and distortion (−117 dBc), 600 MHz bandwidth, and 310 V/μs slew rate. Operating on +7-V and
Figure 6. Typical settling time of the ADA4899-1.
The AD7960 precision differential ADC offers best-in-class noise and linearity without latency or pipeline delay, high accuracy (18-bit resolution, ±0.8-LSB INL, 99-dB SNR, and –117-dB THD), fast sampling (5 MSPS), low power dissipation, and low cost. Powered from +5 V (VDD1) and +1.8 V (VDD2 and VIO) supplies, it dissipates only 46.5 mW at 5 MSPS when converting in echoed-clock mode. Its core power dissipation scales linearly with throughput, making it well suited for low-power applications with high channel density. The 5 V and 1.8 V supplies can be generated by low-noise LDOs such as ADP7104 and ADP124.
The ADC’s full-scale differential input range is set to 5 V or 4.096 V by an external reference. To fully use its dynamic range, the input signals must swing from 0 to VREF. In this signal chain, the 5-V reference is supplied by the ADR4550 high-precision (±0.02% max initial error), low-power (950 µA max operating current) voltage reference, which features excellent temperature stability and low output noise. The AD8031 rail-to-rail op amp buffers the external reference. Stable with large capacitive loads, it can drive the decoupling capacitors required to minimize voltage spikes caused by transient currents. The AD8031 is ideal for a wide range of applications, from battery-operated systems with wide bandwidth to high-speed systems where high component density requires low power dissipation.
The AD7960 digital interface offers self-clocked and echoed-clock modes using low-voltage differential signaling (LVDS) to enable high-speed data transfer up to 300 MHz (CLK± and D±) between the ADC and the digital host. The LVDS interface allows multiple devices to share a common clock, reducing the number of digital lines and easing signal routing. The lower power dissipation as compared to parallel interfaces is especially useful in multiplexed applications.
The AD7960 returns to acquisition mode about 115 ns after the start of conversion, leaving about 40% of the total 200-ns cycle time to acquire the signal. This relatively long acquisition time relaxes the burden on the amplifier’s bandwidth and settling time requirements and makes the differential inputs easier to drive. The 5-MSPS throughput rate allows multiple channels to be multiplexed at fast scan rates, so fewer ADCs are required in high-channel-count systems.
During the conversion, the AD7960 has a quiet-time requirement at 90 ns to 110 ns where the multiplexer inputs must not be switched. Thus, to avoid corrupting the ongoing conversion, the external multiplexer must be switched to less than 90 ns or more than 110 ns after the rising edge of the CNV± start signal. If the analog inputs are switched during this quiet time, the current conversion may be corrupted by up to 15 LSBs. The analog inputs should be switched as early as possible to allow the maximum time to slew a full-scale signal and settle the input.
After every 16 conversions, the multiplexer switches between –5 V and +5 V about 10 ns after the rising edge of CNV±, as shown in Figure 7. This creates a full-scale differential step, so the ADC output change from negative full-scale to positive full-scale as shown in Figure 8.
Figure 7. Oscilloscope plot shows kickback from the internal CAP DAC.
Figure 8. AD7960 output shows the ADG774 switching after every 16 conversions.
This switching time delay must be greater than the ADC’s 1.6-ns aperture delay. The signal measured at the ADC input shows about 1-V p-p kickback (Figure 7, highlighted in red) from the capacitive DAC in the AD7960. To ensure that the output is fully settled, the driver amplifier must settle this transient before the next conversion starts, within the approximately 80 ns acquisition time of the ADC when running at 5 MSPS. Running the ADC at lower throughput rates provides more acquisition time to settle this kickback, resulting in a lower crosstalk error between the multiplexer input channels and better settling time to a full-scale step.
The signal measured at the multiplexer input also shows a kickback from the channel switching. A buffer amplifier at the multiplexer inputs helps to settle this kickback. If the input buffer amplifier cannot be used for cost or space reasons, an optimized RC filter can be added to the inputs to reduce the effect of the kickback and crosstalk. The value of RC filter used on the multiplexer inputs impacts the overall noise and settling time of the signal chain.
When the multiplexer is static, the output of the data-acquisition system with the AD7960 running at its maximum 5-MSPS throughput rate is about 14 LSBs away from nominal full scale, representing the system’s overall gain and offset error. When the multiplexer is switching, the ADA4899-1 driver amplifier helps to settle the output to positive and negative full scale within an acceptable channel-to-channel crosstalk error for most applications. The output error scales exponentially with throughput, reaching a maximum of 0.01% at 5 MSPS, as shown in Figure 9. The zero crosstalk error at lower throughput rates shows that the ADC output settles to its final value during the first conversion.
Figure 9. Crosstalk error vs. throughput as a percentage of full-scale amplitude.
As shown in Figure 10, the crosstalk error relative to full scale is less than 0.001% at 1 V p-p (10% of full scale), and scales linearly with differential input amplitude. The crosstalk error relative to step amplitude is almost flat over the full input span and is always less than 0.01%.
Figure 10. Crosstalk error vs. differential input signal.
This multiplexed signal chain offers optimized performance with the best noise vs. settling time trade-off. These results demonstrate that a wide bandwidth, fast-settling amplifier is required to settle the large voltage step and kickback from the ADC input and to reduce the magnitude of the crosstalk error when multiplexing.
Multiplexed Data-Acquisition System Layout Considerations
Figure 11. Top layer of evaluation board for a multiplexed data-acquisition system.
Multiplexed Data-Acquisition Applications
The excellent linearity and low noise provide enhanced image quality in computed tomography (CT) and digital X-ray (DXR) applications. Switching many channels at high sampling rates into fewer ADCs allows a shorter scanning period and decreased exposure to the X-ray dosage, providing an accurate, affordable diagnosis and a better patient experience. In CT scanners, the pixel current is captured continuously using a single integrator and track-and-hold per channel, with outputs multiplexed to a high-speed ADC. A low-noise analog front end transforms the small current from each pixel into a large voltage, which is then converted into digital data that can be processed.
Multiplexed medical imaging systems, especially CT and DXR, specify typical pixel-to-pixel crosstalk error of ±0.1% from adjacent pixels and ±0.01% from nonadjacent pixels. The results presented here suggest that the crosstalk error generated from this multiplexed signal chain is well within the acceptable limits, even at maximum throughput and full-scale range.
Share this article
Copyright 1995- Analog Devices, Inc. All rights reserved.