|Thursday, June 14, 2012|
9:30 AM - 10:30 AM
|Welcome and Keynote Address|
Aart de Geus, Synopsys CEO & Chairman of the Board, Joachim Kunkel, Sr. Vice President and General Manager [Synopsys Solutions Group]
SNUG will kick off with a message from Synopsys CEO Aart de Geus, who will present an overview of the company’s business and technology direction, including the impact of the recent acquisition of Magma Design Automation.
|Thursday, June 14, 2012|
10:45 AM - 12:15 PM
|A1 User Session: Front-to-Back Implementation|
|Design Optimization and Formal Checking with Retiming Techniques|
Philippe Maneta [ST-Ericsson]
Recently, the wireless semiconductor industry has seen the expansion of tablets with high-definition video using sophisticated video processing for image rendering. Now it sees the rise of 3D graphics. Such devices manage huge amounts of data with wide data to be processed at high-speed frequencies using complex algorithms, like FFT with multiplier operands. Such operands, along with a high-speed frequency target, become critical to meeting timing closure. Various techniques can be used to split such logic cones as register cloning and retiming. Structuring the RTL is a complex task that has an impact on schedule. Then it appears that the better trade-off is to leave the tools restructuring the design by itself, but these optimizations become very sophisticated for synthesis tools, making equivalence checking harder. This paper describes a concrete case on a 2D/3D graphics IP development, including retiming improvements, from the synthesis step to equivalence checking.
|Advanced Design Flow: Design of a Full-HD120 Video Accelerator from a C Architecture to an ICC Implementation|
Alexandre Bleys [ST-Ericsson]
- This article will share the experience on the usage of a high-level custom design flow, based on Synopsys tools to design and implement the first hardware video P120 H264 encoder. The presentation will cover the complete design flow used to generate and implement this IP, from the description of:
- the high-level, synthesizable architecture IP & flow based on SCC, through
- the topographical synthesizable study based on DC-SPG, and finish with
- a presentation of the implementation, based on ICC-SPG
We will be sharing accurate reports on each interesting step of the global flow.
|Advanced Design Flow for LPDDR2 non Volatile Memory Design|
Anna Faldarini, Christophe Laurent [Micron Technology]
The adoption of a Low Power Double Data Rate 2 (LPDDR2) interface for Non Volatile Memories creates new design challenges with respect to traditional memory interfaces. In order to achieve a higher clock frequency, low-power consumption and to cope with higher design complexity, like new usercommands and configurable pipeline length, a complete review of the existing design flow was required. This paper details the improvements made in the three principal phases of the flow: design, synthesis and physical implementation. Design enhancement went through optimized standard cells creation, manually inserted clock gating cells and progressive clock tree implementation. Topographical synthesis, multi-scenario functionalities and low-power techniques were integrated in the synthesis flow while multi-scenario, timing-driven optimizations, magnetic placement and clock tree guidelines are just some of the new features used in the physical implementation flow.
|A2 User Session: Low-Power Verification|
|Formal and Low-Power Verification on Large SoC Designs|
Yassine EL Khourassani [ST-Ericsson]
Designing a complex, multi-voltage SoC is a challenge induced by greater functionality integration, small size and low-power consumption constraints. Today, formal verification and low-power checks are methodologies that make these challenges more affordable. Multi-voltage checkers help critique UPF power intent and the power architecture check. They don’t only tackle the electrical aspects. Verification of the architectural choices is also a mainstream approach in MVRC built-in rules, and the advanced procedures and scripts that profit from the overall possibilities of MVRC commands. The formal analysis is considered a dedicated skill to functional verification experts. The improved maturity of both low-power concepts and formal verification will help to reach a convergence, and we could expect a breakthrough in concepts alignment. This paper outlines how the power intent could be checked by formal verification techniques in order to address the verification requirements in a much more exhaustive, quick to setup and pragmatic methodology.
|Dynamic Low-Power Verification on a Multi-CPU Subsystem using VCS-NLP|
Massimo Calligaro [ST-Ericsson]
A methodology for dynamic, low-power verification has to address several elements in a specific way: modelling, scenario definition, platform implementation and debugging interface to address a few. A subsystem including multiple CPU instances with independent multi-voltage power domains requires complex scenarios to be executed and, therefore, an efficient debugging interface to be able to analyze and trace power-related malfunctions. A recent ST-Ericsson project implementing several low-power features has premiered the usage of VCS-NLP as the base tool for the simulation platform. This paper gives an overview of the dynamic verification approach, describes how VCS-NLP has been integrated in the existing tool flow and shows how its debug features have been used to analyze scenarios execution and to trace malfunction causes. Finally, some significant bug cases are analyzed.
|Real Voltage Modeling through Assertions|
Ankita Arya, Mohit Jain, Chandan Singh [STMicroelectronics]
Multi-rail macros are designed to operate in multiple, low-power modes depending upon the voltage value of each supply and state of low-power pins. Various low-power techniques like retention, DVFS, body biasing, employ varying the voltage values to different levels. For successful working of the designs on silicon, the voltages should lie in a specific range as the macro switches from one mode and another. In the current SoC verification strategy, such cases where supply goes outside of a specified range of operation for a particular mode would normally be detected either very late in the design or in worst case at silicon. Using SV assertions and MVSIM, it is possible to detect such invalid cases very early at RTL stage and allow correction of the design/software beforehand.
|A3 User & Tutorial Session: Hierarchical Design & Floorplanning|
|ICC Template-Based Power Network Synthesis (TPNS) & Power Network Analysis (PNA) to Increase Implementation and Verification Efficiency of Mixed-Signal Design Multi-Voltage Power Ground Grids|
Christelle Leherpeur [STMicroelectronics]
When we begin to implement a multi voltage product with a new technology, very often we don't initially know the best way to define the size of the different metallization stripes which will be used (width and pitch) to make those PG grids more robust as there is no fact-based documentation as a reference. Very often when you exchange ideas with designers about the size of "the" power/ground grids you have to generate, often they tell you: "take an example or be inspired by looking at this product" or " I did it like this because that's the way we always used to do it". In reality during the product development design step, the floorplan die size is always moving to take into account the last mandatory requested modifications often requiring a re-implementation of the PG grid."
|Hierarchical Design-Planning of a Multi-million Instance Design|
This article discusses the floorplanning study carried out on a high-performance 32nm SoC design. Using our design as a case study we illustrate different steps of the floorplan flow. We go from higher level picture down to detail TCL commands on each step and highlight various issues and our solutions. A brief overview of our timing constraints methodology, timing correlation and setup/hold fixing methodology is also provided.
|Faster Top-Level Closure with Transparent Interface Optimization (TIO)|
Gaspard Thaller [Synopsys]
Transparent Interface Optimization (TIO) in IC Compiler is a new capability that addresses the challenges of gigascale design and enables faster top-level closure. This tutorial will provide designers technical information on TIO, its usage, current capabilities and roadmap.
Target audience: Design and CAD engineers and managers responsible for physical implementation and verification
|A4 User Session: Design for Test and ATPG I|
|State-of-the-Art, Low-Power DFT Methodology|
Swapnil Bahl, Shray Khullar, Roberto Mattiuzzo, Saverio Graniello [STMicroelectronics]
High power consumption is an issue both in Shift and Capture mode during scan test. Generating power-aware ATPG vectors based on switching activity has been widely supported and used in the industry. Power budget i.e. allowed percentage switching activity of flops, directly impacts the test coverage and pattern count. An aggressive budget may result in unacceptable QoR while a relaxed one may generate patterns that fail on silicon. Also, the absolute power consumption may vary for same switching activity patterns as flops in different logic cones may consume different power. This is more of a concern with today’s SoC which have blocks with different power and voltage domains, different operating frequencies and multi-variety of transistors used. We present a methodology based on latest Power-aware ATPG features like weighted and per_clock_domain budget to generate accurate ATPG vectors that respect the power specification. The results show very good correlation and deviation within +-10%.
|Early Power Analysis Methodology using PrimeTime PX to Assess Achievable Maximum Shift Frequency before ATPG|
Jean-Michel Lagoutte [ST-Ericsson], Philippe Rossant [Synopsys France]
SoC and IP designers often need to anticipate the maximum achievable frequency they could use to test their design - especially during shift - without facing any IR drop issues. So the question is basically: is it indeed possible to anticipate this kind of maximum frequency limit, without needing to generate any ATPG patterns? In this paper we describe an original approach, using the PT-PX tool and specific methodology in order to try proposing a solution to this problem. We will show the flow, the methodology, and the results we have seen on representative sets of IPs, the correlation with results obtained from low-power driven ATPG, discussing advantages and limits of such an approach.
|Using TetraMax Top Level Protocol Generation to Extract DFTMAX Codec Information for Lifetest Pattern Generation (HTOL)|
Gerald Briat, Stéphane Guilhot [ST-Ericsson], Philippe Rossant [Synopsys]
On complex SoCs, we often need to generate specific ATPG patterns such as HTOL patterns: These specific patterns are used during the burn-in phase. For these, we have to run the ATPG Codec by Codec when DFTMAX Cores have been embedded in the design, contrary to the production ATPG patterns, which are using full flat chip and all the Codecs. These HTOL patterns could also be used as a backup in case of any IR drop induced failure. To achieve this, we have used TetraMax Top Level Protocol Generation (TLPG) feature on a complex SoC. This paper describes the flow and its alternatives, the results obtained, and the limitations seen.
|A5 User and Tutorial Session: FPGA Implementation|
|Implementing Dual Role Device USB2/3 IP from Synopsys using the HAPS6x Platform|
Nicolas Krohmer [Texas Instrument]
This paper describes a platform developed by TI to use the DesignWare USB3.0 controller from Synopsys (called DWC_USB3) embedded onto a SoC. This environment gives the possibility to software teams to have a hardware platform to develop and valid in advance their software concerning the USB interfaces of the SoC. This document will not cover software aspects, only hardware side. The environment described in this paper has been developed and installed on a HAPS6x board from Synopsys and use a specific TI PHY daughter board supporting USB attachment and allowing USB1, USB2 and USB3 connection. USB 3.0 Controller FPGA synthesis and place and route will also be covered.
|Standard SDC & Clock Issues in Complex FPGA Designs |
Laurent Sol, Xavier Mathes [Synopsys France]
As FPGA designs are growing in size and complexity, it is becoming mandatory to define accurate design constraints in order to guarantee a correct behavior of FPGA designs similarly to what has been done for many years in ASIC designs. With this purpose, all FPGA implementation tools are moving to the Standard Design Constraint format which guarantees the same interpretation of the design constraint all along the design process. This leads to increasing design predictability. Additionally, accurate timing constraints are crucial to a successful gated-clock conversion for ASIC FPGA-based prototypes. In this session you will learn how Synplify Pro and Synplify Premier handle Standard Design Constraints and design techniques for successful gated clock conversion.
Target Audience: Intermediate; Design engineers, engineering managers, validation engineers, FPGA designers
|A6 User Session: AMS Verification and Sign-off|
|Methodology for ST NVM Technologies Description Turned to Interconnect Parasitic Extraction with StarRC and to the Memory Cell Characterization with Rapid3D|
Marina Gratarola, Silvia Lesma, Luca Togni [STMicroelectronics], Claudio Rallo [Synopsys]
The presence of two different polysilicon process layers into the NVM technologies, with one of them staying at a different level according to the presence or lack of the other one, pointed out a limitation in the StarRC capability to describe complex layer stacks. The presence of conformal dielectrics and of other SRAM dedicated layers has furthermore complicated the cross section. The solution found to correctly customize the StarRC technology files for these technologies involves a new version of an already-existing itf statement. This article describes the solution, the validation methodology and its application using StarRC and Rapid3D.
|Case Study: Correlating PrimeTime with SPICE |
Casey McCoy [Atmel Corporation]
An automated methodology offered by Synopsys is employed for correlating PrimeTime with HSPICE simulation, in order to assess library quality and PrimeTime accuracy. Being integral to the ASIC design flow, PrimeTime is subject to review during failure analysis, and electrical simulation (HSPICE) serves as the reference. Correlation methodology is presented with modifications. Statistics-based graphical results highlight significant discrepancies. Certain cell types and paths are investigated based upon discrepancies, using the methodology iteratively. Multiple causes of discrepancy are identified. Remedies are applied, and subsequent correlation is improved to within expectations.
|Groundbreaking SQL Method to Analyze Circuit Check Reports |
Pierluigi Daglio, Salvatore Santapa, Alessandro Valerio [STMicroelectronics]
Verification of complex SoCs (integrating third-party IP modules) and custom ASICs is becoming more complex year-by-year and connectivity errors in the assembly phase are quite common. HSIMplus Static Circuit Check capability helps designers find design problems before the simulation phase. Based on a heuristic methodology, unfortunately it also produces a huge amount of false errors. In this paper, we present a Structured Query Language (SQL) based approach, together with a user-friendly Tcl/Tk interface, able to analyze massive number of violations and to generate waivers for false violations. Grouping, filtering and sorting mechanisms are also supported. Moreover, a bottom-up methodology avoids finding false errors when integrating IPs at a higher level of hierarchy in the design enabling the verification of complex SoCs. Finally, the verification process becomes safer, faster and more productive.
|Thursday, June 14, 2012|
1:30 PM - 3:00 PM
|B1 Tutorial Session: Front-End IP Integration|
|Galaxy Constraints Analyzer Intro, Update & Demo|
Emmanuel Pluchart [Synopsys France]
Today’s SoC designs are extremely complex with tight design schedules. Any change to timing constraints can have a significant impact on timing results and time to tapeout. After providing some background information on the technology, we will highlight actual and future tools usage/capabilities. Among them: SDC-to-SDC to analyze the differences between two SDC files for unintended behavior changes, Block-to-Top consistency, 2011.12 highlights, etc. This tutorial will also demonstrate how to use and navigate through the GUI, run scripts, main commands to know and useful rules through a short “live” demo.
Target audience: Design implementation engineers and managers looking for a solution to drastically reduce the time needed to provide clean constraint definitions.
|Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair |
Zaka Bhatti [Synopsys, Inc.]
Selection of memory compilers and logic libraries has significant impact on the power, performance and area of SoC designs. This tutorial presents best practices for implementing the optimal combination of memories, libraries and embedded test and repair to meet your design requirements. Also, learn how the DesignWare Memory Compilers and Logic Libraries are used in conjunction with Synopsys tools including ICC and DC to deliver a high-performance, low-power and differentiated SoC design. Benchmarks on CPU and GPU implementations will also be shared.
Target audience: Design engineers, system architects
|B2 User & Tutorial Session: Testbench and Verification IP|
|A Beginner’s Guide to Using SystemC TLM-2.0 IP with UVM|
John Aynsley, David Long, Doug Smith [Doulos]
UVM 1.x includes support for the communication interfaces defined by the SystemC TLM-2.0 standard, although some implementation details differ. This enables integration of SystemC TLM-2.0 IP into a SystemVerilog UVM verification environment. The connection between SystemC and SystemVerilog currently requires a tool-specific language interface such as Synopsys TLI, since it is not yet implemented as part of UVM. This paper begins with a brief overview of TLM-2.0 aimed at novice users. It then discusses the steps required to add a SystemC TLM-2.0 model into a SystemVerilog UVM environment and simulate it with VCS. At each step, issues that users will face are explored and suggestions made for practical fixes, showing the relevant pieces of code. Finally, the paper gives a summary of areas where the UVM implementation of TLM-2.0 differs from the SystemC standard and proposes workarounds to ensure correct communication between the SystemVerilog and SystemC domains.
|Accelerated SoC Verification with Synopsys Discovery VIP for the ARM AMBA 4 ACE Protocol|
Chris Thompson [Synopsys Canada]
As the complexity and number of processor cores in SoC designs increase, so do the verification challenges. One such challenge is verifying hardware based cache coherency protocols used by these multi-core SoCs. Synopsys provides 100% SystemVerilog-based VIP that supports the ARM® AMBA® 4 AXI™ and ACE™ (AXI Coherency Extensions) protocols, as well as the UVM, VMM and OVM methodologies. Constrained-random sequences, protocol checks and coverage plans are also provided.
This tutorial describes how a reference verification platform built with the Discovery VIP for the AMBA ACE protocol can be utilized to accelerate the verification of multi-core SoCs. Also highlighted are Synopsys verification technologies like Discovery Visualization Environment (DVE) and Protocol Analyzer.
Target Audience: Design and verification engineers and managers
|B3 User and Combo Session: Clock Tree Synthesis & Sign-off|
|Asic Compliance CTMesh Solution|
CTMesh is a clock network introduced to cater the demand of high performance design. However, due to the mesh nature of the clock network, it posts challenge on clock tree implementation as well as STA signoff. The intent of this paper is to propose the systematic solution to implement CTMesh with less ping pong iteration between spice simulator and APR during clock tree synthesis stage as well as STA signoff solution on CTMesh network design.
|PrimeTime Usability Update & Multi-Scenario DRC Fixing|
Eric Zann [Synopsys France]
PrimeTime’s 2011.12 release adds to the existing extensive graphical design analysis & debug environment with new capabilities. This version also extends the production-proven ECO technology from earlier releases to multiple new areas of design rule constraint (DRC) fixing. Together, PrimeTime ECO enables you to perform ECO fixing for timing and DRC across multiple scenarios in parallel using CPU resources efficiently from your compute environment. New enhancements in DRC fixing include trade-offs for timing costs and a flexible approach to utilizing compute resources for multi-scenario fixing. This tutorial is for designers responsible for timing convergence and signoff and will show how users are effectively using PrimeTime’s graphical analysis capabilities, as well as the ECO solution with the latest ICC flows.
The tutorial will be followed by a Customer Testimonial:
|B4 User & Tutorial Session: Design for Test and ATPG II|
|Efficient Flow for the Debug of Compressed Scan Patterns During Serial Simulations |
Sébastien Rousset, Mathieu Thomas [Scaleo Chip]
The current ATPG pattern validation flow is mainly driven through a two-step approach. The first step focuses on compression bypass scan patterns that allow full debug capability at the expense of simulation time. The second step verifies the compressed patterns in simulation without debugging possibility. The presented flow is based on Dual STIL patterns and allows fast and easy debug of compressed patterns in serial mode. It uses the combination of internal scan chains definition, standard serial patterns and its associated parallel ones to allow simulation of compressed pattern to speed-up the ATPG verification, with the same debug capabilities as classical bypass pattern verification.
|Galaxy Test Update|
Jean-Pierre Popieul [Synopsys France]
This tutorial will provide the latest updates to DFTMAX Compression, TetraMAX ATPG and Yield Explorer. We will present the new DFTMAX “Shared IO architecture” that provides the capability to share I/Os across CODECs, reducing the overhead of top level ports. We will also present the latest features related to DFTMAX Serializer, and to low power. Presence of Xs in design is impacting the overall QoR in DFTMAX flows. We will study how to track down and eliminate X sources to improve QoR. Finally we will highlight how adding physical attributes improves yield and diagnostics debug. Target audience: Test and product engineers
|B5 User White Paper and Tutorial Session: Advanced FPGA Design Techniques|
|FPGA Hierarchical Design Techniques using Synopsys SynplifyPremier and Xilinx PlanAhead|
James McLenaghan [Xilinx], Xavier Mathes [Synopsys]
The latest Xilinx 7 Series FPGAs, built on a 28nm HPL process, allow the prototyping of very large and complex ASIC designs. The Virtex7 2000T contains over 2.4M flip-flops and 45 Mbits of on-chip SRAM, thus accommodating up to 20M equivalent ASIC gates. This dramatic increase in capacity and design size requires new implementation approaches to help preserve design performance between RTL iterations and improve the repeatability and stability of the development process. SynplifyPremier, through its Automatic and Manual Compile Point methodology, allows the definition of design partitions which help maintain the quality of results of the design. This approach allows incremental synthesis and Place and Route. This paper will describe how to set-up the Compile Point methodology in conjunction with PlanAhead’s Hierarchical Design capabilities and will showcase the benefits in terms of turn-around time and results preservation on real designs.
|Synopsys Cookbook to Reduce Congestion on Virtex6 Designs|
Laurent Sol [Synopsys France]
FPGA high utilization, aggressive timing constraints, placement issues, logic packing: there can be several root causes leading to congestion or routability issues in Virtex6 devices. These issues are highly design-dependant. Thus it is mandatory to accurately identify and diagnose the problem in order to adopt the correct strategy to fix it. In this session you will learn through case studies what causes congestion issues, how to correctly diagnose the problem and what solution should be adopted to solve it.
Target audience: Intermediate; design engineers, engineering managers, validation engineers, FPGA designers.
The tutorial will be followed by a Customer Testimonial:
Benoit Suffran, ST-Ericsson
|New Synopsys Implementation Flow for Xilinx Series 7|
Xavier Mathes [Synopsys]
With the Serie-7 devices, XILINX is moving away from its traditional EDIF and UCF formats and is introducing a new implementation flow for its backend that will rapidly replace the current ISE flow. This flow relies on new formats for design entry and constraints and uses a new approach for the implementation. In the session, you will learn how SynplifyPro and SynplifyPremier front-end tools interact with Xilinx’ new back-end, what Synopsys tool current level of support for these new devices is and what the known limitations are.
Target audience: Intermediate; design engineers, engineering managers, validation engineers, FPGA designers
|B6 User and Tutorial/Demo Session: Digital/Analog Co-Design|
|Bridging the Digital/Analog Gap in Design Implementation|
Giuseppe Conti [STMicroelectronics], Giuseppe Contarino [Synopsys Italy]
Modern silicon process technologies allows for the “seamless” integration of digital and analog functions onto a single chip, and demands for an equally “seamless” inter-operability between the respective design implementation flows. The flow proposed in this paper leverages on the newly developed link between IC Compiler and Custom Designer, to enable the rapid and reliable integration of digital blocks into analog chips (big A small D) and vice versa (small A big D), as well as handling the most complex digital and analog system-on-chip. The availability of a lossless, bi-directional bridge between Milkyway and OpenAccess makes it possible to perform tasks such as floorplanning, analog pre-routing, or post-routing analog editing, in a simple, efficient manner. A real test case has been used to illustrate the challenges and the solutions, highlighting the achieved results.
|Digital/Analog Co-design with IC Compiler and Custom Designer|
Guillaume Thomas [Synopsys]
In this tutorial you will learn how the Galaxy unified implementation solution enables design teams to easily move between digital and custom implementation flows, while maintaining design data integrity. The unified solution accelerates the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development, including the time-critical tape-out phase. See how Galaxy Custom Designer, with tight integration to IC Compiler, enables higher productivity through advanced features such as DRC/LVS correct interactive auto-routing and DRC-aware custom editing. A live demo will complement the tutorial.
Target audience: IC Compiler physical implementation engineers, layout designers that need to perform custom edits on an IC Compiler design, design engineering and CAD managers.
|Thursday, June 14, 2012|
3:30 PM - 5:00 PM
|C1 User & Tutorial Session: RTL Synthesis|
|An All-Inclusive Solution for Clock Domain Crossings|
Charles Laurent, Phuong Nguyen, Joseph Dekoker, Domenique Spagnuolo [Sigma Designs]
Asynchronous Clock Domain Crossings (CDCs) should always be carefully designed, especially at GHz speeds. This problem has been discussed in many papers but none of them have considered all of the aspects of CDCs - for example synthesis constraints are seldom mentioned. We will point out the potential issues of CDCs without carefully constructed synthesis constraints. In this paper, we present an all-inclusive solution for this problem - from design to synthesis and static timing analysis (STA) constraints. The solution is based on two elementary designs, one for control signals and the other for data path signals. Known problems for CDCs such as metastability, glitch, reconvergence, and timing constraints for a data path are solved by cell choice, synthesis and STA constraints. We will also show how to construct a CDC handshaking mechanism from these two elements as an example of implementation.
|Galaxy RTL: Design Compiler Family Update|
Alberto Baldi [Synopsys]
This tutorial presents the latest advancements in the Design Compiler family of products including DC Explorer, Design Compiler Graphical to help you achieve best-in-class quality-of-results in the shortest possible time. See how you can speed-up the development of high-quality RTL & constrains with DC Explorer for a faster design implementation and generate an early netlist to start physical exploration in IC Compiler even when your design data is incomplete. Learn methodologies to achieve superior design results while streamlining the flow for a faster, more predictable design implementation using physical guidance technology (SPG) in Design Compiler Graphical.
Target audience: Front End design, CAD and RTL design engineers/managers
|C2 Combo and Tutorial Session: Core Simulation|
|VCS Technologies and Testbench Methodologies for Achieving Higher Video Throughput|
Fabian Delguste [Synopsys]
Verification engineers always face the challenge of meeting the ever reducing time to market and always growing list of corner cases to verify. There are new technologies that can help elevate some of these challenges. They can be in the form of simulator features or by using new methodology in building the testbenches. This paper introduces the concept of designing a testbench using verification components in parallel and demonstrates how the SystemVerilog language constructs and VCS technology allows higher throughput of video frames than the traditional approach. The topics discussed apply to testbenches involving protocols like HDMI and MIPI. Target audience: Verification engineers, verification managers and team leads
The tutorial will be followed by a Customer Testimonial:
Marc Schmitz, ST-Ericsson
|Getting X propagation under Control|
Roger Ninane [Synopsys]
The X-optimism semantics of standard RTL simulation can lead to incorrect behavior which often conceals design bugs. These bugs lead to passing simulations and creating problems that are difficult to correct later in the flow. This tutorial explores a new method to address this problem that changes the X semantics in order to remove the incorrect results dues to X-optimism.
Target audience: Design and verification engineers and managers
|C3 User & Tutorial Session: Design Closure|
|Implementing an High-Performance Graphic Core with Synopsys Galaxy Platform in a Fast and Predictable Turnaround Time|
Pascal Teissier [STMicroelectronics]
Today, implementing a high performance core in an advanced design node below 45nm is challenging the traditional Place and Route flow. In addition, a very short schedule and a new set of RTL and SDC timing constraints without any Physical guidance for the Physical Implementation, push over the limit the risk for failure. This article will describe how, from the synthesis to the layout, using the latest technologies from Synopsys like Topographical Synthesis and Design Compiler Graphical (DCG) to improve timing, placement and area convergence with IC Compiler (ICC), Early exploration and feasibility in ICC for a faster and predictable turnaround time , ICC advanced Placement and Optimization (focal_opt) for aggressive timing closure, ICC Transparent Interface Optimization (TIO) for top level interface path optimization and finally close link to Primetime Signoff STA for final ECO (PT cheetah), the target frequency and the schedule can be achieved successfully.
|Optimized Implementation for High Performance Cores: Techniques for High Performance Cores Using Synopsys Galaxy Platform - ARM® Cortex™-A15 Case Study|
Herve Raffard [Synopsys]
Learn how to predictably achieve high performance while minimizing power. We will present an optimized implementation methodology for an ARM Cortex™-A15 processor core based on Synopsys’ Galaxy™ Implementation platform. This session will highlight the latest technologies/techniques in Design Compiler and IC Compiler used to achieve challenging performance/power targets. These include physical guidance, delay performance vs. area tradeoffs, leakage optimization, innovative methods to reduce slack across register stages during final timing closure, and more. We will examine benefit/cost tradeoffs of each technique; performance/ease of convergence and impact on schedule/turnaround time. We will also share results obtained using this combination of optimized methodology, tools and physical IP.
Target audience: Physical design, CAD and RTL design engineers/managers
|C4 User, Tutorial and R&D Session: Advanced Test Techniques|
|Custom LBIST Integration in an Automotive Design|
Marzia Annovazzi, Marcello Raimondi [STMicroelectronics]
The quality of silicon is increasingly important for all devices, especially for automotive applications where a defect could have serious consequences. In automotive products the request to use a Logic Bist test to identify new defects on field is becoming frequent too. When the devices are very small and without any memories inside, the area overhead prevent the use of the standard logic Bist insertion approaches. Our requirement was to reach very high test coverage with a Logic Bist on a very small device and to launch the LBist test using an FSM included in the device, without any communication with external devices.With the standard LBist integration flows we couldn't reach the required coverage and the area overhead was too big. Using some Synopsys IPs, with the Synopsys support, we implemented a custom simple solution, very useful for the small devices and we could satisfy all the requirements.
|Introduction to the Synopsys DesignWare STAR Memory System (SMS)|
Steven Oostdijk [Synopsys]
This tutorial will introduce attendees to memory test and diagnostics in advanced nodes and the Synopsys DesignWare® STAR Memory System™ IP that supports Memory Test. The DesignWare® Self-Test and Repair (STAR) Memory System is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or non-repairable embedded memories across any foundry or process node. Silicon-proven in over a billion chips on a range of process nodes, the STAR Memory System™ is a cost-effective solution for improving test quality and repair of manufacturing faults found in advanced processes. The STAR Memory System’s highly automated design implementation and diagnostic flow enables SoC designers to achieve quick design closure and significantly improve time-to-market and time-to-yield in volume production.
Target audience: DFT and RTL designers and architects, test and product engineers, foundry engineers
|R&D Session: Core Wrapping|
Frederic Neuveux [Synopsys]
During this session attendees will have the opportunity to directly interact with our R&D engineers working on the development of the Synopsys Galaxy Test Platform. Synopsys R&D will introduce the Core Wrapping technology, one of their current developments on Design for Test. We will conclude this session with a Q&A session.
Target audience: Test and product engineers
|C5 Tutorial & Demo Session: Custom Processors & Design Verification using FPGA Platforms|
|Programmable Hardware Accelerators made Easy: Rapid Prototyping of Custom Processors on HAPS without Compromising Performance, Power or Area|
Xavier Buisson [Synopsys]
Dealing with changes has become more important than ever and designers need to deal with growing performance and power efficiency demands while meeting time-to-market pressure: a solution is to replace fixed hardware implementations by a programmable hardware accelerator that is flexible enough to deal with multiple standards and use cases, while meeting power, performance and area constraints? In this session, you will learn how custom processors or Application Specific Instruction-set Processors can provide the right trade-off between flexibility and power, performance. You will also learn how Synopsys Processor Designer greatly eases the implementation and verification of custom processors by enabling the creation of the optimized RTL code, software tools as well as a SystemC model from a single formal input specification. Finally we will demonstrate how to use the Synopsys FPGA flow to quickly come to an FPGA-based prototype using HAPS Systems and UMRBus.
Target audience: Intermediate; design engineers, engineering managers, chip architects, validation engineers, FPGA designers
|Debug and Functional Verification using Latest Identify Features|
Laurent Sol [Synopsys]
FPGA based prototyping allow to perform at-speed verification of full System-On-Chips or IP and are commonly used for early software development and for hardware/software integration. Software debuggers are efficient tools for the validation of the software code but are not sufficient to find and debug hardware or design errors. The Identify product is a powerful FPGA verification tool that allows you to quickly find and correct functional design errors in hardware at system speed. In this session, you will learn how Identify can help gain visibility in FPGA prototypes. The tutorial will describe Identify 2012.03 new features such as Deep-Trace Debug, Debug Signal Banks and Sample compression.
Target audience: Intermediate; design engineers, engineering managers, chip architects, validation engineers, FPGA designers
|C6 Tutorial Session: Analog IPs & Circuit Simulation|
|The Evolving Integrated Communication AFE|
Manuel Mota [Synopsys]
The AFE is a critical element of the communications transceiver. This tutorial looks into the building blocks that make up the AFE and how its requirements continue to evolve as more advanced communications protocols are developed. The characteristics of the AFE for several communication system will be reviewed and best practices for its integration within today’s complex SoCs discussed. This tutorial also provides an overview of the DesignWare® Data Converter IP Portfolio and how it is used to create efficient analog interface solutions that are robust and meet the integration requirements of the SoC developers.
Target audience: Design engineers, system architects
|How to Get the Most from Your Circuit Simulation|
Beatrice Solignac [Synopsys]
This tutorial provides useful tips and tricks to reduce simulation time without compromising accuracy for CustomSim (XA). We will reveal performance and ease of use enhancements targeted for simulation of memory designs.
Target audience: Analog/mixed-signal design engineers, CAD managers & engineering managers