Micron and Samsung, the initial developing members of the HMCC, are working closely with Altera, IBM, Open-Silicon, Xilinx and now Microsoft to accelerate widespread industry adoption of HMC technology.
The technology will enable highly efficient memory solutions for applications ranging from industrial products to high-performance computing and large-scale networking. The HMCC's team of developers plans to deliver a draft interface specification to a growing number of adopters that are joining the consortium. Then, the combined team of developers and adopters will refine the draft and release a final interface specification at the end of this year.
Adopter membership in the HMCC is available to any company interested in joining the consortium and participating in the specification development. The HMCC has responded to interest from more than 75 prospective adopters.
As envisioned, HMC capabilities will leap beyond current and near-term memory architectures in the areas of performance, packaging and power efficiencies, offering a major shift from present memory technology. By opening new doors for developers, manufacturers and architects, the consortium is committed to making HMC a new standard in high-performance memory technology.
HMC technology represents a major step forward in the direction of increasing memory bandwidth and performance, while decreasing the energy and latency needed for moving data between the memory arrays and the processor cores, said KD Hallman, General Manager of Microsoft Strategic Software/Silicon Architectures. Harvesting this solution for various future systems could lead to better and/or novel digital experiences.
One of the primary challenges facing the industry -- and a key motivation for forming the HMCC -- is that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can provide. The term memory wall has been used to describe this dilemma. Breaking through the memory wall requires architecture such as the HMC that can provide increased density and bandwidth at significantly reduced power consumption.