ARM Technical Support Knowledge Articles
Cortex-A5 Knowledge Articles
Knowledge Articles in this section
Bus Interface (1)
Reset and Initialization (2)
Cortex-A9 MPCore and Cortex-A5 MPCore SMP initialization example
Do Cortex-A5 cache evictions generate INCR burst type transfers ?
How does Cortex-A5 make use of data linefill buffers 0 and 1 ?
How does the Cortex-A5 automatic data prefetcher work ?
How shold we connect Cortex-A5 to PL310 to assert PL310 idle when CPU is in standby ?
How should we initialise the L1 memories and what is the function of L1RSTDISABLE signal ?
Performance Monitor Unit example code for ARM11 and Cortex-A/R
Unused top level files in Cortex-A5
What is the purpose of WFI and WFE instructions and the event signals ?
When DMA writes via ACP to coherent memory, does it pollute the L1 cache ?
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