#ifndef CSR_DMA_H
#define CSR_DMA_H
#include "stdint.h"
#define CSR_DMA_DMA_CONTROL_GO_BIT_WIDTH 1
#define CSR_DMA_DMA_CONTROL_GO_BIT_MASK 0x1
#define CSR_DMA_DMA_CONTROL_GO_BIT_OFFSET 0
#define CSR_DMA_DMA_CONTROL_ABORT_BIT_WIDTH 1
#define CSR_DMA_DMA_CONTROL_ABORT_BIT_MASK 0x1
#define CSR_DMA_DMA_CONTROL_ABORT_BIT_OFFSET 1
#define CSR_DMA_DMA_CONTROL_MAX_BURST_BIT_WIDTH 8
#define CSR_DMA_DMA_CONTROL_MAX_BURST_BIT_MASK 0xff
#define CSR_DMA_DMA_CONTROL_MAX_BURST_BIT_OFFSET 2
#define CSR_DMA_DMA_CONTROL_BYTE_WIDTH 8
#define CSR_DMA_DMA_CONTROL_BYTE_SIZE 8
#define CSR_DMA_DMA_CONTROL_BYTE_OFFSET 0x0
#define CSR_DMA_DMA_STATUS_VERSION_BIT_WIDTH 16
#define CSR_DMA_DMA_STATUS_VERSION_BIT_MASK 0xffff
#define CSR_DMA_DMA_STATUS_VERSION_BIT_OFFSET 0
#define CSR_DMA_DMA_STATUS_DONE_BIT_WIDTH 1
#define CSR_DMA_DMA_STATUS_DONE_BIT_MASK 0x1
#define CSR_DMA_DMA_STATUS_DONE_BIT_OFFSET 16
#define CSR_DMA_DMA_STATUS_ERROR_BIT_WIDTH 1
#define CSR_DMA_DMA_STATUS_ERROR_BIT_MASK 0x1
#define CSR_DMA_DMA_STATUS_ERROR_BIT_OFFSET 17
#define CSR_DMA_DMA_STATUS_BYTE_WIDTH 8
#define CSR_DMA_DMA_STATUS_BYTE_SIZE 8
#define CSR_DMA_DMA_STATUS_BYTE_OFFSET 0x8
#define CSR_DMA_DMA_ERROR_ADDR_ERROR_ADDR_BIT_WIDTH 32
#define CSR_DMA_DMA_ERROR_ADDR_ERROR_ADDR_BIT_MASK 0xffffffff
#define CSR_DMA_DMA_ERROR_ADDR_ERROR_ADDR_BIT_OFFSET 0
#define CSR_DMA_DMA_ERROR_ADDR_BYTE_WIDTH 8
#define CSR_DMA_DMA_ERROR_ADDR_BYTE_SIZE 8
#define CSR_DMA_DMA_ERROR_ADDR_BYTE_OFFSET 0x10
#define CSR_DMA_DMA_ERROR_STATS_ERROR_TYPE_BIT_WIDTH 1
#define CSR_DMA_DMA_ERROR_STATS_ERROR_TYPE_BIT_MASK 0x1
#define CSR_DMA_DMA_ERROR_STATS_ERROR_TYPE_BIT_OFFSET 0
#define CSR_DMA_DMA_ERROR_STATS_ERROR_SRC_BIT_WIDTH 1
#define CSR_DMA_DMA_ERROR_STATS_ERROR_SRC_BIT_MASK 0x1
#define CSR_DMA_DMA_ERROR_STATS_ERROR_SRC_BIT_OFFSET 1
#define CSR_DMA_DMA_ERROR_STATS_ERROR_TRIG_BIT_WIDTH 1
#define CSR_DMA_DMA_ERROR_STATS_ERROR_TRIG_BIT_MASK 0x1
#define CSR_DMA_DMA_ERROR_STATS_ERROR_TRIG_BIT_OFFSET 2
#define CSR_DMA_DMA_ERROR_STATS_BYTE_WIDTH 8
#define CSR_DMA_DMA_ERROR_STATS_BYTE_SIZE 8
#define CSR_DMA_DMA_ERROR_STATS_BYTE_OFFSET 0x18
#define CSR_DMA_DMA_DESC_SRC_ADDR_SRC_ADDR_BIT_WIDTH 32
#define CSR_DMA_DMA_DESC_SRC_ADDR_SRC_ADDR_BIT_MASK 0xffffffff
#define CSR_DMA_DMA_DESC_SRC_ADDR_SRC_ADDR_BIT_OFFSET 0
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_0 0x20
#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_1 0x28
#define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_WIDTH 32
#define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_MASK 0xffffffff
#define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_OFFSET 0
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_0 0x30
#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_1 0x38
#define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_WIDTH 32
#define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_MASK 0xffffffff
#define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_OFFSET 0
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_0 0x40
#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_1 0x48
#define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_WIDTH 1
#define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_MASK 0x1
#define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_OFFSET 0
#define CSR_DMA_DMA_DESC_CFG_READ_MODE_BIT_WIDTH 1
#define CSR_DMA_DMA_DESC_CFG_READ_MODE_BIT_MASK 0x1
#define CSR_DMA_DMA_DESC_CFG_READ_MODE_BIT_OFFSET 1
#define CSR_DMA_DMA_DESC_CFG_ENABLE_BIT_WIDTH 1
#define CSR_DMA_DMA_DESC_CFG_ENABLE_BIT_MASK 0x1
#define CSR_DMA_DMA_DESC_CFG_ENABLE_BIT_OFFSET 2
#define CSR_DMA_DMA_DESC_CFG_BYTE_WIDTH 8
#define CSR_DMA_DMA_DESC_CFG_BYTE_SIZE 16
#define CSR_DMA_DMA_DESC_CFG_ARRAY_DIMENSION 1
#define CSR_DMA_DMA_DESC_CFG_ARRAY_SIZE_0 2
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_0 0x50
#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_1 0x58
typedef struct {
  uint64_t dma_control;
  uint64_t dma_status;
  uint64_t dma_error_addr;
  uint64_t dma_error_stats;
  uint64_t dma_desc_src_addr[2];
  uint64_t dma_desc_dst_addr[2];
  uint64_t dma_desc_num_bytes[2];
  uint64_t dma_desc_cfg[2];
  uint64_t __reserved_0x60;
  uint64_t __reserved_0x68;
  uint64_t __reserved_0x70;
  uint64_t __reserved_0x78;
  uint64_t __reserved_0x80;
  uint64_t __reserved_0x88;
  uint64_t __reserved_0x90;
  uint64_t __reserved_0x98;
  uint64_t __reserved_0xa0;
  uint64_t __reserved_0xa8;
  uint64_t __reserved_0xb0;
  uint64_t __reserved_0xb8;
  uint64_t __reserved_0xc0;
  uint64_t __reserved_0xc8;
  uint64_t __reserved_0xd0;
  uint64_t __reserved_0xd8;
  uint64_t __reserved_0xe0;
  uint64_t __reserved_0xe8;
  uint64_t __reserved_0xf0;
  uint64_t __reserved_0xf8;
} csr_dma_t;
#endif
