MDK-ARM/bsp/mpu6050_reg.h


#ifndef __6050_REG__
#define __6050_REG__


//#define MPU_ACCEL_OFFS_REG		0X06	//accel_offsĴ,ɶȡ汾,Ĵֲδᵽ
//#define MPU_PROD_ID_REG			0X0C	//prod idĴ,ڼĴֲδᵽ
#define MPU_SELF_TESTX_REG		0X0D	//ԼĴX
#define MPU_SELF_TESTY_REG		0X0E	//ԼĴY
#define MPU_SELF_TESTZ_REG		0X0F	//ԼĴZ
#define MPU_SELF_TESTA_REG		0X10	//ԼĴA
#define MPU_SAMPLE_RATE_REG		0X19	//ƵʷƵ
#define MPU_CFG_REG				0X1A	//üĴ
#define MPU_GYRO_CFG_REG		0X1B	//üĴ
#define MPU_ACCEL_CFG_REG		0X1C	//ٶȼüĴ
#define MPU_MOTION_DET_REG		0X1F	//˶ֵⷧüĴ
#define MPU_FIFO_EN_REG			0X23	//FIFOʹܼĴ
#define MPU_I2CMST_CTRL_REG		0X24	//IICƼĴ
#define MPU_I2CSLV0_ADDR_REG	0X25	//IICӻ0ַĴ
#define MPU_I2CSLV0_REG			0X26	//IICӻ0ݵַĴ
#define MPU_I2CSLV0_CTRL_REG	0X27	//IICӻ0ƼĴ
#define MPU_I2CSLV1_ADDR_REG	0X28	//IICӻ1ַĴ
#define MPU_I2CSLV1_REG			0X29	//IICӻ1ݵַĴ
#define MPU_I2CSLV1_CTRL_REG	0X2A	//IICӻ1ƼĴ
#define MPU_I2CSLV2_ADDR_REG	0X2B	//IICӻ2ַĴ
#define MPU_I2CSLV2_REG			0X2C	//IICӻ2ݵַĴ
#define MPU_I2CSLV2_CTRL_REG	0X2D	//IICӻ2ƼĴ
#define MPU_I2CSLV3_ADDR_REG	0X2E	//IICӻ3ַĴ
#define MPU_I2CSLV3_REG			0X2F	//IICӻ3ݵַĴ
#define MPU_I2CSLV3_CTRL_REG	0X30	//IICӻ3ƼĴ
#define MPU_I2CSLV4_ADDR_REG	0X31	//IICӻ4ַĴ
#define MPU_I2CSLV4_REG			0X32	//IICӻ4ݵַĴ
#define MPU_I2CSLV4_DO_REG		0X33	//IICӻ4дݼĴ
#define MPU_I2CSLV4_CTRL_REG	0X34	//IICӻ4ƼĴ
#define MPU_I2CSLV4_DI_REG		0X35	//IICӻ4ݼĴ

#define MPU_I2CMST_STA_REG		0X36	//IIC״̬Ĵ
#define MPU_INTBP_CFG_REG		0X37	//ж/·üĴ
#define MPU_INT_EN_REG			0X38	//жʹܼĴ
#define MPU_INT_STA_REG			0X3A	//ж״̬Ĵ

#define MPU_ACCEL_XOUTH_REG		0X3B	//ٶֵ,X8λĴ
#define MPU_ACCEL_XOUTL_REG		0X3C	//ٶֵ,X8λĴ
#define MPU_ACCEL_YOUTH_REG		0X3D	//ٶֵ,Y8λĴ
#define MPU_ACCEL_YOUTL_REG		0X3E	//ٶֵ,Y8λĴ
#define MPU_ACCEL_ZOUTH_REG		0X3F	//ٶֵ,Z8λĴ
#define MPU_ACCEL_ZOUTL_REG		0X40	//ٶֵ,Z8λĴ

#define MPU_TEMP_OUTH_REG		0X41	//¶ֵ߰λĴ
#define MPU_TEMP_OUTL_REG		0X42	//¶ֵ8λĴ

#define MPU_GYRO_XOUTH_REG		0X43	//ֵ,X8λĴ
#define MPU_GYRO_XOUTL_REG		0X44	//ֵ,X8λĴ
#define MPU_GYRO_YOUTH_REG		0X45	//ֵ,Y8λĴ
#define MPU_GYRO_YOUTL_REG		0X46	//ֵ,Y8λĴ
#define MPU_GYRO_ZOUTH_REG		0X47	//ֵ,Z8λĴ
#define MPU_GYRO_ZOUTL_REG		0X48	//ֵ,Z8λĴ

#define MPU_I2CSLV0_DO_REG		0X63	//IICӻ0ݼĴ
#define MPU_I2CSLV1_DO_REG		0X64	//IICӻ1ݼĴ
#define MPU_I2CSLV2_DO_REG		0X65	//IICӻ2ݼĴ
#define MPU_I2CSLV3_DO_REG		0X66	//IICӻ3ݼĴ

#define MPU_I2CMST_DELAY_REG	0X67	//IICʱĴ
#define MPU_SIGPATH_RST_REG		0X68	//źͨλĴ
#define MPU_MDETECT_CTRL_REG	0X69	//˶ƼĴ
#define MPU_USER_CTRL_REG		0X6A	//ûƼĴ
#define MPU_PWR_MGMT1_REG		0X6B	//ԴĴ1
#define MPU_PWR_MGMT2_REG		0X6C	//ԴĴ2 
#define MPU_FIFO_CNTH_REG		0X72	//FIFOĴ߰λ
#define MPU_FIFO_CNTL_REG		0X73	//FIFOĴͰλ
#define MPU_FIFO_RW_REG			0X74	//FIFOдĴ
#define MPU_DEVICE_ID_REG		0X75	//IDĴ
 
#define MPU6050_ID					0x68

#endif

