Datasets:

HPAI-BSC
/

NotSoTiny-25-12

task_id stringlengths 16 24	shuttle_name stringclasses 7 values	project_name stringlengths 12 79	task_name stringlengths 7 59	top_module_name stringlengths 9 54	system_message stringclasses 1 value	prompt stringlengths 724 368k	golden_module stringlengths 66 320k
tt06-finale_0001	tt06-finale	CEJMU-tt06_tinyrv1	task_alu	tt_um_cejmu_riscv	You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with: // >>> Module Implementation Begin // <<< Module Implementation End Your ta...	/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */ module alu(clk, reset, a, b, instruction, rd); // >>> Module Implementation Begin // <<< Module Implementation End endmodule module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fet...	module alu(clk, reset, a, b, instruction, rd); wire _00_; wire _01_; wire _02_; wire _03_; wire _04_; wire _05_; wire _06_; wire _07_; wire _08_; wire _09_; wire _10_; wire _11_; wire _12_; wire _13_; wire _14_; wire [31:0] _15_; wire _16_; wire _17_; wire _18_; wire _19_; wire...
tt06-finale_0002	tt06-finale	CEJMU-tt06_tinyrv1	task_control	tt_um_cejmu_riscv	You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with: // >>> Module Implementation Begin // <<< Module Implementation End Your ta...	/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */ module alu(clk, reset, a, b, instruction, rd); wire _00_; wire _01_; wire _02_; wire _03_; wire _04_; wire _05_; wire _06_; wire _07_; wire _08_; wire _09_; wire _10_; wire _11_; wire _12_; wire _13_...	module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req); wire _000_; wire _001_; wire _002_; wire [2:0] _003_; wire _004_; wire _005_; wire _006_; wire _007_; wire _008_; wire _009_; wire _010_; wire _011_; wire [2:0] _012_; wire _01...
tt06-finale_0003	tt06-finale	CEJMU-tt06_tinyrv1	task_cpu	tt_um_cejmu_riscv	You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with: // >>> Module Implementation Begin // <<< Module Implementation End Your ta...	/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */ module alu(clk, reset, a, b, instruction, rd); wire _00_; wire _01_; wire _02_; wire _03_; wire _04_; wire _05_; wire _06_; wire _07_; wire _08_; wire _09_; wire _10_; wire _11_; wire _12_; wire _13_...	module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1); wire [31:0] _00_; wire [31:0] _01_; wire [12:0] _02_; wire [31:0] _03_; wire [31:0] _04_; wire [6:0] _05_; wire _06_; wire _07_; wire _08_; wire _09_; wire _10_; wire [31:0] _11_; wire [31:0] _12_; wire [...
tt06-finale_0004	tt06-finale	CEJMU-tt06_tinyrv1	task_instructioncounter	tt_um_cejmu_riscv	"You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)	"/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)	"module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);\n wire [15:0] _0(...TRUNCATED)
tt06-finale_0005	tt06-finale	CEJMU-tt06_tinyrv1	task_regs	tt_um_cejmu_riscv	"You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)	"/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)	"module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);\n wire [31:0] _000_;\n(...TRUNCATED)
tt06-finale_0006	tt06-finale	CEJMU-tt06_tinyrv1	task_spi_master	tt_um_cejmu_riscv	"You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)	"/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)	"module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_vali(...TRUNCATED)
tt06-finale_0007	tt06-finale	CEJMU-tt06_tinyrv1	task_tt_um_cejmu_riscv	tt_um_cejmu_riscv	"You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)	"/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */\n\nmodu(...TRUNCATED)	"module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);\n wire _0_;\n (...TRUNCATED)
tt06-finale_0008	tt06-finale	CKPope-tt06-verilog-template	task_Compx1	tt_um_CKPope_top	"You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)	"module tt_um_CKPope_top \n(\n input wire [7:0] ui_in, // Dedicated inputs for X and Y Target(...TRUNCATED)	"module Compx1\n(\n input a,\n\tinput b,\n \toutput reg aeqb,\t\t\n\toutput reg agtb,\t\t\n\toutpu(...TRUNCATED)
tt06-finale_0009	tt06-finale	CKPope-tt06-verilog-template	task_Compx4	tt_um_CKPope_top	"You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)	"module tt_um_CKPope_top \n(\n input wire [7:0] ui_in, // Dedicated inputs for X and Y Target(...TRUNCATED)	"module Compx4\n(\n input [3:0] a_hex,\n\tinput [3:0] b_hex,\n \toutput reg a_eq_b,\t\t\n\toutput (...TRUNCATED)
tt06-finale_0010	tt06-finale	CKPope-tt06-verilog-template	task_Mealy_SM	tt_um_CKPope_top	"You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are giv(...TRUNCATED)	"module tt_um_CKPope_top \n(\n input wire [7:0] ui_in, // Dedicated inputs for X and Y Target(...TRUNCATED)	"module Mealy_SM\n(\n input clk,\n input reset,\t \n input motion,\n input x_comp_eq,\n inp(...TRUNCATED)

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NotSoTiny: A Large, Living Benchmark for RTL Code Generation

Summary

NotSoTiny is a large, structurally rich, and "living" benchmark designed to assess Large Language Models (LLMs) on the generation of context-aware RTL (Register-Transfer Level) code. Built from hundreds of real hardware designs produced by the Tiny Tapeout community, this benchmark overcomes the limitations of prior static datasets by periodically incorporating new designs, making it resilient to data contamination.

Unlike previous benchmarks which rely on standalone modules or explicit specifications, NotSoTiny focuses on contextual module completion. In this setup, models are presented with a full design context, where one module is masked. The LLM must infer the missing module's functionality and interface solely from the surrounding implementation, mirroring real-world development scenarios where new components must integrate into existing systems.

This dataset includes the 25-12 release, with 1,114 deduplicated and curated tasks derived from real, taped-out hardware designs, making it significantly larger and more complex than existing RTL benchmarks.

Supported Tasks and Leaderboards

Task: module-completion (Hardware (Verilog) Code Completion).
Leaderboard: Solutions are evaluated using syntex checks and functional correctness through Formal Equivalence Checking (via Yosys). A leaderboard tracking model performance is available in the TuRTLe Leaderboard.

Languages

The dataset contains:

Verilog (for hardware designs, prompts, and golden modules).
English (for system messages and metadata).

Dataset Structure

Data Instances

Each row in the dataset represents a single module completion task. The model is given a system_message and a prompt (containing the context file task.v), and is expected to generate the missing Verilog code that matches the functionality of the golden_module.

Data Fields

task_id (string): A unique identifier for the task, formatted as <shuttle_name>_<incremental_number>.
shuttle_name (string): The identifier of the Tiny Tapeout shuttle from which the design originated (e.g., TT06, TT08).
project_name (string): The name of the original Tiny Tapeout project containing the task.
task_name (string): The name of the task directory, corresponding to the specific design module being tested.
system_message (string): A unified system prompt (same for all tasks) used to instruct the LLM.
prompt (string): The content of task.v. This contains the surrounding design context with the target module missing, serving as the input for the LLM.
golden_module (string): The content of original_module.v. This is the ground truth implementation of the maked module, used for formal verification.

Data Splits

The 25-12 release consists of a single split containing 1,114 validated tasks. These tasks are derived from multiple Tiny Tapeout shuttles (TT06, TT07, TT08, TT09, TT10 IHP-02, TT10 IHP-25a, and TTsky25a).

Dataset Creation

Curation Rationale

Current RTL benchmarks suffer from insufficient scale, shallow verification protocols, and a high risk of training data contamination. NotSoTiny was created to address these issues by:

Scale & Complexity: Providing tasks with deeper hierarchies and complex control/datapath interactions typical of real hardware.
Living Nature: Utilizing the continuous release schedule of Tiny Tapeout shuttles to constantly refresh the benchmark, keeping it ahead of LLM training data.
Rigorous Verification: Using formal equivalence checking to ensure functional correctness, as simulation testbenches were found to have low coverage.

Source Data

The designs are sourced from the Tiny Tapeout project repositories on GitHub. These are open-source digital, mixed-signal, and analog circuits submitted by researchers and engineers for fabrication.

Data Processing

The dataset construction pipeline follows these steps:

Filtering: Projects are filtered to ensure they contain valid src/ and test/ directories, a Makefile, and a valid info.yaml.
Module Aggregation: The vppreproc tool is used to merge project files into a single self-contained Verilog file, preserving internal hierarchies.
Task Building: Each aggregated design is decomposed into multiple tasks. For each task, the body of one module is removed (to be generated), while the remaining modules serve as context.
Temporal Deduplication: To prevent data leakage and redundancy, designs are deduplicated across shuttles using MinHash and Locality-Sensitive Hashing (LSH). If duplicates exist, only the version from the oldest shuttle is retained.
Self-Verification: A final validation step ensures compatibility by verifying the golden solution against itself using the general Yosys formal verification script. Only tasks that pass this check are included.

Considerations for Using the Data

To use this dataset for benchmarking, it is highly recommended to integrate with the TuRTLe framework. TuRTLe is a unified evaluation framework designed to automate the entire benchmarking pipeline for RTL generation.

Specifically, the framework handles:

Model Serving: It manages model interactions and generation requests.
Processing & Verification: It executes all necessary processing steps, from initial syntax validation to rigorous Formal Equivalence Checking (using Yosys) against the golden_module.
Final Reporting: It calculates and outputs the final performance results hsing standardized metrics.

Additional Information

License

The dataset is released under the Apache License 2.0.

Citation Information

@misc{ghorab2025notsotinylargelivingbenchmark,
      title={NotSoTiny: A Large, Living Benchmark for RTL Code Generation}, 
      author={Razine Moundir Ghorab and Emanuele Parisi and Cristian Gutierrez-Gomez and Miquel Albert\'i-Binimelis and Miquel Moreto and Dario Garcia-Gasulla and Gokcen Kestor},
      year={2025},
      eprint={2512.20823},
      archivePrefix={arXiv},
      primaryClass={cs.AR},
      url={[https://arxiv.org/abs/2512.20823](https://arxiv.org/abs/2512.20823)}, 
}

Acknowledgements

The HPAI team behind NotSoTiny would like to thank the Tiny Tapeout community for the open source efforts, which made possible this contribution. Special thanks to Matt Venn for his support.

Downloads last month: 45

Size of downloaded dataset files:

38.7 MB

Size of the auto-converted Parquet files:

7.6 MB

Number of rows:

1,114

Collection including HPAI-BSC/NotSoTiny-25-12

LLMs for Chip Design

Collection

Benchmarks, datasets and other resources related with LLM models tuned for chip design. • 5 items • Updated Feb 17 • 2

Paper for HPAI-BSC/NotSoTiny-25-12

NotSoTiny: A Large, Living Benchmark for RTL Code Generation

Paper • 2512.20823 • Published Dec 23, 2025