stack : 48;
#endif
	};
	uint64_t val;
} pore_pc_stack0_reg;

#define PORE_ID_FLAGS_VALID_BITS 0xffffffffffffff0full

typedef union {
	struct {
#if (__BYTE_ORDER == __BIG_ENDIAN)
		uint64_t reserved0 : 32;	/* 0..31 */
		uint64_t pib_parity_fail : 1;	/* 32 */
		uint64_t pib_status : 3;	/* 33..35 */
		uint64_t oci_parity_fail : 1;	/* 36 */
		uint64_t oci_status : 3;	/* 37..39 */
		uint64_t reserved1 : 8;		/* 40..47 */
		uint64_t ugt : 1;		/* 48 unsigned greater than */
		uint64_t ult : 1;		/* 49 unsigned less than */
		uint64_t sgt : 1;		/* 50 signed greater than */
		uint64_t slt : 1;		/* 51 signed smaller than */
		uint64_t c : 1;			/* 52 carry */
		uint64_t o : 1;			/* 53 overflow */
		uint64_t n : 1;			/* 54 negative */
		uint64_t z : 1;			/* 55 zero flag */
		uint64_t reserved2 : 4;		/* 56..59 */
		uint64_t ibuf_id : 4;		/* 60..63 */
#else
		uint64_t ibuf_id : 4;
		uint64_t reserved2 : 4;
		uint64_t z : 1;
		uint64_t n : 1;
		uint64_t o : 1;
		uint64_t c : 1;
		uint64_t slt : 1;
		uint64_t sgt : 1;
		uint64_t ult : 1;
		uint64_t ugt : 1;
		uint64_t reserved1 : 8;
		uint64_t oci_status : 3;
		uint64_t oci_parity_fail : 1;
		uint64_t pib_status : 3;
		uint64_t pib_parity_fail : 1;
		uint64_t reserved0 : 32;
#endif
	};
	uint64_t val;
} pore_id_flags_reg;

#define PORE_MEMORY_RELOC_VALID_BITS 0x00000003fffff000ull

typedef union {
	struct {
#if (__BYTE_ORDER == __BIG_ENDIAN)
		uint64_t reserved0 : 30;
		uint64_t memory_reloc_region : 2;
		uint64_t memory_reloc_base : 20;
		uint64_t reserved1 : 12;
#else
		uint64_t reserved1 : 12;
		uint64_t memory_reloc_base : 20;
		uint64_t memory_reloc_region : 2;
		uint64_t reserved0 : 30;
#endif
	};
	uint64_t val;
} pore_memory_reloc_reg;

#define PORE_DATA0_VALID_BITS 0xffffffff00000000ull

#define PORE_I2C_E0_PARAM_VALID_BITS 0xff3f7fff00000000ull
#define PORE_I2C_E1_PARAM_VALID_BITS 0xff3f7ff000000000ull
#define PORE_I2C_E2_PARAM_VALID_BITS 0xff3f7ff000000000ull

typedef union {
	struct {
#if (__BYTE_ORDER == __BIG_ENDIAN)
		uint64_t i2c_engine_identifier : 4;
		uint64_t i2c_engine_address_range : 4;
		uint64_t reserved1 : 2;
		uint64_t i2c_engine_port : 6;
		uint64_t reserved2 : 1;
		uint64_t i2c_engine_device_id : 7;
		uint64_t i2c_engine_speed : 8;
		uint64_t reserved0 : 32;
#else
		uint64_t reserved0 : 32;
		uint64_t i2c_engine_speed : 8;
		uint64_t i2c_engine_device_id : 7;
		uint64_t reserved2 : 1;
		uint64_t i2c_engine_port : 6;
		uint64_t reserved1 : 2;
		uint64_t i2c_engine_address_range : 4;
		uint64_t i2c_engine_identifier : 4;

#endif
	};
	uint64_t val;
} pore_i2c_en_param_reg;

typedef union {
	struct {
#if (__BYTE_ORDER == __BIG_ENDIAN)
		uint32_t r_n_w : 1;
		uint32_t bc  : 1;
		uint32_t chiplet_select : 6;
		uint32_t res0 : 4;
		uint32_t port : 4;
		uint32_t region_select : 8;
		uint32_t res1 : 4;
		uint32_t type_sel_bin : 4;
#else
		uint32_t type_sel_bin : 4;
		uint32_t res1 : 4;
		uint32_t region_select : 8;
		uint32_t port : 4;
		uint32_t res0 : 4;
		uint32_t chiplet_select : 6;
		uint32_t bc  : 1;
		uint32_t r_w : 1;
#endif
	};
	uint32_t val;
} shift_eng_cmd_reg;

typedef union {
	struct {
#if (__BYTE_ORDER == __BIG_ENDIAN)
		uint64_t region_select : 8;
		uint64_t res0 : 8;
		uint64_t type_sel_unary : 16;
		uint64_t res1 : 32;
#else
		uint64_t res1 : 32;
		uint64_t type_sel_unary : 16;
		uint64_t res0 : 8;
		uint64_t region_select : 8;
#endif
	};
	uint64_t val;
} scan_type_select_reg;

/* Scan controller register */
#define SCAN_REGION_OFFSET	0x0007
#define SCAN_DATA_OFFSET(cDR, uDR, bits) (0x8000	      |	\
					  ((cDR) & 0x1) << 14 |	\
					  ((uDR) & 0x1) << 13 |	\
					  ((bits) & 0x3f))

#ifndef FASTI2C_BASE_OFFSET
/* #  define FASTI2C_BASE_OFFSET    0x00008000 */
#  define FASTI2C_BASE_OFFSET    0x00000000 /* new default */
#endif

#define FASTI2C_CONTROL_OFFSET   (FASTI2C_BASE_OFFSET + 0x00000000)
#define FASTI2C_RESET_OFFSET     (FASTI2C_BASE_OFFSET + 0x00000001)
#define FASTI2C_STATUS_OFFSET    (FASTI2C_BASE_OFFSET + 0x00000002)
#define FASTI2C_DATA_OFFSET      (FASTI2C_BASE_OFFSET + 0x00000003)

typedef union {
	struct {
#if (__BYTE_ORDER == __BIG_ENDIAN)
		uint64_t with_start : 1;
		uint64_t with_address : 1;
		uint64_t read_continue : 1;
		uint64_t with_stop : 1;
		uint64_t data_length : 4;
		uint64_t device_address : 7;
		uint64_t read_not_write : 1;

		uint64_t speed : 2;
		uint64_t port_number : 5;
		uint64_t address_range : 3;
		uint64_t _reserved0 : 6;

		uint64_t data0 : 8;
		uint64_t data1 : 8;
		uint64_t data2 : 8;
		uint64_t data3 : 8;
#else
		uint64_t data3 : 8;
		uint64_t data2 : 8;
		uint64_t data1 : 8;
		uint64_t data0 : 8;
		uint64