
  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
  *
  *         (*) value not defined in all devices.
  * @retval None
  */
__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
{
#if defined(RCC_D1CCIPR_FMCSEL)
  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
#else
  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
#endif /*  */
  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
}

/**
  * @brief  Configure USARTx clock source
  * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n
  *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource
  * @param  ClkSource This parameter can be one of the following values:
  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
  *         @arg @ref LL_RCC_USART234578_CL