<s>
No	O
instruction	B-General_Concept
set	I-General_Concept
computing	O
(	O
NISC	O
)	O
is	O
a	O
computing	B-General_Concept
architecture	I-General_Concept
and	O
compiler	B-Language
technology	O
for	O
designing	O
highly	O
efficient	O
custom	O
processors	O
and	O
hardware	O
accelerators	O
by	O
allowing	O
a	O
compiler	B-Language
to	O
have	O
low-level	O
control	O
of	O
hardware	O
resources	O
.	O
</s>
<s>
The	O
term	O
"	O
statically	O
scheduled	O
"	O
means	O
that	O
the	O
operation	O
scheduling	O
and	O
Hazard	B-General_Concept
handling	O
are	O
done	O
by	O
a	O
compiler	B-Language
.	O
</s>
<s>
The	O
term	O
"	O
horizontal	O
nanocoded	O
"	O
means	O
that	O
NISC	O
does	O
not	O
have	O
any	O
predefined	O
instruction	B-General_Concept
set	I-General_Concept
or	O
microcode	B-Device
.	O
</s>
<s>
The	O
compiler	B-Language
generates	O
nanocodes	B-Device
which	O
directly	O
control	O
functional	B-General_Concept
units	I-General_Concept
,	O
registers	O
and	O
multiplexers	B-Protocol
of	O
a	O
given	O
datapath	B-General_Concept
.	O
</s>
<s>
Giving	O
low-level	O
control	O
to	O
the	O
compiler	B-Language
enables	O
better	O
utilization	O
of	O
datapath	B-General_Concept
resources	O
,	O
which	O
ultimately	O
result	O
in	O
better	O
performance	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
and	O
controller	O
of	O
processors	O
are	O
the	O
most	O
tedious	O
and	O
time-consuming	O
parts	O
to	O
design	O
.	O
</s>
<s>
Furthermore	O
,	O
the	O
datapath	B-General_Concept
of	O
NISC	O
processors	O
can	O
even	O
be	O
generated	O
automatically	O
for	O
a	O
given	O
application	O
.	O
</s>
<s>
Since	O
NISC	O
datapaths	B-General_Concept
are	O
very	O
efficient	O
and	O
can	O
be	O
generated	O
automatically	O
,	O
NISC	O
technology	O
is	O
comparable	O
to	O
high	B-General_Concept
level	I-General_Concept
synthesis	I-General_Concept
(	O
HLS	O
)	O
or	O
C	B-Application
to	I-Application
HDL	I-Application
synthesis	O
approaches	O
.	O
</s>
<s>
In	O
fact	O
,	O
one	O
of	O
the	O
benefits	O
of	O
this	O
architecture	O
style	O
is	O
its	O
capability	O
to	O
bridge	O
these	O
two	O
technologies	O
(	O
custom	O
processor	B-General_Concept
design	O
and	O
HLS	O
)	O
.	O
</s>
<s>
In	O
computer	B-General_Concept
science	I-General_Concept
,	O
zero	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
computer	I-General_Concept
(	O
ZISC	O
)	O
refers	O
to	O
a	O
computer	B-General_Concept
architecture	I-General_Concept
based	O
solely	O
on	O
pattern	B-Language
matching	I-Language
and	O
absence	O
of	O
(	O
micro	O
-	O
)	O
instructions	O
in	O
the	O
classical	O
sense	O
.	O
</s>
<s>
These	O
chips	O
are	O
known	O
for	O
being	O
thought	O
of	O
as	O
comparable	O
to	O
the	O
neural	B-Architecture
networks	I-Architecture
,	O
being	O
marketed	O
for	O
the	O
number	O
of	O
"	O
synapses	O
"	O
and	O
"	O
neurons	O
"	O
.	O
</s>
<s>
The	O
acronym	O
ZISC	O
alludes	O
to	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
.	O
</s>
<s>
ZISC	O
is	O
a	O
hardware	O
implementation	O
of	O
Kohonen	B-Algorithm
networks	I-Algorithm
(	O
artificial	B-Architecture
neural	I-Architecture
networks	I-Architecture
)	O
allowing	O
massively	O
parallel	O
processing	O
of	O
very	O
simple	O
data	O
(	O
0	O
or	O
1	O
)	O
.	O
</s>
<s>
According	O
to	O
TechCrunch	O
,	O
software	O
emulations	O
of	O
these	O
types	O
of	O
chips	O
are	O
currently	O
used	O
for	O
image	O
recognition	O
by	O
many	O
large	O
tech	O
companies	O
,	O
such	O
as	O
Facebook	B-Application
and	O
Google	B-Application
.	I-Application
</s>
<s>
Junko	O
Yoshida	O
,	O
of	O
the	O
EE	O
Times	O
,	O
compared	O
the	O
NeuroMem	O
chip	O
with	O
"	O
The	O
Machine	O
"	O
,	O
a	O
machine	O
capable	O
of	O
being	O
able	O
to	O
predict	O
crimes	O
from	O
scanning	O
people	O
's	O
faces	O
,	O
from	O
Person	O
of	O
Interest	O
(	O
TV	O
series	O
)	O
describing	O
it	O
as	O
"	O
the	O
heart	O
of	O
big	B-Application
data	I-Application
"	O
and	O
"foreshadow[ing]	O
a	O
real-life	O
escalation	O
in	O
the	O
era	O
of	O
massive	O
data	O
collection	O
"	O
.	O
</s>
<s>
In	O
the	O
past	O
,	O
microprocessor	O
design	O
technology	O
evolved	O
from	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	O
)	O
to	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
.	O
</s>
<s>
In	O
the	O
early	O
days	O
of	O
the	O
computer	O
industry	O
,	O
compiler	B-Language
technology	O
did	O
not	O
exist	O
and	O
programming	O
was	O
done	O
in	O
assembly	B-Language
language	I-Language
.	O
</s>
<s>
To	O
make	O
programming	O
easier	O
,	O
computer	B-General_Concept
architects	I-General_Concept
created	O
complex	O
instructions	O
which	O
were	O
direct	O
representations	O
of	O
high	O
level	O
functions	O
of	O
high	O
level	O
programming	O
languages	O
.	O
</s>
<s>
As	O
compiler	B-Language
and	O
memory	O
technologies	O
advanced	O
,	O
RISC	B-Architecture
architectures	I-Architecture
were	O
introduced	O
.	O
</s>
<s>
RISC	B-Architecture
architectures	I-Architecture
need	O
more	O
instruction	O
memory	O
and	O
require	O
a	O
compiler	B-Language
to	O
translate	O
high-level	O
languages	O
to	O
RISC	B-Architecture
assembly	B-Language
code	I-Language
.	O
</s>
<s>
Further	O
advancement	O
of	O
compiler	B-Language
and	O
memory	O
technologies	O
leads	O
to	O
emerging	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
processors	O
,	O
where	O
the	O
compiler	B-Language
controls	O
the	O
schedule	O
of	O
instructions	O
and	O
handles	O
data	O
hazards	B-General_Concept
.	O
</s>
<s>
NISC	O
is	O
a	O
successor	O
of	O
VLIW	B-General_Concept
processors	O
.	O
</s>
<s>
In	O
NISC	O
,	O
the	O
compiler	B-Language
has	O
both	O
horizontal	O
and	O
vertical	O
control	O
of	O
the	O
operations	O
in	O
the	O
datapath	B-General_Concept
.	O
</s>
