<s>
Zero	B-Application
ASIC	I-Application
Corporation	I-Application
,	O
formerly	O
Adapteva	B-Application
,	O
Inc.	O
,	O
is	O
a	O
fabless	B-Algorithm
semiconductor	I-Algorithm
company	I-Algorithm
focusing	O
on	O
low	O
power	O
many	B-General_Concept
core	I-General_Concept
microprocessor	B-Architecture
design	O
.	O
</s>
<s>
Adapteva	B-Application
was	O
founded	O
in	O
2008	O
with	O
the	O
goal	O
of	O
bringing	O
a	O
ten	O
times	O
advancement	O
in	O
floating-point	B-Algorithm
performance	O
per	O
watt	O
for	O
the	O
mobile	B-Application
device	I-Application
market	O
.	O
</s>
<s>
Products	O
are	O
based	O
on	O
its	O
Epiphany	O
multi-core	B-Architecture
multiple	B-Operating_System
instruction	I-Operating_System
,	I-Operating_System
multiple	I-Operating_System
data	I-Operating_System
(	O
MIMD	B-Operating_System
)	O
architecture	O
and	O
its	O
Parallella	O
Kickstarter	O
project	O
promoting	O
"	O
a	O
supercomputer	B-Architecture
for	O
everyone	O
"	O
in	O
September	O
2012	O
.	O
</s>
<s>
Adapteva	B-Application
was	O
founded	O
in	O
March	O
2008	O
,	O
by	O
Andreas	O
Olofsson	O
.	O
</s>
<s>
The	O
company	O
was	O
founded	O
with	O
the	O
goal	O
of	O
bringing	O
a	O
10×	O
advancement	O
in	O
floating-point	B-Algorithm
processing	O
energy	O
efficiency	O
for	O
the	O
mobile	B-Application
device	I-Application
market	O
.	O
</s>
<s>
In	O
May	O
2009	O
,	O
Olofsson	O
had	O
a	O
prototype	O
of	O
a	O
new	O
type	O
of	O
massively	B-Operating_System
parallel	I-Operating_System
multi-core	B-Architecture
computer	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
initial	O
prototype	O
was	O
implemented	O
in	O
65nm	O
and	O
had	O
16	O
independent	O
microprocessor	B-Architecture
cores	I-Architecture
.	O
</s>
<s>
The	O
initial	O
prototypes	O
enabled	O
Adapteva	B-Application
to	O
secure	O
US	O
$1.5	O
million	O
in	O
series-A	O
funding	O
from	O
BittWare	O
,	O
a	O
company	O
from	O
Concord	O
,	O
New	O
Hampshire	O
,	O
in	O
October	O
2009	O
.	O
</s>
<s>
Adapteva	B-Application
's	O
first	O
commercial	O
chip	O
product	O
started	O
sampling	O
to	O
customers	O
in	O
early	O
May	O
2011	O
and	O
they	O
soon	O
thereafter	O
announced	O
the	O
capability	O
to	O
put	O
up	O
to	O
4,096	O
cores	O
on	O
a	O
single	O
chip	O
.	O
</s>
<s>
Adapteva	B-Application
's	O
main	O
product	O
family	O
is	O
the	O
Epiphany	O
scalable	O
multi-core	B-Architecture
MIMD	B-Operating_System
architecture	O
.	O
</s>
<s>
The	O
Epiphany	O
architecture	O
could	O
accommodate	O
chips	O
with	O
up	O
to	O
4,096	O
RISC	B-Architecture
out-of-order	B-General_Concept
microprocessors	B-Architecture
,	O
all	O
sharing	O
a	O
single	O
32-bit	O
flat	O
memory	O
space	O
.	O
</s>
<s>
Each	O
RISC	B-Architecture
processor	I-Architecture
in	O
the	O
Epiphany	O
architecture	O
is	O
superscalar	B-General_Concept
with	O
64×	O
32-bit	O
unified	B-General_Concept
register	I-General_Concept
file	I-General_Concept
(	O
integer	O
or	O
single-precision	O
)	O
microprocessor	B-Architecture
operating	O
up	O
to	O
1GHz	O
and	O
capable	O
of	O
2GFLOPS	O
(	O
single-precision	O
)	O
.	O
</s>
<s>
Epiphany	O
's	O
RISC	B-Architecture
processors	I-Architecture
use	O
a	O
custom	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
optimised	O
for	O
single-precision	O
floating-point	B-Algorithm
,	O
but	O
are	O
programmable	O
in	O
high	O
level	O
ANSI	O
C	O
using	O
a	O
standard	O
GNU-GCC	B-Application
tool	O
chain	O
.	O
</s>
<s>
Each	O
RISC	B-Architecture
processor	I-Architecture
(	O
in	O
current	O
implementations	O
;	O
not	O
fixed	O
in	O
the	O
architecture	O
)	O
has	O
32KB	O
of	O
local	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Code	O
(	O
possibly	O
duplicated	O
in	O
each	O
core	O
)	O
and	O
stack	O
space	O
should	O
be	O
in	O
that	O
local	B-General_Concept
memory	I-General_Concept
;	O
in	O
addition	O
(	O
most	O
)	O
temporary	O
data	O
should	O
fit	O
there	O
for	O
full	O
speed	O
.	O
</s>
<s>
Data	O
can	O
also	O
be	O
used	O
from	O
other	O
processor	O
cores	O
local	B-General_Concept
memory	I-General_Concept
at	O
a	O
speed	O
penalty	O
,	O
or	O
off-chip	O
RAM	B-Architecture
with	O
much	O
larger	O
speed	O
penalty	O
.	O
</s>
<s>
The	O
memory	O
architecture	O
does	O
not	O
employ	O
explicit	O
hierarchy	O
of	O
hardware	B-General_Concept
caches	I-General_Concept
,	O
similar	O
to	O
the	O
Sony/Toshiba/IBM	O
Cell	O
processor	O
,	O
but	O
with	O
the	O
additional	O
benefit	O
of	O
off-chip	O
and	O
inter-core	O
loads	O
and	O
stores	O
being	O
supported	O
(	O
which	O
simplifies	O
porting	O
software	O
to	O
the	O
architecture	O
)	O
.	O
</s>
<s>
It	O
is	O
a	O
hardware	O
implementation	O
of	O
partitioned	B-Application
global	I-Application
address	I-Application
space	I-Application
.	O
</s>
<s>
This	O
eliminated	O
the	O
need	O
for	O
complex	O
cache	B-General_Concept
coherency	I-General_Concept
hardware	O
,	O
which	O
places	O
a	O
practical	O
limit	O
on	O
the	O
number	O
of	O
cores	O
in	O
a	O
traditional	O
multicore	B-Operating_System
system	I-Operating_System
.	O
</s>
<s>
All	O
processor	O
nodes	O
are	O
connected	O
through	O
a	O
network	B-Architecture
on	I-Architecture
chip	I-Architecture
,	O
allowing	O
efficient	O
message	O
passing	O
.	O
</s>
<s>
On	O
August	O
19	O
,	O
2012	O
,	O
Adapteva	B-Application
posted	O
some	O
specifications	O
and	O
information	O
about	O
Epiphany	O
multi-core	B-Architecture
coprocessors	O
.	O
</s>
<s>
Technical	O
info	O
for	O
E16G301Epiphany-III	O
16-core	O
65nm	O
Microprocessor	B-Architecture
(	O
E16G301	O
)	O
//	O
admin	O
(	O
August	O
19	O
,	O
2012	O
)	O
E64G401Epiphany-IV	O
64-core	O
28nm	O
Microprocessor	B-Architecture
(	O
E64G401	O
)	O
//	O
admin	O
(	O
August	O
19	O
,	O
2012	O
)	O
Cores	O
16	O
64	O
Core	O
MHz	O
1000	O
800	O
Core	O
GFLOPS	O
2	O
1.6	O
"	O
Sum	O
GHz	O
"	O
16	O
51.2	O
Sum	O
GFLOPS	O
32	O
102	O
mm²	O
8.96	O
8.2	O
nm	O
65	O
28	O
W	O
def	O
.	O
</s>
<s>
The	O
primary	O
markets	O
for	O
the	O
Epiphany	O
multi-core	B-Architecture
architecture	O
include	O
:	O
</s>
<s>
Smartphone	B-Application
applications	O
such	O
as	O
real-time	B-General_Concept
facial	O
recognition	O
,	O
speech	B-Application
recognition	I-Application
,	O
translation	O
,	O
and	O
augmented	B-General_Concept
reality	I-General_Concept
.	O
</s>
<s>
Next	O
generation	O
supercomputers	B-Architecture
requiring	O
drastically	O
better	O
energy	O
efficiency	O
to	O
allow	O
systems	O
to	O
scale	O
to	O
exaflop	O
computing	O
levels	O
.	O
</s>
<s>
Floating-point	B-Algorithm
acceleration	O
in	O
embedded	B-Architecture
systems	I-Architecture
based	O
on	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
architectures	O
.	O
</s>
<s>
In	O
September	O
2012	O
,	O
Adapteva	B-Application
started	O
project	O
Parallella	O
on	O
Kickstarter	O
,	O
which	O
was	O
marketed	O
as	O
"	O
A	O
Supercomputer	B-Architecture
for	O
everyone.	O
"	O
</s>
<s>
By	O
2016	O
,	O
the	O
firm	O
had	O
taped	O
out	O
a	O
1024-core	O
64-bit	B-Device
variant	O
of	O
their	O
Epiphany	O
architecture	O
that	O
featured	O
:	O
larger	O
local	O
stores	O
(	O
64KB	O
)	O
,	O
64-bit	B-Device
addressing	O
,	O
double-precision	O
floating-point	B-Algorithm
arithmetic	I-Algorithm
or	O
SIMD	B-Device
single-precision	O
,	O
and	O
64-bit	B-Device
integer	O
instructions	O
,	O
implemented	O
in	O
the	O
16	O
nm	O
process	O
node	O
.	O
</s>
<s>
This	O
design	O
included	O
instruction	B-General_Concept
set	I-General_Concept
enhancements	O
aimed	O
at	O
deep-learning	B-Algorithm
and	O
cryptography	O
applications	O
.	O
</s>
<s>
In	O
July	O
2017	O
,	O
Adapteva	B-Application
's	O
founder	O
became	O
a	O
DARPA	O
program	O
manager	O
and	O
announced	O
that	O
the	O
Epiphany	O
V	O
was	O
"	O
unlikely	O
"	O
to	O
become	O
available	O
as	O
a	O
commercial	O
product	O
.	O
</s>
<s>
The	O
latest	O
Parallella	O
boards	O
with	O
E16	O
Epiphany	O
chips	O
can	O
be	O
compared	O
to	O
many	O
historic	O
supercomputers	B-Architecture
in	O
terms	O
of	O
raw	O
performance	O
(	O
just	O
as	O
an	O
example	O
,	O
the	O
Cray	O
1the	O
first	O
supercomputer	B-Architecture
per	O
sehad	O
a	O
peak	O
performance	O
of	O
80MFLOPS	O
at	O
1976	O
,	O
and	O
its	O
successor	O
the	O
Cray	O
2	O
had	O
a	O
peak	O
performance	O
of	O
1.9GFLOPS	O
at	O
1985	O
)	O
,	O
and	O
can	O
certainly	O
be	O
used	O
for	O
parallel	O
code	O
development	O
.	O
</s>
<s>
The	O
architectural	O
similarities	O
to	O
supercomputers	B-Architecture
(	O
message	O
passing	O
and	O
NUMA	B-Operating_System
)	O
make	O
the	O
Parallella	O
a	O
potentially	O
useful	O
development	O
system	O
,	O
compared	O
to	O
traditional	O
SMP	O
machines	O
.	O
</s>
<s>
The	O
point	O
being	O
that	O
for	O
a	O
power	O
envelope	O
of	O
5W	O
and	O
in	O
terms	O
of	O
GFLOPS/mm2	O
of	O
chip	O
die	O
space	O
,	O
the	O
current	O
E16	O
Epiphany	O
chips	O
provide	O
vastly	O
more	O
performance	O
than	O
anything	O
else	O
available	O
to	O
date	O
,	O
with	O
an	O
architecture	O
designed	O
to	O
scale	O
,	O
and	O
applicable	O
to	O
more	O
than	O
just	O
embarrassingly	B-Operating_System
parallel	I-Operating_System
GPU	O
tasks	O
.	O
</s>
<s>
it	O
would	O
be	O
capable	O
of	O
running	O
the	O
actor	B-Application
model	I-Application
with	O
many	O
concurrent	O
,	O
fully	O
independent	O
states	O
)	O
.	O
</s>
<s>
It	O
is	O
also	O
suitable	O
for	O
DSP-like	O
tasks	O
where	O
data	O
could	O
be	O
fed	O
directly	O
on	O
chip	O
(	O
from	O
an	O
FPGA	B-Architecture
or	O
other	O
ASIC	O
)	O
without	O
having	O
to	O
create	O
buffers	O
in	O
temporary	O
memory	O
as	O
for	O
a	O
GPU	O
)	O
,	O
making	O
it	O
ideal	O
for	O
robotics	O
&	O
other	O
intelligent	O
sensor	O
applications	O
.	O
</s>
