<s>
Yonah	B-Device
is	O
the	O
code	O
name	O
of	O
Intel	O
's	O
first	O
generation	O
65	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
CPU	B-Architecture
cores	I-Architecture
,	O
based	O
on	O
cores	O
of	O
the	O
earlier	O
Banias	O
(	O
130	O
nm	O
)	O
/	O
Dothan	B-Architecture
(	O
90	O
nm	O
)	O
Pentium	B-Architecture
M	I-Architecture
microarchitecture	O
.	O
</s>
<s>
Yonah	B-Device
CPU	B-Architecture
cores	I-Architecture
were	O
used	O
within	O
Intel	O
's	O
Core	O
Solo	O
and	O
Core	B-Device
Duo	I-Device
mobile	O
microprocessor	O
products	O
.	O
</s>
<s>
SIMD	B-Device
performance	O
on	O
Yonah	B-Device
improved	O
through	O
the	O
addition	O
of	O
SSE3	B-General_Concept
instructions	O
and	O
improvements	O
to	O
SSE	B-General_Concept
and	O
SSE2	B-General_Concept
implementations	O
;	O
integer	O
performance	O
decreased	O
slightly	O
due	O
to	O
higher	O
latency	O
cache	O
.	O
</s>
<s>
Additionally	O
,	O
Yonah	B-Device
included	O
support	O
for	O
the	O
NX	B-General_Concept
bit	I-General_Concept
.	O
</s>
<s>
The	O
Intel	B-Device
Core	I-Device
Duo	O
brand	O
referred	O
to	O
a	O
low-power	O
(	O
less	O
than	O
25watts	O
)	O
dual-core	B-Architecture
microprocessor	O
,	O
which	O
offered	O
lower	O
power	O
operation	O
than	O
the	O
competing	O
AMD	B-General_Concept
Opteron	I-General_Concept
260	O
and	O
860	O
HE	O
at	O
55watts	O
.	O
</s>
<s>
Core	B-Device
Duo	I-Device
was	O
released	O
on	O
January	O
5	O
,	O
2006	O
,	O
with	O
the	O
other	O
components	O
of	O
the	O
Napa	O
platform	O
.	O
</s>
<s>
It	O
was	O
the	O
first	B-Device
Intel	I-Device
processor	I-Device
to	O
be	O
used	O
in	O
Apple	B-Device
Macintosh	I-Device
products	O
(	O
although	O
the	O
Apple	O
Developer	O
Transition	O
Kit	O
machines	O
,	O
non-production	O
units	O
distributed	O
to	O
some	O
developers	O
,	O
used	O
Pentium	B-General_Concept
4	I-General_Concept
processors	O
)	O
.	O
</s>
<s>
There	O
were	O
two	O
variants	O
and	O
one	O
derivative	O
of	O
the	O
Yonah	B-Device
,	O
which	O
did	O
not	O
bear	O
the	O
"	O
Intel	B-Device
Core	I-Device
"	O
brand	O
name	O
:	O
</s>
<s>
A	O
dual-core	B-Architecture
(	O
server	O
)	O
derivative	O
,	O
code-named	O
Sossaman	O
,	O
was	O
released	O
on	O
March	O
14	O
,	O
2006	O
,	O
as	O
the	O
Xeon	B-Device
(	O
branded	O
)	O
LV	O
(	O
low-voltage	O
)	O
.	O
</s>
<s>
The	O
Sossaman	O
differed	O
from	O
the	O
Yonah	B-Device
only	O
in	O
its	O
support	O
for	O
dual-socket	O
configurations	O
(	O
two	O
CPUs	O
providing	O
a	O
total	O
of	O
four	O
cores	O
per	O
motherboard	O
,	O
like	O
AMD	O
Quad	O
FX	O
)	O
,	O
and	O
implementation	O
of	O
36-bit	O
memory	O
addressing	O
(	O
PAE	B-General_Concept
mode	O
)	O
.	O
</s>
<s>
A	O
single-core	O
variant	O
,	O
code-named	O
Yonah-1024	O
,	O
was	O
released	O
as	O
the	O
Celeron	B-Device
(	O
branded	O
)	O
M	O
400	O
series	O
CPUs	O
.	O
</s>
<s>
It	O
was	O
largely	O
identical	O
to	O
the	O
Core	O
Solo	O
branded	O
Yonah	B-Device
,	O
except	O
that	O
it	O
only	O
had	O
half	O
the	O
L2	O
cache	O
and	O
did	O
not	O
support	O
SpeedStep	B-Device
and	O
Intel	O
VT-x	O
.	O
</s>
<s>
Another	O
dual-core	B-Architecture
variant	O
of	O
Yonah	B-Device
was	O
branded	O
as	O
Pentium	B-Device
Dual-Core	I-Device
T2060	B-Device
,	O
T2080	B-Device
,	O
and	O
T2130	O
mobile	O
CPUs	O
with	O
Intel	O
VT-x	O
support	O
.	O
</s>
<s>
Core	B-Device
Duo	I-Device
contains	O
151	O
million	O
transistors	B-Application
,	O
including	O
the	O
shared	O
2MB	O
L2	O
cache	O
.	O
</s>
<s>
Yonah	B-Device
's	O
execution	O
core	O
contains	O
a	O
12-stage	O
pipeline	B-General_Concept
,	O
forecast	O
to	O
eventually	O
be	O
able	O
to	O
run	O
at	O
a	O
maximum	O
frequency	O
of	O
2.332.50GHz	O
.	O
</s>
<s>
The	O
communication	O
between	O
the	O
L2	O
cache	O
and	O
both	O
execution	O
cores	O
is	O
handled	O
by	O
a	O
bus	O
unit	O
controller	O
through	O
arbitration	O
,	O
which	O
reduces	O
cache	O
coherency	O
traffic	O
over	O
the	O
FSB	B-Architecture
,	O
at	O
the	O
expense	O
of	O
raising	O
the	O
core-to-L2	O
latency	O
from	O
10	O
clock	O
cycles	O
(	O
in	O
the	O
Dothan	B-Architecture
Pentium	B-Architecture
M	I-Architecture
)	O
to	O
14	O
clock	O
cycles	O
.	O
</s>
<s>
Core	O
processors	O
communicate	O
with	O
the	O
system	O
chipset	O
over	O
a	O
667MT/s	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
(	O
FSB	B-Architecture
)	O
,	O
up	O
from	O
533MT/s	O
used	O
by	O
the	O
fastest	O
Pentium	B-Architecture
M	I-Architecture
.	O
</s>
<s>
T2050	O
&	O
T2250	O
have	O
also	O
appeared	O
in	O
OEM	O
systems	O
as	O
a	O
low-cost	O
option	O
with	O
a	O
lower	O
533MT/s	O
FSB	B-Architecture
and	O
no	O
Intel	O
VT-x	O
.	O
</s>
<s>
Yonah	B-Device
is	O
supported	O
by	O
the	O
945GM	O
,	O
945PM	O
,	O
945GT	O
,	O
965GM	O
,	O
965PM	O
,	O
and	O
965GT	O
system	O
chipsets	O
.	O
</s>
<s>
Core	B-Device
Duo	I-Device
and	O
Core	O
Solo	O
use	O
Socket	B-Device
M	I-Device
,	O
but	O
due	O
to	O
pin	O
arrangement	O
and	O
new	O
chipset	O
functions	O
are	O
not	O
compatible	O
with	O
any	O
previous	O
Pentium	B-Architecture
M	I-Architecture
motherboard	O
.	O
</s>
<s>
Contrary	O
to	O
early	O
reports	O
,	O
the	O
Intel	B-Device
Core	I-Device
Duo	O
supports	O
Intel	O
VT-x	O
x86	B-General_Concept
virtualization	I-General_Concept
,	O
except	O
in	O
the	O
T2300E	O
model	O
and	O
proprietary	O
T2050/T2150/T2250	O
mounted	O
by	O
OEMs	O
(	O
cf	O
.	O
</s>
<s>
The	O
Intel	B-Device
Pentium	I-Device
Dual	I-Device
Core	I-Device
processors	O
do	O
not	O
have	O
this	O
feature	O
.	O
</s>
<s>
Early	O
Intel	O
specifications	O
mistakenly	O
claimed	O
a	O
halving	O
of	O
the	O
Thermal	B-General_Concept
Design	I-General_Concept
Power	I-General_Concept
.	O
</s>
<s>
Intel	O
64	O
(	O
Intel	O
's	O
x86-64	B-Device
implementation	O
)	O
is	O
not	O
supported	O
by	O
Yonah	B-Device
.	O
</s>
<s>
However	O
,	O
Intel	O
64	O
support	O
is	O
integrated	O
in	O
Yonah	B-Device
's	O
successor	O
,	O
the	O
mobile	O
version	O
of	O
Core	B-Device
2	I-Device
,	O
code-named	O
Merom	B-Device
.	O
</s>
<s>
The	O
Duo	O
version	O
of	O
Intel	B-Device
Core	I-Device
(	O
Yonah	B-Device
)	O
includes	O
two	O
computational	O
cores	O
,	O
providing	O
performance	O
per	O
watt	O
almost	O
as	O
good	O
as	O
any	O
previous	O
single	O
core	O
Intel	O
processors	O
.	O
</s>
<s>
When	O
parallel	O
computations	O
and	O
multiprocessing	O
are	O
able	O
to	O
utilize	O
both	O
cores	O
,	O
the	O
Intel	B-Device
Core	I-Device
Duo	O
delivers	O
much	O
higher	O
peak	O
speed	O
compared	O
to	O
the	O
single-core	O
chips	O
previously	O
available	O
for	O
mobile	O
devices	O
.	O
</s>
<s>
However	O
,	O
Core	O
(	O
Yonah	B-Device
)	O
did	O
not	O
make	O
any	O
further	O
improvements	O
to	O
single	O
threaded	O
processing	O
performance	O
over	O
Dothan	B-Architecture
beyond	O
before-mentioned	O
SSE	B-General_Concept
unit	O
enhancements	O
,	O
and	O
it	O
was	O
still	O
only	O
a	O
32-bit	O
architecture	O
,	O
which	O
proved	O
to	O
be	O
particularly	O
limiting	O
for	O
its	O
server-oriented	O
Sossaman	O
derivative	O
as	O
x86-64	B-Device
operating	O
systems	O
and	O
software	O
became	O
increasingly	O
prevalent	O
.	O
</s>
<s>
According	O
to	O
Mobile	O
Roadmaps	O
from	O
2005	O
,	O
Intel	O
's	O
Yonah	B-Device
project	O
originally	O
focused	O
more	O
on	O
reducing	O
the	O
power	O
consumption	O
of	O
its	O
P6-based	O
Pentium	B-Architecture
M	I-Architecture
processor	O
and	O
aimed	O
to	O
reduce	O
it	O
by	O
50%	O
for	O
Intel	B-Device
Core	I-Device
(	O
Yonah	B-Device
)	O
.	O
</s>
<s>
Despite	O
being	O
less	O
power	O
efficient	O
,	O
Intel	O
continued	O
to	O
market	O
the	O
NetBurst-based	O
Mobile	B-Architecture
Pentium	I-Architecture
4	O
processors	O
for	O
high	O
performance	O
applications	O
until	O
the	O
Yonah	B-Device
project	O
succeeded	O
in	O
extracting	O
higher	O
performance	O
from	O
its	O
lower-power	O
design	O
.	O
</s>
<s>
The	O
Intel	B-Device
Core	I-Device
Duo	O
's	O
inclusion	O
of	O
two	O
highly	O
efficient	O
cores	O
on	O
one	O
chip	O
can	O
provide	O
better	O
performance	O
than	O
a	O
Mobile	B-Architecture
Pentium	I-Architecture
4	O
core	O
,	O
and	O
with	O
much	O
better	O
power-efficiency	O
.	O
</s>
<s>
On	O
July	O
27	O
,	O
2006	O
,	O
Intel	O
's	O
Core	B-Device
2	I-Device
processors	O
were	O
released	O
,	O
which	O
offered	O
x86-64	B-Device
compatibility	O
and	O
eventually	O
displaced	O
Yonah	B-Device
in	O
production	O
.	O
</s>
