<s>
Vivado	B-Algorithm
Design	O
Suite	O
is	O
a	O
software	O
suite	O
produced	O
by	O
Xilinx	O
for	O
synthesis	O
and	O
analysis	O
of	O
hardware	O
description	O
language	O
(	O
HDL	O
)	O
designs	O
,	O
superseding	O
Xilinx	B-Algorithm
ISE	I-Algorithm
with	O
additional	O
features	O
for	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
development	O
and	O
high-level	B-General_Concept
synthesis	I-General_Concept
.	O
</s>
<s>
Vivado	B-Algorithm
represents	O
a	O
ground-up	O
rewrite	O
and	O
re-thinking	O
of	O
the	O
entire	O
design	O
flow	O
(	O
compared	O
to	O
ISE	B-Algorithm
)	O
.	O
</s>
<s>
Like	O
the	O
later	O
versions	O
of	O
ISE	B-Algorithm
,	O
Vivado	B-Algorithm
includes	O
the	O
in-built	O
logic	O
simulator	O
.	O
</s>
<s>
Vivado	B-Algorithm
also	O
introduces	O
high-level	B-General_Concept
synthesis	I-General_Concept
,	O
with	O
a	O
toolchain	O
that	O
converts	O
C	B-Language
code	O
into	O
programmable	O
logic	O
.	O
</s>
<s>
Replacing	O
the	O
15	O
year	O
old	O
ISE	B-Algorithm
with	O
Vivado	B-Algorithm
Design	O
Suite	O
took	O
1000	O
man-years	O
and	O
cost	O
US$200	O
million	O
.	O
</s>
<s>
Vivado	B-Algorithm
was	O
introduced	O
in	O
April	O
2012	O
,	O
and	O
is	O
an	O
integrated	O
design	O
environment	O
(	O
IDE	O
)	O
with	O
system-to-IC	O
level	O
tools	O
built	O
on	O
a	O
shared	O
scalable	O
data	O
model	O
and	O
a	O
common	O
debug	O
environment	O
.	O
</s>
<s>
Vivado	B-Algorithm
includes	O
electronic	O
system	O
level	O
(	O
ESL	O
)	O
design	O
tools	O
for	O
synthesizing	O
and	O
verifying	O
C-based	O
algorithmic	O
IP	O
;	O
standards	O
based	O
packaging	O
of	O
both	O
algorithmic	O
and	O
RTL	O
IP	O
for	O
reuse	O
;	O
standards	O
based	O
IP	O
stitching	O
and	O
systems	O
integration	O
of	O
all	O
types	O
of	O
system	O
building	O
blocks	O
;	O
and	O
the	O
verification	O
of	O
blocks	O
and	O
systems	O
.	O
</s>
<s>
A	O
free	O
version	O
WebPACK	O
Edition	O
of	O
Vivado	B-Algorithm
provides	O
designers	O
with	O
a	O
limited	O
version	O
of	O
the	O
design	O
environment	O
.	O
</s>
<s>
The	O
Vivado	B-Algorithm
High-Level	B-General_Concept
Synthesis	I-General_Concept
compiler	O
enables	O
C	B-Language
,	O
C++	B-Language
and	O
SystemC	B-Language
programs	O
to	O
be	O
directly	O
targeted	O
into	O
Xilinx	O
devices	O
without	O
the	O
need	O
to	O
manually	O
create	O
RTL	O
.	O
</s>
<s>
Vivado	B-Algorithm
HLS	O
is	O
widely	O
reviewed	O
to	O
increase	O
developer	O
productivity	O
,	O
and	O
is	O
confirmed	O
to	O
support	O
C++	B-Language
classes	O
,	O
templates	O
,	O
functions	O
and	O
operator	O
overloading	O
.	O
</s>
<s>
Vivado	B-Algorithm
2014.1	O
introduced	O
support	O
for	O
automatically	O
converting	O
OpenCL	B-Application
kernels	O
to	O
IP	O
for	O
Xilinx	O
devices	O
.	O
</s>
<s>
OpenCL	B-Application
kernels	O
are	O
programs	O
that	O
execute	O
across	O
various	O
CPU	O
,	O
GPU	O
and	O
FPGA	O
platforms	O
.	O
</s>
<s>
The	O
Vivado	B-Algorithm
Simulator	O
is	O
a	O
component	O
of	O
the	O
Vivado	B-Algorithm
Design	O
Suite	O
.	O
</s>
<s>
It	O
is	O
a	O
compiled-language	O
simulator	O
that	O
supports	O
mixed-language	O
,	O
Tcl	B-Operating_System
scripts	O
,	O
encrypted	O
IP	O
and	O
enhanced	O
verification	O
.	O
</s>
<s>
The	O
Vivado	B-Algorithm
IP	O
Integrator	O
allows	O
engineers	O
to	O
quickly	O
integrate	O
and	O
configure	O
IP	O
from	O
the	O
large	O
Xilinx	O
IP	O
library	O
.	O
</s>
<s>
The	O
Integrator	O
is	O
also	O
tuned	O
for	O
MathWorks	O
Simulink	B-Application
designs	O
built	O
with	O
Xilinx	O
's	O
System	O
Generator	O
and	O
Vivado	B-Algorithm
High-Level	B-General_Concept
Synthesis	I-General_Concept
.	O
</s>
<s>
The	O
Vivado	B-Algorithm
Tcl	B-Operating_System
Store	O
is	O
a	O
scripting	O
system	O
for	O
developing	O
add-ons	O
to	O
Vivado	B-Algorithm
,	O
and	O
can	O
be	O
used	O
to	O
add	O
and	O
modify	O
Vivado	B-Algorithm
's	O
capabilities	O
.	O
</s>
<s>
Tcl	B-Operating_System
is	O
the	O
scripting	O
language	O
on	O
which	O
Vivado	B-Algorithm
itself	O
is	O
based	O
.	O
</s>
<s>
All	O
of	O
Vivado	B-Algorithm
's	O
underlying	O
functions	O
can	O
be	O
invoked	O
and	O
controlled	O
via	O
Tcl	B-Operating_System
scripts	O
.	O
</s>
<s>
Vivado	B-Algorithm
supports	O
Xilinx	O
's	O
7-series	O
and	O
all	O
the	O
newer	O
devices	O
(	O
UltraScale	O
and	O
UltraScale+	O
series	O
)	O
.	O
</s>
<s>
For	O
development	O
targeting	O
older	O
Xilinx	O
's	O
devices	O
and	O
CPLDs	O
,	O
the	O
already	O
discontinued	O
Xilinx	B-Algorithm
ISE	I-Algorithm
has	O
to	O
be	O
used	O
.	O
</s>
