<s>
Xilinx	B-Algorithm
ISE	I-Algorithm
(	O
Integrated	O
Synthesis	O
Environment	O
)	O
is	O
a	O
discontinued	O
software	O
tool	O
from	O
Xilinx	O
for	O
synthesis	O
and	O
analysis	O
of	O
HDL	O
designs	O
,	O
which	O
primarily	O
targets	O
development	O
of	O
embedded	B-Architecture
firmware	B-Application
for	O
Xilinx	O
FPGA	B-Architecture
and	O
CPLD	B-General_Concept
integrated	O
circuit	O
(	O
IC	O
)	O
product	O
families	O
.	O
</s>
<s>
It	O
was	O
succeeded	O
by	O
Xilinx	B-Algorithm
Vivado	I-Algorithm
.	O
</s>
<s>
Use	O
of	O
the	O
last	O
released	O
edition	O
from	O
October	O
2013	O
continues	O
for	O
in-system	B-Device
programming	I-Device
of	O
legacy	B-Device
hardware	I-Device
designs	O
containing	O
older	O
FPGAs	B-Architecture
and	O
CPLDs	B-General_Concept
otherwise	O
orphaned	O
by	O
the	O
replacement	O
design	O
tool	O
,	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
.	O
</s>
<s>
ISE	O
enables	O
the	O
developer	O
to	O
synthesize	O
(	O
"	O
compile	O
"	O
)	O
their	O
designs	O
,	O
perform	O
timing	B-Application
analysis	I-Application
,	O
examine	O
RTL	O
diagrams	O
,	O
simulate	O
a	O
design	O
's	O
reaction	O
to	O
different	O
stimuli	O
,	O
and	O
configure	O
the	O
target	O
device	O
with	O
the	O
programmer	B-General_Concept
.	O
</s>
<s>
Other	O
components	O
shipped	O
with	O
the	O
Xilinx	B-Algorithm
ISE	I-Algorithm
include	O
the	O
Embedded	B-Architecture
Development	O
Kit	O
(	O
EDK	O
)	O
,	O
a	O
Software	O
Development	O
Kit	O
(	O
SDK	O
)	O
and	O
ChipScope	O
Pro	O
.	O
</s>
<s>
The	O
Xilinx	B-Algorithm
ISE	I-Algorithm
is	O
primarily	O
used	O
for	O
circuit	O
synthesis	O
and	O
design	O
,	O
while	O
ISIM	O
or	O
the	O
ModelSim	B-Algorithm
logic	O
simulator	O
is	O
used	O
for	O
system-level	O
testing	O
.	O
</s>
<s>
As	O
commonly	O
practiced	O
in	O
the	O
commercial	O
electronic	O
design	O
automation	O
sector	O
,	O
Xilinx	B-Algorithm
ISE	I-Algorithm
is	O
tightly-coupled	O
to	O
the	O
architecture	O
of	O
Xilinx	O
's	O
own	O
chips	O
(	O
the	O
internals	O
of	O
which	O
are	O
highly	O
proprietary	O
)	O
and	O
cannot	O
be	O
used	O
with	O
FPGA	B-Architecture
products	O
from	O
other	O
vendors	O
.	O
</s>
<s>
Since	O
2012	O
,	O
Xilinx	B-Algorithm
ISE	I-Algorithm
has	O
been	O
discontinued	O
in	O
favor	O
of	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
that	O
serves	O
the	O
same	O
roles	O
as	O
ISE	O
with	O
additional	O
features	O
for	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
development	O
.	O
</s>
<s>
The	O
Design	O
hierarchy	O
consists	O
of	O
design	O
files	O
(	O
modules	O
)	O
,	O
whose	O
dependencies	O
are	O
interpreted	O
by	O
the	O
ISE	O
and	O
displayed	O
as	O
a	O
tree	B-Data_Structure
structure	I-Data_Structure
.	O
</s>
<s>
For	O
single-chip	O
designs	O
there	O
may	O
be	O
one	O
main	O
module	O
,	O
with	O
other	O
modules	O
included	O
by	O
the	O
main	O
module	O
,	O
similar	O
to	O
the	O
main( )	O
subroutine	O
in	O
C++	B-Language
programs	I-Language
.	O
</s>
<s>
System-level	O
testing	O
may	O
be	O
performed	O
with	O
ISIM	O
or	O
the	O
ModelSim	B-Algorithm
logic	O
simulator	O
,	O
and	O
such	O
test	O
programs	O
must	O
also	O
be	O
written	O
in	O
HDL	O
languages	O
.	O
</s>
<s>
ModelSim	B-Algorithm
or	O
ISIM	O
may	O
be	O
used	O
to	O
perform	O
the	O
following	O
types	O
of	O
simulations	O
:	O
</s>
<s>
Also	O
,	O
due	O
to	O
the	O
increasing	O
complexity	O
of	O
FPGA	B-Architecture
fabric	O
,	O
including	O
memory	O
blocks	O
and	O
I/O	O
blocks	O
,	O
more	O
complex	O
synthesis	O
algorithms	O
were	O
developed	O
that	O
separate	O
unrelated	O
modules	O
into	O
slices	O
,	O
reducing	O
post-placement	O
errors	O
.	O
</s>
<s>
IP	O
Cores	O
are	O
offered	O
by	O
Xilinx	O
and	O
other	O
third-party	O
vendors	O
,	O
to	O
implement	O
system-level	O
functions	O
such	O
as	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
(	O
DSP	O
)	O
,	O
bus	O
interfaces	O
,	O
networking	O
protocols	O
,	O
image	B-Algorithm
processing	I-Algorithm
,	O
embedded	B-Device
processors	I-Device
,	O
and	O
peripherals	O
.	O
</s>
<s>
Xilinx	O
has	O
been	O
instrumental	O
in	O
shifting	O
designs	O
from	O
ASIC-based	O
implementation	O
to	O
FPGA-based	O
implementation	O
.	O
</s>
<s>
The	O
Subscription	O
Edition	O
is	O
the	O
licensed	O
version	O
of	O
Xilinx	B-Algorithm
ISE	I-Algorithm
,	O
and	O
a	O
free	O
trial	B-License
version	I-License
is	O
available	O
for	O
download	O
.	O
</s>
<s>
The	O
Web	O
Edition	O
is	O
the	O
free	O
version	O
of	O
Xilinx	B-Algorithm
ISE	I-Algorithm
,	O
that	O
can	O
be	O
downloaded	O
and	O
used	O
for	O
no	O
charge	O
.	O
</s>
<s>
The	O
low-cost	O
Spartan	O
family	O
of	O
FPGAs	B-Architecture
is	O
fully	O
supported	O
by	O
this	O
edition	O
,	O
as	O
well	O
as	O
the	O
family	O
of	O
CPLDs	B-General_Concept
,	O
meaning	O
small	O
developers	O
and	O
educational	O
institutions	O
have	O
no	O
overheads	O
from	O
the	O
cost	O
of	O
development	O
software	O
.	O
</s>
<s>
License	O
registration	O
is	O
required	O
to	O
use	O
the	O
Web	O
Edition	O
of	O
Xilinx	B-Algorithm
ISE	I-Algorithm
,	O
which	O
is	O
free	O
and	O
can	O
be	O
renewed	O
an	O
unlimited	O
number	O
of	O
times	O
.	O
</s>
<s>
ISE	O
supports	O
up	O
to	O
Spartan	O
6	O
,	O
and	O
the	O
older	O
devices	O
including	O
CPLDs	B-General_Concept
(	O
XC9500	O
and	O
CoolRunner	O
)	O
.	O
</s>
<s>
For	O
development	O
targeting	O
newer	O
Xilinx	O
's	O
devices	O
(	O
7	O
series	O
,	O
UltraScale	O
and	O
UltraScale+	O
series	O
)	O
,	O
the	O
Xilinx	B-Algorithm
Vivado	I-Algorithm
has	O
to	O
be	O
used	O
.	O
</s>
<s>
Xilinx	O
officially	O
supports	O
Microsoft	B-Application
Windows	I-Application
Version	O
7	O
64	B-Device
bit	I-Device
,	O
Red	O
Hat	O
Enterprise	O
4	O
,	O
5	O
,	O
&	O
6	O
Workstations	O
(	O
32	O
&	O
64	B-Device
bits	I-Device
)	O
and	O
SUSE	O
Linux	B-Application
Enterprise	O
11	O
(	O
32	O
&	O
64	B-Device
bits	I-Device
)	O
.	O
</s>
<s>
Certain	O
other	O
Linux	B-Application
distributions	O
can	O
run	O
Xilinx	B-Algorithm
ISE	I-Algorithm
WebPack	O
with	O
some	O
modifications	O
or	O
configurations	O
,	O
including	O
Gentoo	B-Application
Linux	I-Application
,	O
Arch	O
Linux	B-Application
,	O
FreeBSD	B-Operating_System
and	O
Fedora	O
.	O
</s>
