<s>
Xetal	B-General_Concept
is	O
the	O
name	O
of	O
a	O
family	O
of	O
non	O
commercial	O
massively	B-Operating_System
parallel	I-Operating_System
processors	O
developed	O
within	O
Philips	O
Research	O
.	O
</s>
<s>
The	O
Xetal	B-General_Concept
was	O
conceived	O
in	O
1999	O
at	O
Philips	O
Research	O
when	O
researchers	O
Kleihorst	O
,	O
Abbo	O
and	O
Van	O
der	O
Avoird	O
investigated	O
possibilities	O
for	O
combining	O
a	O
CMOS	B-Architecture
image	I-Architecture
sensor	I-Architecture
with	O
powerful	O
image	B-Algorithm
processing	I-Algorithm
logic	O
.	O
</s>
<s>
Since	O
CMOS	B-Architecture
image	I-Architecture
sensors	I-Architecture
(	O
contrary	O
to	O
CCD	B-Algorithm
sensors	I-Algorithm
)	O
can	O
be	O
produced	O
using	O
the	O
same	O
manufacturing	O
process	O
as	O
processors	O
,	O
both	O
could	O
be	O
combined	O
in	O
a	O
single	O
integrated	O
circuit	O
(	O
IC	O
)	O
.	O
</s>
<s>
With	O
the	O
image	B-Algorithm
sensor	I-Algorithm
and	O
image	B-Algorithm
processing	I-Algorithm
combined	O
on	O
the	O
same	O
die	O
it	O
is	O
essentially	O
possible	O
to	O
parallelize	O
image	B-Algorithm
processing	I-Algorithm
up	O
to	O
the	O
level	O
where	O
each	O
pixel	B-Algorithm
has	O
its	O
dedicated	O
image	B-Algorithm
processing	I-Algorithm
logic	O
.	O
</s>
<s>
In	O
such	O
a	O
design	O
the	O
image	B-Algorithm
sensor	I-Algorithm
would	O
be	O
in	O
the	O
upper	O
layers	O
of	O
the	O
IC	O
while	O
the	O
image	B-Algorithm
processing	I-Algorithm
would	O
be	O
done	O
in	O
the	O
lower	O
layers	O
,	O
so	O
image	O
data	O
would	O
be	O
transferred	O
from	O
one	O
layer	O
to	O
the	O
other	O
,	O
instead	O
of	O
through	O
external	O
pins	O
or	O
wires	O
.	O
</s>
<s>
Additionally	O
there	O
is	O
inherent	O
parallelism	B-Operating_System
in	O
image	B-Algorithm
processing	I-Algorithm
algorithms	I-Algorithm
.	O
</s>
<s>
Many	O
algorithms	O
do	O
the	O
same	O
processing	O
on	O
every	O
pixel	B-Algorithm
.	O
</s>
<s>
Image	B-Algorithm
processing	I-Algorithm
is	O
therefore	O
a	O
suitable	O
domain	O
for	O
a	O
massively	B-Operating_System
parallel	I-Operating_System
approach	O
using	O
an	O
SIMD	B-Device
architecture	O
.	O
</s>
<s>
Although	O
massive	B-Operating_System
parallelism	I-Operating_System
is	O
not	O
a	O
new	O
idea	O
(	O
earlier	O
examples	O
include	O
ILLIAC	B-Device
IV	I-Device
and	O
Goodyear	B-Device
MPP	I-Device
)	O
the	O
Xetal	B-General_Concept
1	O
was	O
one	O
of	O
the	O
first	O
to	O
apply	O
this	O
approach	O
to	O
image	B-Algorithm
processing	I-Algorithm
.	O
</s>
<s>
The	O
first	O
design	O
combined	O
a	O
QVGA	O
image	B-Algorithm
sensor	I-Algorithm
with	O
line-based	O
A/D	O
conversion	O
.	O
</s>
<s>
In	O
this	O
design	O
,	O
the	O
analogue	O
pixel	B-Algorithm
values	O
of	O
the	O
sensor	O
were	O
converted	O
line	O
by	O
line	O
(	O
instead	O
of	O
pixel	B-Algorithm
by	O
pixel	B-Algorithm
)	O
.	O
</s>
<s>
Each	O
A/D	O
converter	O
is	O
connected	O
to	O
a	O
dedicated	O
processing	O
element	O
(	O
PE	O
)	O
to	O
do	O
image	B-Algorithm
processing	I-Algorithm
.	O
</s>
<s>
This	O
parallel	O
design	O
meant	O
that	O
a	O
complete	O
line	O
of	O
320	O
pixels	B-Algorithm
could	O
essentially	O
be	O
processed	O
in	O
a	O
single	O
clock	O
cycle	O
.	O
</s>
<s>
This	O
parallelism	B-Operating_System
was	O
also	O
applied	O
to	O
the	O
memory	O
architecture	O
,	O
where	O
each	O
processing	O
element	O
could	O
access	O
a	O
pixel	B-Algorithm
from	O
a	O
so-called	O
/Line	O
memory	O
.	O
</s>
<s>
On	O
top	O
of	O
that	O
CMOS	B-Architecture
sensors	I-Architecture
at	O
the	O
time	O
were	O
produced	O
using	O
a	O
350-nm	O
process	O
using	O
3	O
metal	O
layers	O
.	O
</s>
<s>
Development	O
of	O
the	O
CMOS	B-Architecture
sensor	I-Architecture
and	O
the	O
image	O
processor	O
therefore	O
continued	O
independently	O
.	O
</s>
<s>
The	O
image	O
processor	O
resulting	O
from	O
this	O
was	O
the	O
Xetal	B-General_Concept
1	O
,	O
first	O
produced	O
in	O
2001	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
combined	O
with	O
a	O
CMOS	B-Architecture
image	I-Architecture
sensor	I-Architecture
at	O
QVGA	O
resolution	O
running	O
at	O
15	O
frames	O
per	O
second	O
the	O
Xetal	B-General_Concept
1	O
could	O
essentially	O
perform	O
5000	O
operations	O
per	O
pixel	B-Algorithm
.	O
</s>
<s>
During	O
testing	O
it	O
turned	O
out	O
the	O
Xetal	B-General_Concept
1	O
could	O
even	O
be	O
clocked	O
up	O
to	O
38	O
MHz	O
,	O
more	O
than	O
double	O
the	O
original	O
specification	O
,	O
resulting	O
in	O
a	O
raw	O
performance	O
of	O
over	O
12	O
GOPS	O
.	O
</s>
<s>
It	O
was	O
soon	O
discovered	O
that	O
with	O
these	O
levels	O
of	O
performance	O
it	O
was	O
possible	O
to	O
do	O
much	O
more	O
than	O
just	O
image	B-Algorithm
processing	I-Algorithm
.	O
</s>
<s>
The	O
research	O
team	O
which	O
now	O
also	O
involved	O
Ben	O
Schueler	O
,	O
Joost	O
'	O
t	O
Hart	O
,	O
Peter	O
Meijer	O
,	O
Alexander	O
Danilin	O
,	O
Xinting	O
Chao	O
and	O
Herman	O
Budde	O
created	O
demonstrations	O
which	O
showed	O
that	O
Xetal	B-General_Concept
1	O
was	O
capable	O
of	O
running	O
computer	B-Application
vision	I-Application
algorithms	O
such	O
as	O
object	O
recognition	O
and	O
tracking	O
,	O
including	O
a	O
self-playing	O
pinball	B-Application
machine	I-Application
,	O
air	O
drumming	O
,	O
and	O
Robocup	O
robots	O
.	O
</s>
<s>
Usually	O
the	O
Xetal-I	O
chip	O
was	O
shown	O
as	O
a	O
wireless	O
smart	B-General_Concept
camera	I-General_Concept
name	O
WiCa	O
,	O
a	O
design	O
by	O
Ben	O
Schueler	O
.	O
</s>
<s>
Xetal-I	O
was	O
later	O
succeeded	O
by	O
the	O
Xetal-II	O
chip	O
.	O
</s>
