<s>
Xeon	B-General_Concept
Phi	I-General_Concept
was	O
a	O
series	O
of	O
x86	B-Operating_System
manycore	B-General_Concept
processors	I-General_Concept
designed	O
and	O
made	O
by	O
Intel	O
.	O
</s>
<s>
It	O
was	O
intended	O
for	O
use	O
in	O
supercomputers	B-Architecture
,	O
servers	O
,	O
and	O
high-end	O
workstations	O
.	O
</s>
<s>
Its	O
architecture	O
allowed	O
use	O
of	O
standard	O
programming	O
languages	O
and	O
application	B-Application
programming	I-Application
interfaces	I-Application
(	O
APIs	B-Application
)	O
such	O
as	O
OpenMP	B-Application
.	O
</s>
<s>
Xeon	B-General_Concept
Phi	I-General_Concept
launched	O
in	O
2010	O
.	O
</s>
<s>
Since	O
it	O
was	O
originally	O
based	O
on	O
an	O
earlier	O
GPU	O
design	O
(	O
codenamed	B-Architecture
"	I-Architecture
Larrabee	I-Architecture
"	I-Architecture
)	O
by	O
Intel	O
that	O
was	O
cancelled	O
in	O
2009	O
,	O
it	O
shared	O
application	O
areas	O
with	O
GPUs	O
.	O
</s>
<s>
The	O
main	O
difference	O
between	O
Xeon	B-General_Concept
Phi	I-General_Concept
and	O
a	O
GPGPU	B-Architecture
like	O
Nvidia	B-Device
Tesla	I-Device
was	O
that	O
Xeon	B-General_Concept
Phi	I-General_Concept
,	O
with	O
an	O
x86-compatible	O
core	O
,	O
could	O
,	O
with	O
less	O
modification	O
,	O
run	O
software	O
that	O
was	O
originally	O
targeted	O
to	O
a	O
standard	O
x86	B-Operating_System
CPU	O
.	O
</s>
<s>
In	O
June	O
2013	O
,	O
the	O
Tianhe-2	B-Device
supercomputer	B-Architecture
at	O
the	O
National	B-Device
Supercomputer	I-Device
Center	I-Device
in	I-Device
Guangzhou	I-Device
(	O
NSCC-GZ	O
)	O
was	O
announced	O
as	O
the	O
world	O
's	O
fastest	B-Operating_System
supercomputer	I-Operating_System
(	O
,	O
it	O
is	O
)	O
.	O
</s>
<s>
It	O
used	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
coprocessors	I-General_Concept
and	O
Ivy	O
Bridge-EP	O
Xeon	B-Device
processors	O
to	O
achieve	O
33.86petaFLOPS	O
.	O
</s>
<s>
The	O
Xeon	B-General_Concept
Phi	I-General_Concept
product	O
line	O
directly	O
competed	O
with	O
Nvidia	O
's	O
Tesla	B-Device
and	O
AMD	B-Operating_System
Radeon	I-Operating_System
Instinct	I-Operating_System
lines	O
of	O
deep	B-Algorithm
learning	I-Algorithm
and	O
GPGPU	B-Architecture
cards	O
.	O
</s>
<s>
The	O
Larrabee	B-Architecture
microarchitecture	I-Architecture
(	O
in	O
development	O
since	O
2006	O
)	O
introduced	O
very	O
wide	O
(	O
512-bit	O
)	O
SIMD	B-Device
units	O
to	O
a	O
x86	B-Operating_System
architecture	I-Operating_System
based	O
processor	O
design	O
,	O
extended	O
to	O
a	O
cache-coherent	B-General_Concept
multiprocessor	O
system	O
connected	O
via	O
a	O
ring	O
bus	O
to	O
memory	O
;	O
each	O
core	O
was	O
capable	O
of	O
four-way	O
multithreading	B-General_Concept
.	O
</s>
<s>
Due	O
to	O
the	O
design	O
being	O
intended	O
for	O
GPU	O
as	O
well	O
as	O
general	O
purpose	O
computing	O
,	O
the	O
Larrabee	B-Architecture
chips	O
also	O
included	O
specialised	O
hardware	O
for	O
texture	O
sampling	O
.	O
</s>
<s>
The	O
project	O
to	O
produce	O
a	O
retail	O
GPU	O
product	O
directly	O
from	O
the	O
Larrabee	B-Architecture
research	O
project	O
was	O
terminated	O
in	O
May	O
2010	O
.	O
</s>
<s>
Another	O
contemporary	O
Intel	O
research	O
project	O
implementing	O
x86	B-Operating_System
architecture	I-Operating_System
on	O
a	O
many-multicore	O
processor	O
was	O
the	O
'	O
Single-chip	B-General_Concept
Cloud	I-General_Concept
Computer	I-General_Concept
 '	O
(	O
prototype	O
introduced	O
2009	O
)	O
,	O
a	O
design	O
mimicking	O
a	O
cloud	B-Architecture
computing	I-Architecture
computer	O
datacentre	O
on	O
a	O
single	O
chip	O
with	O
multiple	O
independent	O
cores	B-Architecture
:	O
the	O
prototype	O
design	O
included	O
48	O
cores	B-Architecture
per	O
chip	O
with	O
hardware	O
support	O
for	O
selective	O
frequency	O
and	O
voltage	O
control	O
of	O
cores	B-Architecture
to	O
maximize	O
energy	O
efficiency	O
,	O
and	O
incorporated	O
a	O
mesh	B-Architecture
network	I-Architecture
for	O
inter-chip	O
messaging	O
.	O
</s>
<s>
The	O
design	O
lacked	O
cache-coherent	B-General_Concept
cores	B-Architecture
and	O
focused	O
on	O
principles	O
that	O
would	O
allow	O
the	O
design	O
to	O
scale	O
to	O
many	O
more	O
cores	B-Architecture
.	O
</s>
<s>
The	O
Teraflops	B-General_Concept
Research	I-General_Concept
Chip	I-General_Concept
(	O
prototype	O
unveiled	O
2007	O
)	O
is	O
an	O
experimental	O
80-core	O
chip	O
with	O
two	O
floating-point	B-Algorithm
units	O
per	O
core	O
,	O
implementing	O
a	O
96-bit	O
VLIW	B-General_Concept
architecture	O
instead	O
of	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
.	O
</s>
<s>
Intel	O
's	O
Many	B-General_Concept
Integrated	I-General_Concept
Core	I-General_Concept
(	O
MIC	O
)	O
prototype	O
board	O
,	O
named	O
Knights	O
Ferry	O
,	O
incorporating	O
a	O
processor	O
codenamed	O
Aubrey	O
Isle	O
was	O
announced	O
31	O
May	O
2010	O
.	O
</s>
<s>
The	O
product	O
was	O
stated	O
to	O
be	O
a	O
derivative	O
of	O
the	O
Larrabee	B-Architecture
project	O
and	O
other	O
Intel	O
research	O
including	O
the	O
Single-chip	B-General_Concept
Cloud	I-General_Concept
Computer	I-General_Concept
.	O
</s>
<s>
The	O
development	O
product	O
was	O
offered	O
as	O
a	O
PCIe	O
card	O
with	O
32	O
in-order	O
cores	B-Architecture
at	O
up	O
to	O
1.2GHz	O
with	O
four	O
threads	B-General_Concept
per	O
core	O
,	O
2GB	O
GDDR5	O
memory	O
,	O
and	O
8MB	O
coherent	O
L2	O
cache	O
(	O
256KB	O
per	O
core	O
with	O
32KB	O
L1	O
cache	O
)	O
,	O
and	O
a	O
power	O
requirement	O
of	O
~	O
300W	O
,	O
built	O
at	O
a	O
45nm	O
process	O
.	O
</s>
<s>
The	O
prototype	O
boards	O
only	O
support	O
single-precision	O
floating-point	B-Algorithm
instructions	O
.	O
</s>
<s>
Initial	O
developers	O
included	O
CERN	O
,	O
Korea	O
Institute	O
of	O
Science	O
and	O
Technology	O
Information	O
(	O
KISTI	O
)	O
and	O
Leibniz	B-General_Concept
Supercomputing	I-General_Concept
Centre	I-General_Concept
.	O
</s>
<s>
The	O
Knights	O
Corner	O
product	O
line	O
is	O
made	O
at	O
a	O
22nm	B-Algorithm
process	O
size	O
,	O
using	O
Intel	O
's	O
Tri-gate	O
technology	O
with	O
more	O
than	O
50	O
cores	B-Architecture
per	O
chip	O
,	O
and	O
is	O
Intel	O
's	O
first	O
many-cores	B-General_Concept
commercial	O
product	O
.	O
</s>
<s>
In	O
June	O
2011	O
,	O
SGI	O
announced	O
a	O
partnership	O
with	O
Intel	O
to	O
use	O
the	O
MIC	O
architecture	O
in	O
its	O
high-performance	B-Architecture
computing	I-Architecture
products	O
.	O
</s>
<s>
In	O
September	O
2011	O
,	O
it	O
was	O
announced	O
that	O
the	O
Texas	O
Advanced	O
Computing	O
Center	O
(	O
TACC	O
)	O
will	O
use	O
Knights	O
Corner	O
cards	O
in	O
their	O
10-petaFLOPS	O
"	O
Stampede	O
"	O
supercomputer	B-Architecture
,	O
providing	O
8petaFLOPS	O
of	O
compute	O
power	O
.	O
</s>
<s>
On	O
18	O
June	O
2012	O
,	O
Intel	O
announced	O
at	O
the	O
2012	O
Hamburg	O
International	O
Supercomputing	B-Architecture
Conference	O
that	O
Xeon	B-General_Concept
Phi	I-General_Concept
will	O
be	O
the	O
brand	O
name	O
used	O
for	O
all	O
products	O
based	O
on	O
their	O
Many	B-General_Concept
Integrated	I-General_Concept
Core	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
In	O
June	O
2012	O
,	O
Cray	O
announced	O
it	O
would	O
be	O
offering	O
22nm	B-Algorithm
'	O
Knight	O
's	O
Corner	O
 '	O
chips	O
(	O
branded	O
as	O
'	O
Xeon	B-General_Concept
Phi	I-General_Concept
 '	O
)	O
as	O
a	O
co-processor	O
in	O
its	O
'	O
Cascade	O
 '	O
systems	O
.	O
</s>
<s>
In	O
June	O
2012	O
,	O
ScaleMP	O
announced	O
a	O
virtualization	O
update	O
allowing	O
Xeon	B-General_Concept
Phi	I-General_Concept
as	O
a	O
transparent	O
processor	O
extension	O
,	O
allowing	O
legacy	O
MMX/SSE	O
code	O
to	O
run	O
without	O
code	O
changes	O
.	O
</s>
<s>
An	O
important	O
component	O
of	O
the	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
coprocessor	I-General_Concept
's	O
core	O
is	O
its	O
vector	O
processing	O
unit	O
(	O
VPU	O
)	O
.	O
</s>
<s>
The	O
VPU	O
features	O
a	O
novel	O
512-bit	O
SIMD	B-Device
instruction	O
set	O
,	O
officially	O
known	O
as	O
Intel	O
Initial	O
Many	B-General_Concept
Core	I-General_Concept
Instructions	O
(	O
Intel	O
IMCI	O
)	O
.	O
</s>
<s>
The	O
VPU	O
also	O
supports	O
Fused	O
Multiply-Add	O
(	O
FMA	O
)	O
instructions	O
and	O
hence	O
can	O
execute	O
32	O
SP	O
or	O
16	O
DP	O
floating	B-Algorithm
point	I-Algorithm
operations	O
per	O
cycle	O
.	O
</s>
<s>
On	O
12	O
November	O
2012	O
,	O
Intel	O
announced	O
two	O
Xeon	B-General_Concept
Phi	I-General_Concept
coprocessor	O
families	O
using	O
the	O
22nm	B-Algorithm
process	O
size	O
:	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
3100	O
and	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
5110P	O
.	O
</s>
<s>
The	O
Xeon	B-General_Concept
Phi	I-General_Concept
3100	O
will	O
be	O
capable	O
of	O
more	O
than	O
1teraFLOPS	O
of	O
double-precision	O
floating-point	B-Algorithm
instructions	O
with	O
240GB/s	O
memory	O
bandwidth	O
at	O
300W	O
.	O
</s>
<s>
The	O
Xeon	B-General_Concept
Phi	I-General_Concept
5110P	O
will	O
be	O
capable	O
of	O
1.01teraFLOPS	O
of	O
double-precision	O
floating-point	B-Algorithm
instructions	O
with	O
320GB/s	O
memory	O
bandwidth	O
at	O
225W	O
.	O
</s>
<s>
The	O
Xeon	B-General_Concept
Phi	I-General_Concept
7120P	O
will	O
be	O
capable	O
of	O
1.2teraFLOPS	O
of	O
double-precision	O
floating-point	B-Algorithm
instructions	O
with	O
352GB/s	O
memory	O
bandwidth	O
at	O
300W	O
.	O
</s>
<s>
On	O
17	O
June	O
2013	O
,	O
the	O
Tianhe-2	B-Device
supercomputer	B-Architecture
was	O
announced	O
by	O
TOP500	B-Operating_System
as	O
the	O
world	O
's	O
fastest	O
.	O
</s>
<s>
Tianhe-2	B-Device
used	O
Intel	B-Device
Ivy	I-Device
Bridge	I-Device
Xeon	B-Device
and	O
Xeon	B-General_Concept
Phi	I-General_Concept
processors	O
to	O
achieve	O
33.86petaFLOPS	O
.	O
</s>
<s>
The	O
cores	B-Architecture
of	O
Knights	O
Corner	O
are	O
based	O
on	O
a	O
modified	O
version	O
of	O
P54C	O
design	O
,	O
used	O
in	O
the	O
original	O
Pentium	O
.	O
</s>
<s>
The	O
basis	O
of	O
the	O
Intel	B-General_Concept
MIC	I-General_Concept
architecture	O
is	O
to	O
leverage	O
x86	B-Operating_System
legacy	O
by	O
creating	O
an	O
x86-compatible	O
multiprocessor	O
architecture	O
that	O
can	O
use	O
existing	O
parallelization	O
software	O
tools	O
.	O
</s>
<s>
Programming	O
tools	O
include	O
OpenMP	B-Application
,	O
OpenCL	B-Application
,	O
Cilk/Cilk	O
Plus	O
and	O
specialised	O
versions	O
of	O
Intel	O
's	O
Fortran	O
,	O
C++	O
and	O
math	O
libraries	O
.	O
</s>
<s>
Design	O
elements	O
inherited	O
from	O
the	O
Larrabee	B-Architecture
project	O
include	O
x86	B-Operating_System
ISA	O
,	O
4-way	O
SMT	B-Operating_System
per	O
core	O
,	O
512-bit	O
SIMD	B-Device
units	O
,	O
32KB	O
L1	O
instruction	O
cache	O
,	O
32KB	O
L1	O
data	O
cache	O
,	O
coherent	O
L2	O
cache	O
(	O
512KB	O
per	O
core	O
)	O
,	O
and	O
ultra-wide	O
ring	O
bus	O
connecting	O
processors	O
and	O
memory	O
.	O
</s>
<s>
The	O
Knights	O
Corner	O
512-bit	O
SIMD	B-Device
instructions	O
share	O
many	O
intrinsic	O
functions	O
with	O
AVX-512	B-General_Concept
extension	O
.	O
</s>
<s>
+Models	O
of	O
Xeon	B-General_Concept
Phi	I-General_Concept
X100	O
Series	O
Name	O
Serial	O
Code	O
Cores( Threads	O
@	O
4×	O
core	O
)	O
Clock	O
(	O
MHz	O
)	O
L2cache	O
GDDR5	O
ECC	O
memory	O
Peak	O
DPcompute(GFLOPS )	O
TDP(W )	O
Coolingsystem	O
Form	O
factor	O
Released	O
Base	O
Turbo	O
Quantity	O
Channels	O
BWGB/s	O
Xeon	B-General_Concept
Phi	I-General_Concept
3110X	O
SE3110X	O
61	O
(	O
244	O
)	O
1053	O
-	O
30.5	O
MB6	O
GB	O
12240	O
1028	O
300	O
Bare	O
board	O
PCIe	O
2.0	O
x16	O
card	O
November	O
,	O
20128	O
GB16320	O
Xeon	B-General_Concept
Phi	I-General_Concept
3120ASC3120A	O
57	O
(	O
228	O
)	O
1100	O
-	O
28.5	O
MB	O
6	O
GB	O
12	O
240	O
1003	O
300	O
Fan/heatsink	O
17	O
June	O
2013Xeon	O
Phi	O
3120P	O
SC3120P	O
57	O
(	O
228	O
)	O
1100	O
-	O
28.5	O
MB	O
6	O
GB	O
12	O
240	O
1003	O
300	O
Passive	O
heatsink	O
17	O
June	O
2013Xeon	O
Phi	O
31S1PBC31S1P57	O
(	O
228	O
)	O
1100	O
-28.5	O
MB8	O
GB16320	O
1003270Passive	O
heatsink17	O
June	O
2013Xeon	O
Phi	O
5110PSC5110P60	O
(	O
240	O
)	O
1053	O
-30.0	O
MB8	O
GB16320	O
1011225Passive	O
heatsink12	O
Nov	O
2012	O
Xeon	B-General_Concept
Phi	I-General_Concept
5120D	O
SC5120D	O
60	O
(	O
240	O
)	O
1053	O
-	O
30.0	O
MB	O
8	O
GB	O
16	O
352	O
1011	O
245	O
Bare	O
board	O
SFF	O
230-pin	O
card	O
17	O
June	O
2013	O
BC5120DXeon	O
Phi	O
SE10PSE10P61	O
(	O
244	O
)	O
1100	O
-30.5	O
MB8	O
GB16352	O
1074300Passive	O
heatsink	O
PCIe	O
2.0	O
x16	O
card12	O
Nov	O
.	O
2012Xeon	O
Phi	O
SE10XSE10X61	O
(	O
244	O
)	O
1100	O
-30.5	O
MB8	O
GB16352	O
1074	O
300Bare	O
board12	O
Nov	O
.	O
2012Xeon	O
Phi	O
7110PSC7110P61	O
(	O
244	O
)	O
1100	O
125030.5	O
MB16	O
GB16352	O
1220	O
300Passive	O
heatsink	O
???	O
</s>
<s>
Xeon	B-General_Concept
Phi	I-General_Concept
7110XSC7110X61	O
(	O
244	O
)	O
1250	O
?	O
</s>
<s>
?	O
Xeon	B-General_Concept
Phi	I-General_Concept
7120ASC7120A61	O
(	O
244	O
)	O
1238	O
1333	O
30.5	O
MB	O
16	O
GB	O
16	O
352	O
1208	O
300	O
Fan/heatsink	O
6	O
April	O
2014Xeon	O
Phi	O
7120DSC7120D61	O
(	O
244	O
)	O
1238	O
1333	O
30.5	O
MB	O
16	O
GB	O
16	O
352	O
1208	O
270	O
Bare	O
board	O
SFF	O
230-pin	O
card	O
March	O
?	O
</s>
<s>
Intel	O
officially	O
first	O
revealed	O
details	O
of	O
its	O
second-generation	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
products	O
on	O
17	O
June	O
2013	O
.	O
</s>
<s>
Intel	O
said	O
that	O
the	O
next	O
generation	O
of	O
Intel	B-General_Concept
MIC	I-General_Concept
Architecture-based	O
products	O
will	O
be	O
available	O
in	O
two	O
forms	O
,	O
as	O
a	O
coprocessor	O
or	O
a	O
host	O
processor	O
(	O
CPU	O
)	O
,	O
and	O
be	O
manufactured	O
using	O
Intel	O
's	O
14	O
nm	O
process	O
technology	O
.	O
</s>
<s>
Knights	O
Landing	O
contains	O
up	O
to	O
72	O
Airmont	B-Device
(	O
Atom	O
)	O
cores	B-Architecture
with	O
four	O
threads	B-General_Concept
per	O
core	O
,	O
using	O
LGA	B-Device
3647	I-Device
socket	O
supporting	O
up	O
to	O
384GB	O
of	O
"	O
far	O
"	O
DDR4	O
2133	O
RAM	O
and	O
816GB	O
of	O
stacked	O
"	O
near	O
"	O
3DMCDRAM	O
,	O
a	O
version	O
of	O
the	B-General_Concept
Hybrid	I-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
.	O
</s>
<s>
Each	O
core	O
has	O
two	O
512-bit	O
vector	O
units	O
and	O
supports	O
AVX-512	B-General_Concept
SIMD	B-Device
instructions	O
,	O
specifically	O
the	O
Intel	O
AVX-512	B-General_Concept
Foundational	O
Instructions	O
(	O
AVX-512F	O
)	O
with	O
Intel	O
AVX-512	B-General_Concept
Conflict	O
Detection	O
Instructions	O
(	O
AVX-512CD	O
)	O
,	O
Intel	O
AVX-512	B-General_Concept
Exponential	O
and	O
Reciprocal	O
Instructions	O
(	O
AVX-512ER	O
)	O
,	O
and	O
Intel	O
AVX-512	B-General_Concept
Prefetch	O
Instructions	O
(	O
AVX-512PF	O
)	O
.	O
</s>
<s>
Support	O
for	O
IMCI	O
has	O
been	O
removed	O
in	O
favor	O
of	O
AVX-512	B-General_Concept
.	O
</s>
<s>
The	O
National	O
Energy	O
Research	O
Scientific	O
Computing	O
Center	O
announced	O
that	O
Phase	O
2	O
of	O
its	O
newest	O
supercomputing	B-Architecture
system	O
"	O
Cori	O
"	O
would	O
use	O
Knights	O
Landing	O
Xeon	B-General_Concept
Phi	I-General_Concept
coprocessors	O
.	O
</s>
<s>
On	O
20	O
June	O
2016	O
,	O
Intel	O
launched	O
the	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
product	O
family	O
x200	O
based	O
on	O
the	O
Knights	O
Landing	O
architecture	O
,	O
stressing	O
its	O
applicability	O
to	O
not	O
just	O
traditional	O
simulation	O
workloads	O
,	O
but	O
also	O
to	O
machine	O
learning	O
.	O
</s>
<s>
The	O
model	O
lineup	O
announced	O
at	O
launch	O
included	O
only	O
Xeon	B-General_Concept
Phi	I-General_Concept
of	O
bootable	O
form-factor	O
,	O
but	O
two	O
versions	O
of	O
it	O
:	O
standard	O
processors	O
and	O
processors	O
with	O
integrated	O
Intel	O
Omni-Path	B-Operating_System
architecture	I-Operating_System
fabric	O
.	O
</s>
<s>
On	O
14	O
November	O
2016	O
,	O
the	O
48th	O
list	O
of	O
TOP500	B-Operating_System
contained	O
10	O
systems	O
using	O
Knights	O
Landing	O
platforms	O
.	O
</s>
<s>
All	O
models	O
can	O
boost	O
to	O
their	O
peak	O
speeds	O
,	O
adding	O
200MHz	O
to	O
their	O
base	O
frequency	O
when	O
running	O
just	O
one	O
or	O
two	O
cores	B-Architecture
.	O
</s>
<s>
When	O
running	O
from	O
three	O
to	O
the	O
maximum	O
number	O
of	O
cores	B-Architecture
,	O
the	O
chips	O
can	O
only	O
boost	O
100MHz	O
above	O
the	O
base	O
frequency	O
.	O
</s>
<s>
All	O
chips	O
run	O
high-AVX	O
code	O
at	O
a	O
frequency	O
reduced	O
by	O
200MHz	O
.	O
</s>
<s>
Knights	O
Hill	O
was	O
expected	O
to	O
be	O
used	O
in	O
the	O
United	O
States	O
Department	O
of	O
Energy	O
Aurora	B-Device
supercomputer	I-Device
,	O
to	O
be	O
deployed	O
at	O
Argonne	O
National	O
Laboratory	O
.	O
</s>
<s>
However	O
,	O
Aurora	B-Device
was	O
delayed	O
in	O
favor	O
of	O
using	O
an	O
"	O
advanced	O
architecture	O
"	O
with	O
a	O
focus	O
on	O
machine	O
learning	O
.	O
</s>
<s>
In	O
2017	O
,	O
Intel	O
announced	O
that	O
Knights	O
Hill	O
had	O
been	O
canceled	O
in	O
favor	O
of	O
another	O
architecture	O
built	O
from	O
the	O
ground	O
up	O
to	O
enable	O
Exascale	B-General_Concept
computing	I-General_Concept
in	O
the	O
future	O
.	O
</s>
<s>
Knights	O
Mill	O
is	O
Intel	O
's	O
codename	O
for	O
a	O
Xeon	B-General_Concept
Phi	I-General_Concept
product	O
specialized	O
in	O
deep	B-Algorithm
learning	I-Algorithm
,	O
initially	O
released	O
in	O
December	O
2017	O
.	O
</s>
<s>
Nearly	O
identical	O
in	O
specifications	O
to	O
Knights	O
Landing	O
,	O
Knights	O
Mill	O
includes	O
optimizations	O
for	O
better	O
utilization	O
of	O
AVX-512	B-General_Concept
instructions	O
and	O
enables	O
four-way	O
hyper-threading	B-Operating_System
.	O
</s>
<s>
Single-precision	O
and	O
variable-precision	O
floating-point	B-Algorithm
performance	O
increased	O
,	O
at	O
the	O
expense	O
of	O
double-precision	O
floating-point	B-Algorithm
performance	O
.	O
</s>
<s>
One	O
performance	O
and	O
programmability	O
study	O
reported	O
that	O
achieving	O
high	O
performance	O
with	O
Xeon	B-General_Concept
Phi	I-General_Concept
still	O
needs	O
help	O
from	O
programmers	O
and	O
that	O
merely	O
relying	O
on	O
compilers	O
with	O
traditional	O
programming	O
models	O
is	O
insufficient	O
.	O
</s>
<s>
Other	O
studies	O
in	O
various	O
domains	O
,	O
such	O
as	O
life	O
sciences	O
and	O
deep	B-Algorithm
learning	I-Algorithm
,	O
have	O
shown	O
that	O
exploiting	O
the	O
thread	O
-	O
and	O
SIMD-parallelism	O
of	O
Xeon	B-General_Concept
Phi	I-General_Concept
achieves	O
significant	O
speed-ups	O
.	O
</s>
