<s>
Xeon	B-Device
(	O
)	O
is	O
a	O
brand	O
of	O
x86	B-Operating_System
microprocessors	I-Operating_System
designed	O
,	O
manufactured	O
,	O
and	O
marketed	O
by	O
Intel	O
,	O
targeted	O
at	O
the	O
non-consumer	O
workstation	B-Device
,	O
server	B-Application
,	O
and	O
embedded	B-Architecture
system	I-Architecture
markets	O
.	O
</s>
<s>
Xeon	B-Device
processors	O
are	O
based	O
on	O
the	O
same	O
architecture	O
as	O
regular	O
desktop-grade	O
CPUs	O
,	O
but	O
have	O
advanced	O
features	O
such	O
as	O
support	O
for	O
ECC	B-General_Concept
memory	I-General_Concept
,	O
higher	O
core	B-Device
counts	O
,	O
more	O
PCI	O
Express	O
lanes	O
,	O
support	O
for	O
larger	O
amounts	O
of	O
RAM	O
,	O
larger	O
cache	B-General_Concept
memory	I-General_Concept
and	O
extra	O
provision	O
for	O
enterprise-grade	O
reliability	B-General_Concept
,	I-General_Concept
availability	I-General_Concept
and	I-General_Concept
serviceability	I-General_Concept
(	O
RAS	B-General_Concept
)	O
features	O
responsible	O
for	O
handling	O
hardware	O
exceptions	O
through	O
the	O
Machine	B-Device
Check	I-Device
Architecture	I-Device
.	O
</s>
<s>
They	O
are	O
often	O
capable	O
of	O
safely	O
continuing	O
execution	O
where	O
a	O
normal	O
processor	O
cannot	O
due	O
to	O
these	O
extra	O
RAS	B-General_Concept
features	O
,	O
depending	O
on	O
the	O
type	O
and	O
severity	O
of	O
the	O
machine-check	B-Device
exception	I-Device
(	O
MCE	O
)	O
.	O
</s>
<s>
Some	O
also	O
support	O
multi-socket	O
systems	O
with	O
two	O
,	O
four	O
,	O
or	O
eight	O
sockets	O
through	O
use	O
of	O
the	O
Ultra	B-Architecture
Path	I-Architecture
Interconnect	I-Architecture
(	O
UPI	O
)	O
bus	O
.	O
</s>
<s>
The	O
Xeon	B-Device
brand	O
has	O
been	O
maintained	O
over	O
several	O
generations	O
of	O
IA-32	B-Device
and	O
x86-64	B-Device
processors	O
.	O
</s>
<s>
Older	O
models	O
added	O
the	O
Xeon	B-Device
moniker	O
to	O
the	O
end	O
of	O
the	O
name	O
of	O
their	O
corresponding	O
desktop	O
processor	O
,	O
but	O
more	O
recent	O
models	O
used	O
the	O
name	O
Xeon	B-Device
on	O
its	O
own	O
.	O
</s>
<s>
The	O
Xeon	B-Device
CPUs	O
generally	O
have	O
more	O
cache	B-General_Concept
than	O
their	O
desktop	O
counterparts	O
in	O
addition	O
to	O
multiprocessing	O
capabilities	O
.	O
</s>
<s>
Some	O
shortcomings	O
that	O
make	O
Xeon	B-Device
processors	O
unsuitable	O
for	O
most	O
consumer-grade	O
desktop	O
PCs	O
include	O
lower	O
clock	O
rates	O
at	O
the	O
same	O
price	O
point	O
(	O
since	O
servers	O
run	O
more	O
tasks	O
in	O
parallel	O
than	O
desktops	O
,	O
core	B-Device
counts	O
are	O
more	O
important	O
than	O
clock	O
rates	O
)	O
,	O
and	O
,	O
usually	O
,	O
the	O
lack	O
of	O
an	O
integrated	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Application
)	O
.	O
</s>
<s>
Processor	O
models	O
prior	O
to	O
Sapphire	O
Rapids-WS	O
lack	O
support	O
for	O
overclocking	B-Application
(	O
with	O
the	O
exception	O
of	O
Xeon	B-Device
W-3175X	O
)	O
.	O
</s>
<s>
Despite	O
such	O
disadvantages	O
,	O
Xeon	B-Device
processors	O
have	O
always	O
had	O
popularity	O
among	O
some	O
desktop	O
users	O
(	O
video	O
editors	O
and	O
other	O
power	B-General_Concept
users	I-General_Concept
)	O
,	O
mainly	O
due	O
to	O
higher	O
core	B-Device
count	O
potential	O
,	O
and	O
higher	O
performance	O
to	O
price	O
ratio	O
vs.	O
the	O
Core	B-Device
i7	I-Device
in	O
terms	O
of	O
total	O
computing	O
power	O
of	O
all	O
cores	B-Architecture
.	O
</s>
<s>
Since	O
most	O
Intel	B-Device
Xeon	I-Device
CPUs	I-Device
lack	O
an	O
integrated	O
GPU	B-Application
,	O
systems	O
built	O
with	O
those	O
processors	O
require	O
a	O
discrete	O
graphics	O
card	O
or	O
a	O
separate	O
GPU	B-Application
if	O
computer	B-Device
monitor	I-Device
output	O
is	O
desired	O
.	O
</s>
<s>
Intel	B-Device
Xeon	I-Device
is	O
a	O
distinct	O
product	O
line	O
from	O
the	O
similarly-named	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
.	O
</s>
<s>
The	O
first-generation	O
Xeon	B-General_Concept
Phi	I-General_Concept
is	O
a	O
completely	O
different	O
type	O
of	O
device	O
more	O
comparable	O
to	O
a	O
graphics	O
card	O
;	O
it	O
is	O
designed	O
for	O
a	O
PCI	O
Express	O
slot	O
and	O
is	O
meant	O
to	O
be	O
used	O
as	O
a	O
multi-core	B-Architecture
coprocessor	O
,	O
like	O
the	O
Nvidia	B-Device
Tesla	I-Device
.	O
</s>
<s>
In	O
the	O
second	O
generation	O
,	O
Xeon	B-General_Concept
Phi	I-General_Concept
evolved	O
into	O
a	O
main	O
processor	O
more	O
similar	O
to	O
the	O
Xeon	B-Device
.	O
</s>
<s>
It	O
conforms	O
to	O
the	O
same	O
socket	O
as	O
a	O
Xeon	B-Device
processor	O
and	O
is	O
x86-compatible	O
;	O
however	O
,	O
as	O
compared	O
to	O
Xeon	B-Device
,	O
the	O
design	O
point	O
of	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
emphasizes	O
more	O
cores	B-Architecture
with	O
higher	O
memory	O
bandwidth	O
.	O
</s>
<s>
The	O
first	O
Xeon-branded	O
processor	O
was	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	B-Device
(	O
code-named	O
"	O
Drake	O
"	O
)	O
.	O
</s>
<s>
It	O
was	O
released	O
in	O
1998	O
,	O
replacing	O
the	O
Pentium	B-Device
Pro	I-Device
in	O
Intel	O
's	O
server	B-Application
lineup	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	B-Device
was	O
a	O
"	O
Deschutes	O
"	O
Pentium	B-General_Concept
II	I-General_Concept
(	O
and	O
shared	O
the	O
same	O
product	O
code	O
:	O
80523	O
)	O
with	O
a	O
full-speed	O
512kB	O
(	O
1	O
kB	O
=	O
1024	O
B	O
)	O
,	O
1MB	O
(	O
1	O
MB	O
=	O
1024	O
kB	O
=	O
10242	O
B	O
)	O
,	O
or	O
2MB	O
L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
L2	B-General_Concept
cache	I-General_Concept
was	O
implemented	O
with	O
custom	O
512	O
kB	O
SRAMs	O
developed	O
by	O
Intel	O
.	O
</s>
<s>
The	O
number	O
of	O
SRAMs	O
depended	O
on	O
the	O
amount	O
of	O
cache	B-General_Concept
.	O
</s>
<s>
Each	O
SRAM	O
was	O
a	O
12.90mm	O
by	O
17.23mm	O
(	O
222.21mm	O
)	O
die	O
fabricated	O
in	O
a	O
0.35µm	O
four-layer	O
metal	O
CMOS	O
process	O
and	O
packaged	O
in	O
a	O
cavity-down	O
wire-bonded	O
land	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
.	O
</s>
<s>
The	O
additional	O
cache	B-General_Concept
required	O
a	O
larger	O
module	O
and	O
thus	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	B-Device
used	O
a	O
larger	O
slot	O
,	O
Slot	B-Device
2	I-Device
.	O
</s>
<s>
It	O
was	O
supported	O
by	O
the	O
440GX	O
dual-processor	O
workstation	B-Device
chipset	B-Device
and	O
the	O
450NX	O
quad	O
-	O
or	O
octo-processor	O
chipset	B-Device
.	O
</s>
<s>
In	O
1999	O
,	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
Xeon	B-Device
was	O
replaced	O
by	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
Xeon	B-Device
.	O
</s>
<s>
Reflecting	O
the	O
incremental	O
changes	O
from	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
"	O
Deschutes	O
"	O
core	B-Device
to	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
"	O
Katmai	O
"	O
core	B-Device
,	O
the	O
first	O
Pentium	B-General_Concept
III	I-General_Concept
Xeon	B-Device
,	O
named	O
"	O
Tanner	O
"	O
,	O
was	O
just	O
like	O
its	O
predecessor	O
except	O
for	O
the	O
addition	O
of	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
(	O
SSE	O
)	O
and	O
a	O
few	O
cache	B-General_Concept
controller	O
improvements	O
.	O
</s>
<s>
The	O
second	O
version	O
,	O
named	O
"	O
Cascades	O
"	O
,	O
was	O
based	O
on	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
"	O
Coppermine	O
"	O
core	B-Device
.	O
</s>
<s>
The	O
"	O
Cascades	O
"	O
Xeon	B-Device
used	O
a	O
133MHz	O
bus	O
and	O
relatively	O
small	O
256kB	O
on-die	O
L2	B-General_Concept
cache	I-General_Concept
resulting	O
in	O
almost	O
the	O
same	O
capabilities	O
as	O
the	O
Slot	B-Device
1	I-Device
Coppermine	O
processors	O
,	O
which	O
were	O
capable	O
of	O
dual-processor	O
operation	O
but	O
not	O
quad-processor	O
operation	O
.	O
</s>
<s>
That	O
came	O
in	O
two	O
variants	O
:	O
with	O
1MB	O
or	O
2MB	O
of	O
L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Its	O
bus	O
speed	O
was	O
fixed	O
at	O
100MHz	O
,	O
though	O
in	O
practice	O
the	O
cache	B-General_Concept
was	O
able	O
to	O
offset	O
this	O
.	O
</s>
<s>
In	O
mid-2001	O
,	O
the	O
Xeon	B-Device
brand	O
was	O
introduced	O
(	O
"	O
Pentium	O
"	O
was	O
dropped	O
from	O
the	O
name	O
)	O
.	O
</s>
<s>
The	O
initial	O
variant	O
that	O
used	O
the	O
new	O
NetBurst	B-Device
microarchitecture	I-Device
,	O
"	O
Foster	O
"	O
,	O
was	O
slightly	O
different	O
from	O
the	O
desktop	O
Pentium	B-General_Concept
4	I-General_Concept
(	O
"	O
Willamette	O
"	O
)	O
.	O
</s>
<s>
It	O
was	O
a	O
decent	O
chip	O
for	O
workstations	B-Device
,	O
but	O
for	O
server	B-Application
applications	I-Application
it	O
was	O
almost	O
always	O
outperformed	O
by	O
the	O
older	O
Cascades	O
cores	B-Architecture
with	O
a	O
2	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
and	O
AMD	O
's	O
Athlon	B-Architecture
MP	I-Architecture
.	O
</s>
<s>
At	O
most	O
two	O
Foster	O
processors	O
could	O
be	O
accommodated	O
in	O
a	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	B-Operating_System
)	O
system	O
built	O
with	O
a	O
mainstream	O
chipset	B-Device
,	O
so	O
a	O
second	O
version	O
(	O
Foster	O
MP	O
)	O
was	O
introduced	O
with	O
a	O
1MB	O
L3	O
cache	B-General_Concept
and	O
the	O
Jackson	O
Hyper-Threading	B-Operating_System
capacity	O
.	O
</s>
<s>
In	O
2002	O
Intel	O
released	O
a	O
130	O
nm	O
version	O
of	O
Xeon	B-Device
branded	O
CPU	O
,	O
codenamed	O
"	O
Prestonia	O
"	O
.	O
</s>
<s>
It	O
supported	O
Intel	O
's	O
new	O
Hyper-Threading	B-Operating_System
technology	I-Operating_System
and	O
had	O
a	O
512kB	O
L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
This	O
was	O
based	O
on	O
the	O
"	O
Northwood	O
"	O
Pentium	B-General_Concept
4	I-General_Concept
core	B-Device
.	O
</s>
<s>
A	O
new	O
server	B-Application
chipset	B-Device
,	O
E7500	O
(	O
which	O
allowed	O
the	O
use	O
of	O
dual-channel	O
DDR	O
SDRAM	O
)	O
,	O
was	O
released	O
to	O
support	O
this	O
processor	O
in	O
servers	O
,	O
and	O
soon	O
the	O
bus	O
speed	O
was	O
boosted	O
to	O
533MT/s	O
(	O
accompanied	O
by	O
new	O
chipsets	B-Device
:	O
the	O
E7501	O
for	O
servers	O
and	O
the	O
E7505	O
for	O
workstations	B-Device
)	O
.	O
</s>
<s>
The	O
Prestonia	O
performed	O
much	O
better	O
than	O
its	O
predecessor	O
and	O
noticeably	O
better	O
than	O
Athlon	B-Architecture
MP	I-Architecture
.	O
</s>
<s>
The	O
support	O
of	O
new	O
features	O
in	O
the	O
E75xx	O
series	O
also	O
gave	O
it	O
a	O
key	O
advantage	O
over	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
Xeon	B-Device
and	O
Athlon	B-Architecture
MP	I-Architecture
branded	O
CPUs	O
(	O
both	O
stuck	O
with	O
rather	O
old	O
chipsets	B-Device
)	O
,	O
and	O
it	O
quickly	O
became	O
the	O
top-selling	O
server/workstation	O
processor	O
.	O
</s>
<s>
Subsequent	O
to	O
the	O
Prestonia	O
was	O
the	O
"	O
Gallatin	O
"	O
,	O
which	O
had	O
an	O
L3	O
cache	B-General_Concept
of	O
1MB	O
or	O
2MB	O
.	O
</s>
<s>
Its	O
Xeon	B-Device
MP	I-Device
version	O
also	O
performed	O
much	O
better	O
than	O
the	O
Foster	O
MP	O
,	O
and	O
was	O
popular	O
in	O
servers	O
.	O
</s>
<s>
Later	O
experience	O
with	O
the	O
130nm	B-Algorithm
process	O
allowed	O
Intel	O
to	O
create	O
the	O
Xeon	B-Device
MP	I-Device
branded	O
Gallatin	O
with	O
4MB	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
Xeon	B-Device
branded	O
Prestonia	O
and	O
Gallatin	O
were	O
designated	O
80532	O
,	O
like	O
Northwood	O
.	O
</s>
<s>
Due	O
to	O
a	O
lack	O
of	O
success	O
with	O
Intel	O
's	O
Itanium	B-General_Concept
and	O
Itanium	B-General_Concept
2	O
processors	O
,	O
AMD	O
was	O
able	O
to	O
introduce	O
x86-64	B-Device
,	O
a	O
64-bit	O
extension	O
to	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
.	O
</s>
<s>
the	O
90	O
nm	O
version	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
(	O
"	O
Prescott	O
"	O
)	O
,	O
and	O
a	O
Xeon	B-Device
version	O
codenamed	O
"	O
Nocona	O
"	O
with	O
1	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
was	O
released	O
in	O
2004	O
.	O
</s>
<s>
Released	O
with	O
it	O
were	O
the	O
E7525	O
(	O
workstation	B-Device
)	O
,	O
E7520	O
and	O
E7320	O
(	O
both	O
server	B-Application
)	O
chipsets	B-Device
,	O
which	O
added	O
support	O
for	O
PCI	O
Express	O
,	O
DDR-II	O
and	O
Serial	O
ATA	O
.	O
</s>
<s>
The	O
Xeon	B-Device
was	O
noticeably	O
slower	O
than	O
AMD	O
's	O
Opteron	B-General_Concept
,	O
although	O
it	O
could	O
be	O
faster	O
in	O
situations	O
where	O
Hyper-Threading	B-Operating_System
came	O
into	O
play	O
.	O
</s>
<s>
A	O
slightly	O
updated	O
core	B-Device
called	O
"	O
Irwindale	O
"	O
was	O
released	O
in	O
early	O
2005	O
,	O
with	O
2	O
MB	O
L2	B-General_Concept
cache	I-General_Concept
and	O
the	O
ability	O
to	O
have	O
its	O
clock	O
speed	O
reduced	O
during	O
low	O
processor	O
demand	O
.	O
</s>
<s>
Although	O
it	O
was	O
a	O
bit	O
more	O
competitive	O
than	O
the	O
Nocona	O
had	O
been	O
,	O
independent	O
showed	O
that	O
AMD	O
's	O
Opteron	B-General_Concept
still	O
outperformed	O
Irwindale	O
.	O
</s>
<s>
Both	O
of	O
these	O
Prescott-derived	O
Xeons	B-Device
have	O
the	O
product	O
code	O
80546	O
.	O
</s>
<s>
64-bit	O
Xeon	B-Device
MPs	I-Device
were	O
introduced	O
in	O
April	O
2005	O
.	O
</s>
<s>
The	O
cheaper	O
"	O
Cranford	O
"	O
was	O
an	O
MP	O
version	O
of	O
Nocona	O
,	O
while	O
the	O
more	O
expensive	O
"	O
Potomac	O
"	O
was	O
a	O
Cranford	O
with	O
8MB	O
of	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
first	O
dual-core	B-Architecture
CPU	O
branded	O
Xeon	B-Device
,	O
codenamed	O
Paxville	O
DP	O
,	O
product	O
code	O
80551	O
,	O
was	O
released	O
by	O
Intel	O
on	O
October	O
10	O
,	O
2005	O
.	O
</s>
<s>
Paxville	O
DP	O
had	O
NetBurst	B-Device
microarchitecture	I-Device
,	O
and	O
was	O
a	O
dual-core	B-Architecture
equivalent	O
of	O
the	O
single-core	O
Irwindale	O
(	O
related	O
to	O
the	O
Pentium	B-Device
D	I-Device
branded	O
"	O
Smithfield	B-Device
"	O
)	O
with	O
4MB	O
of	O
L2	B-General_Concept
Cache	I-General_Concept
(	O
2MB	O
per	O
core	B-Device
)	O
.	O
</s>
<s>
The	O
only	O
Paxville	O
DP	O
model	O
released	O
ran	O
at	O
2.8GHz	O
,	O
featured	O
an	O
800MT/s	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
,	O
and	O
was	O
produced	O
using	O
a	O
90	O
nm	O
process	O
.	O
</s>
<s>
There	O
are	O
two	O
versions	O
:	O
one	O
with	O
2MB	O
of	O
L2	B-General_Concept
Cache	I-General_Concept
(	O
1MB	O
per	O
core	B-Device
)	O
,	O
and	O
one	O
with	O
4MB	O
of	O
L2	O
(	O
2MB	O
per	O
core	B-Device
)	O
.	O
</s>
<s>
Paxville	O
MP	O
,	O
called	O
the	O
dual-core	B-Device
Xeon	I-Device
7000-series	O
,	O
was	O
produced	O
using	O
a	O
90nm	O
process	O
.	O
</s>
<s>
Paxville	O
MP	O
clock	O
ranges	O
between	O
2.67GHz	O
and	O
3.0GHz	O
(	O
model	O
numbers	O
7020	O
–	O
7041	O
)	O
,	O
with	O
some	O
models	O
having	O
a	O
667MT/s	O
FSB	B-Architecture
,	O
and	O
others	O
having	O
an	O
800MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
Released	O
on	O
August	O
29	O
,	O
2006	O
,	O
the	O
7100	O
series	O
,	O
codenamed	O
Tulsa	O
(	O
product	O
code	O
80550	O
)	O
,	O
is	O
an	O
improved	O
version	O
of	O
Paxville	O
MP	O
,	O
built	O
on	O
a	O
65nm	B-Algorithm
process	I-Algorithm
,	O
with	O
2MB	O
of	O
L2	B-General_Concept
cache	I-General_Concept
(	O
1MB	O
per	O
core	B-Device
)	O
and	O
up	O
to	O
16MB	O
of	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
It	O
uses	O
Socket	B-Device
604	I-Device
.	O
</s>
<s>
Tulsa	O
was	O
released	O
in	O
two	O
lines	O
:	O
the	O
N-line	O
uses	O
a	O
667MT/s	O
FSB	B-Architecture
,	O
and	O
the	O
M-line	O
uses	O
an	O
800MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
L3	O
cache	B-General_Concept
ranges	O
from	O
4MB	O
to	O
16MB	O
across	O
the	O
models	O
.	O
</s>
<s>
On	O
May	O
23	O
,	O
2006	O
,	O
Intel	O
released	O
the	O
dual-core	B-Architecture
CPU	O
(	O
Xeon	B-Device
branded	O
5000	O
series	O
)	O
codenamed	O
Dempsey	O
(	O
product	O
code	O
80555	O
)	O
.	O
</s>
<s>
Released	O
as	O
the	O
Dual-Core	B-Device
Xeon	I-Device
5000-series	O
,	O
Dempsey	O
is	O
a	O
NetBurst	B-Device
microarchitecture	I-Device
processor	O
produced	O
using	O
a	O
65	O
nm	O
process	O
,	O
and	O
is	O
virtually	O
identical	O
to	O
Intel	O
's	O
"	O
Presler	B-Device
"	O
Pentium	B-Device
Extreme	I-Device
Edition	I-Device
,	O
except	O
for	O
the	O
addition	O
of	O
SMP	B-Operating_System
support	O
,	O
which	O
lets	O
Dempsey	O
operate	O
in	O
dual-processor	O
systems	O
.	O
</s>
<s>
Some	O
models	O
have	O
a	O
667MT/s	O
FSB	B-Architecture
,	O
and	O
others	O
have	O
a	O
1066MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
Dempsey	O
has	O
4MB	O
of	O
L2	B-General_Concept
Cache	I-General_Concept
(	O
2MB	O
per	O
core	B-Device
)	O
.	O
</s>
<s>
A	O
Medium	O
Voltage	O
model	O
,	O
at	O
3.2GHz	O
and	O
1066MT/s	O
FSB	B-Architecture
(	O
model	O
number	O
5063	O
)	O
,	O
has	O
also	O
been	O
released	O
.	O
</s>
<s>
Dempsey	O
also	O
introduces	O
a	O
new	O
interface	O
for	O
Xeon	B-Device
processors	O
:	O
LGA	B-Device
771	I-Device
,	O
also	O
known	O
as	O
Socket	B-Device
J	I-Device
.	O
Dempsey	O
was	O
the	O
first	O
Xeon	B-Device
core	B-Device
in	O
a	O
long	O
time	O
to	O
be	O
somewhat	O
competitive	O
with	O
its	O
Opteron-based	O
counterparts	O
,	O
although	O
it	O
could	O
not	O
claim	O
a	O
decisive	O
lead	O
in	O
any	O
performance	O
metric	O
–	O
that	O
would	O
have	O
to	O
wait	O
for	O
its	O
successor	O
,	O
the	O
Woodcrest	O
.	O
</s>
<s>
On	O
March	O
14	O
,	O
2006	O
,	O
Intel	O
released	O
a	O
dual-core	B-Architecture
processor	I-Architecture
codenamed	O
Sossaman	O
and	O
branded	O
as	O
Xeon	B-Device
LV	O
(	O
low-voltage	O
)	O
.	O
</s>
<s>
The	O
Sossaman	O
was	O
a	O
low-/ultra	O
-low-power	O
and	O
double-processor	O
capable	O
CPU	O
(	O
like	O
AMD	O
Quad	O
FX	O
)	O
,	O
based	O
on	O
the	O
"	O
Yonah	B-Device
"	O
processor	O
,	O
for	O
ultradense	O
non-consumer	O
environment	O
(	O
i.e.	O
,	O
targeted	O
at	O
the	O
blade-server	O
and	O
embedded	O
markets	O
)	O
,	O
and	O
was	O
rated	O
at	O
a	O
thermal	B-General_Concept
design	I-General_Concept
power	I-General_Concept
(	O
TDP	B-General_Concept
)	O
of	O
31	O
W	O
(	O
LV	O
:	O
1.66GHz	O
,	O
2GHz	O
and	O
2.16GHz	O
)	O
and	O
15	O
W	O
(	O
ULV	O
:	O
1.66GHz	O
)	O
.	O
</s>
<s>
As	O
such	O
,	O
it	O
supported	O
most	O
of	O
the	O
same	O
features	O
as	O
earlier	O
Xeons	B-Device
:	O
Virtualization	B-General_Concept
Technology	I-General_Concept
,	O
667MT/s	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
,	O
and	O
dual-core	B-Architecture
processing	O
,	O
but	O
did	O
not	O
support	O
64-bit	O
operations	O
,	O
so	O
it	O
could	O
not	O
run	O
64-bit	O
server	B-Application
software	I-Application
,	O
such	O
as	O
Microsoft	O
Exchange	O
Server	B-Application
2007	O
,	O
and	O
therefore	O
was	O
limited	O
to	O
16GB	O
of	O
memory	O
.	O
</s>
<s>
A	O
planned	O
successor	O
,	O
codenamed	O
"	O
Merom	B-Device
MP	O
"	O
was	O
to	O
be	O
a	O
drop-in	O
upgrade	O
to	O
enable	O
Sossaman-based	O
servers	O
to	O
upgrade	O
to	O
64-bit	O
capability	O
.	O
</s>
<s>
The	O
3000	O
series	O
,	O
codenamed	O
Conroe	O
(	O
product	O
code	O
80557	O
)	O
dual-core	B-Device
Xeon	I-Device
(	O
branded	O
)	O
CPU	O
,	O
released	O
at	O
the	O
end	O
of	O
September	O
2006	O
,	O
was	O
the	O
first	O
Xeon	B-Device
for	O
single-CPU	O
operation	O
.	O
</s>
<s>
The	O
same	O
processor	O
is	O
branded	O
as	O
Core	B-Device
2	I-Device
Duo	I-Device
or	O
as	O
Pentium	B-Device
Dual-Core	I-Device
and	O
Celeron	B-Device
,	O
with	O
varying	O
features	O
disabled	O
.	O
</s>
<s>
They	O
use	O
LGA	B-Device
775	I-Device
(	O
Socket	B-Device
T	I-Device
)	O
,	O
operate	O
on	O
a	O
1066MHz	O
front-side	B-Architecture
bus	I-Architecture
,	O
support	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
and	O
Intel	O
Virtualization	B-General_Concept
Technology	I-General_Concept
but	O
do	O
not	O
support	O
Hyper-Threading	B-Operating_System
.	O
</s>
<s>
Conroe	O
Processors	O
with	O
a	O
number	O
ending	O
in	O
"	O
5	O
"	O
have	O
a	O
1333MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
The	O
3100	O
series	O
,	O
codenamed	O
Wolfdale	B-Device
(	O
product	O
code	O
80570	O
)	O
dual-core	B-Device
Xeon	I-Device
(	O
branded	O
)	O
CPU	O
,	O
was	O
just	O
a	O
rebranded	O
version	O
of	O
the	O
Intel	O
's	O
mainstream	O
Core	B-Device
2	I-Device
Duo	I-Device
E7000/E8000	O
and	O
Pentium	B-Device
Dual-Core	I-Device
E5000	O
processors	O
,	O
featuring	O
the	O
same	O
45	O
nm	O
process	O
and	O
6MB	O
of	O
L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Unlike	O
most	O
Xeon	B-Device
processors	O
,	O
they	O
only	O
support	O
single-CPU	O
operation	O
.	O
</s>
<s>
They	O
use	O
LGA	B-Device
775	I-Device
(	O
Socket	B-Device
T	I-Device
)	O
,	O
operate	O
on	O
a	O
1333MHz	O
front-side	B-Architecture
bus	I-Architecture
,	O
support	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
and	O
Intel	O
Virtualization	B-General_Concept
Technology	I-General_Concept
but	O
do	O
not	O
support	O
Hyper-Threading	B-Operating_System
.	O
</s>
<s>
On	O
June	O
26	O
,	O
2006	O
,	O
Intel	O
released	O
the	O
dual-core	B-Architecture
CPU	O
(	O
Xeon	B-Device
branded	O
5100	O
series	O
)	O
codenamed	O
Woodcrest	O
(	O
product	O
code	O
80556	O
)	O
;	O
it	O
was	O
the	O
first	O
Intel	B-Device
Core	I-Device
microarchitecture	I-Device
processor	O
to	O
be	O
launched	O
on	O
the	O
market	O
.	O
</s>
<s>
It	O
is	O
a	O
server	B-Application
and	O
workstation	B-Device
version	O
of	O
the	O
Intel	B-Device
Core	I-Device
2	I-Device
processor	O
.	O
</s>
<s>
Intel	O
claimed	O
that	O
it	O
provides	O
an	O
80%	O
boost	O
in	O
performance	O
,	O
while	O
reducing	O
power	O
consumption	O
by	O
20%	O
relative	O
to	O
the	O
Pentium	B-Device
D	I-Device
.	O
</s>
<s>
Most	O
models	O
have	O
a	O
1333MT/s	O
FSB	B-Architecture
,	O
except	O
for	O
the	O
5110	O
and	O
5120	O
,	O
which	O
have	O
a	O
1066MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
All	O
Woodcrest	O
processors	O
use	O
the	O
LGA	B-Device
771	I-Device
socket	O
and	O
all	O
except	O
two	O
models	O
have	O
a	O
TDP	B-General_Concept
of	O
65W	O
.	O
</s>
<s>
The	O
5160	O
has	O
a	O
TDP	B-General_Concept
of	O
80W	O
and	O
the	O
5148LV	O
(	O
2.33GHz	O
)	O
has	O
a	O
TDP	B-General_Concept
of	O
40W	O
.	O
</s>
<s>
The	O
previous	O
generation	O
Xeons	B-Device
had	O
a	O
TDP	B-General_Concept
of	O
130W	O
.	O
</s>
<s>
All	O
models	O
support	O
Intel	O
64	O
(	O
Intel	O
's	O
x86-64	B-Device
implementation	O
)	O
,	O
the	O
XD	B-General_Concept
bit	I-General_Concept
,	O
and	O
Virtualization	B-General_Concept
Technology	I-General_Concept
,	O
with	O
the	O
Demand-based	O
switching	O
power	O
management	O
option	O
only	O
on	O
Dual-Core	B-Device
Xeon	I-Device
5140	O
or	O
above	O
.	O
</s>
<s>
Woodcrest	O
has	O
4MB	O
of	O
shared	O
L2	B-General_Concept
Cache	I-General_Concept
.	O
</s>
<s>
On	O
November	O
11	O
,	O
2007	O
,	O
Intel	O
released	O
the	O
dual-core	B-Architecture
CPU	O
(	O
Xeon	B-Device
branded	O
5200	O
series	O
)	O
codenamed	O
Wolfdale-DP	O
(	O
product	O
code	O
80573	O
)	O
.	O
</s>
<s>
It	O
is	O
built	O
on	O
a	O
45	O
nm	O
process	O
like	O
the	O
desktop	O
Core	B-Device
2	I-Device
Duo	I-Device
and	O
Xeon-SP	O
Wolfdale	B-Device
,	O
featuring	O
Intel	O
64	O
(	O
Intel	O
's	O
x86-64	B-Device
implementation	O
)	O
,	O
the	O
XD	B-General_Concept
bit	I-General_Concept
,	O
and	O
Virtualization	B-General_Concept
Technology	I-General_Concept
.	O
</s>
<s>
Wolfdale	B-Device
has	O
6MB	O
of	O
shared	O
L2	B-General_Concept
Cache	I-General_Concept
.	O
</s>
<s>
The	O
7200	O
series	O
,	O
codenamed	O
Tigerton	O
(	O
product	O
code	O
80564	O
)	O
is	O
an	O
MP-capable	O
processor	O
,	O
similar	O
to	O
the	O
7300	O
series	O
,	O
but	O
,	O
in	O
contrast	O
,	O
only	O
one	O
core	B-Device
is	I-Device
active	O
on	O
each	O
silicon	O
chip	O
and	O
the	O
other	O
one	O
is	O
disabled	O
,	O
resulting	O
in	O
a	O
dual-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
Intel	O
released	O
relabeled	O
versions	O
of	O
its	O
quad-core	B-Architecture
(	O
2×2	O
)	O
Core	B-Device
2	I-Device
Quad	I-Device
processor	O
as	O
the	O
Xeon	B-Device
3200-series	O
(	O
product	O
code	O
80562	O
)	O
on	O
January	O
7	O
,	O
2007	O
.	O
</s>
<s>
The	O
2×2	O
"	O
quad-core	B-Architecture
"	O
(	O
dual-die	O
dual-core	B-Architecture
)	O
comprised	O
two	O
separate	O
dual-core	B-Architecture
die	O
next	O
to	O
each	O
other	O
in	O
one	O
CPU	O
package	O
.	O
</s>
<s>
Like	O
the	O
3000-series	O
,	O
these	O
models	O
only	O
support	O
single-CPU	O
operation	O
and	O
operate	O
on	O
a	O
1066MHz	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Intel	O
released	O
relabeled	O
versions	O
of	O
its	O
quad-core	B-Architecture
Core	B-Device
2	I-Device
Quad	I-Device
Yorkfield	B-Device
Q9300	O
,	O
Q9400	O
,	O
Q9x50	O
and	O
QX9770	O
processors	O
as	O
the	O
Xeon	B-Device
3300-series	O
(	O
product	O
code	O
80569	O
)	O
.	O
</s>
<s>
This	O
processor	O
comprises	O
two	O
separate	O
dual-core	B-Architecture
dies	O
next	O
to	O
each	O
other	O
in	O
one	O
CPU	O
package	O
and	O
manufactured	O
in	O
a	O
45	O
nm	O
process	O
.	O
</s>
<s>
The	O
L2	B-General_Concept
cache	I-General_Concept
is	O
a	O
unified	O
6MB	O
per	O
die	O
(	O
except	O
for	O
the	O
X3320	O
and	O
X3330	O
with	O
a	O
smaller	O
3MB	O
L2	B-General_Concept
cache	I-General_Concept
per	O
die	O
)	O
,	O
and	O
a	O
front-side	B-Architecture
bus	I-Architecture
of	O
1333MHz	O
.	O
</s>
<s>
All	O
models	O
feature	O
Intel	O
64	O
(	O
Intel	O
's	O
x86-64	B-Device
implementation	O
)	O
,	O
the	O
XD	B-General_Concept
bit	I-General_Concept
,	O
and	O
Virtualization	B-General_Concept
Technology	I-General_Concept
,	O
as	O
well	O
as	O
Demand-based	O
switching	O
.	O
</s>
<s>
The	O
Yorkfield-CL	O
(	O
product	O
code	O
80584	O
)	O
variant	O
of	O
these	O
processors	O
are	O
X3323	O
,	O
X3353	O
and	O
X3363	O
.	O
</s>
<s>
They	O
have	O
a	O
reduced	O
TDP	B-General_Concept
of	O
80W	O
and	O
are	O
made	O
for	O
single-CPU	O
LGA	B-Device
771	I-Device
systems	O
instead	O
of	O
LGA	B-Device
775	I-Device
,	O
which	O
is	O
used	O
in	O
all	O
other	O
Yorkfield	B-Device
processors	O
.	O
</s>
<s>
In	O
all	O
other	O
respects	O
,	O
they	O
are	O
identical	O
to	O
their	O
Yorkfield	B-Device
counterparts	O
.	O
</s>
<s>
A	O
quad-core	B-Architecture
(	O
2×2	O
)	O
successor	O
of	O
the	O
Woodcrest	O
for	O
DP	O
segment	O
,	O
consisting	O
of	O
two	O
dual-core	B-Architecture
Woodcrest	O
chips	O
in	O
one	O
package	O
similarly	O
to	O
the	O
dual-core	B-Architecture
Pentium	B-Device
D	I-Device
branded	O
CPUs	O
(	O
two	O
single-core	O
chips	O
)	O
or	O
the	O
quad-core	B-Architecture
Kentsfield	B-Device
.	O
</s>
<s>
All	O
Clovertowns	B-Device
use	O
the	O
LGA	B-Device
771	I-Device
package	O
.	O
</s>
<s>
The	O
Clovertown	B-Device
has	O
been	O
usually	O
implemented	O
with	O
two	O
Woodcrest	O
dies	O
on	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
,	O
with	O
8MB	O
of	O
L2	B-General_Concept
cache	I-General_Concept
(	O
4MB	O
per	O
die	O
)	O
.	O
</s>
<s>
Like	O
Woodcrest	O
,	O
lower	O
models	O
use	O
a	O
1066MT/s	O
FSB	B-Architecture
,	O
and	O
higher	O
models	O
use	O
a	O
1333MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
Intel	O
released	O
Clovertown	B-Device
,	O
product	O
code	O
80563	O
,	O
on	O
November	O
14	O
,	O
2006	O
with	O
models	O
E5310	O
,	O
E5320	O
,	O
E5335	O
,	O
E5345	O
,	O
and	O
X5355	O
,	O
ranging	O
from	O
1.6GHz	O
to	O
2.66GHz	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	O
,	O
SSE	O
,	O
SSE2	O
,	O
SSE3	O
,	O
SSSE3	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT	O
.	O
</s>
<s>
The	O
E	O
and	O
X	O
designations	O
are	O
borrowed	O
from	O
Intel	O
's	O
Core	B-Device
2	I-Device
model	O
numbering	O
scheme	O
;	O
an	O
ending	O
of	O
-0	O
implies	O
a	O
1066MT/s	O
FSB	B-Architecture
,	O
and	O
an	O
ending	O
of	O
-5	O
implies	O
a	O
1333MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
All	O
models	O
have	O
a	O
TDP	B-General_Concept
of	O
80W	O
with	O
the	O
exception	O
of	O
the	O
X5355	O
,	O
which	O
has	O
a	O
TDP	B-General_Concept
of	O
120W	O
,	O
and	O
the	O
X5365	O
,	O
which	O
has	O
a	O
TDP	B-General_Concept
of	O
150W	O
.	O
</s>
<s>
A	O
low-voltage	O
version	O
of	O
Clovertown	B-Device
with	O
a	O
TDP	B-General_Concept
of	O
50W	O
has	O
a	O
model	O
numbers	O
L5310	O
,	O
L5320	O
and	O
L5335	O
(	O
1.6GHz	O
,	O
1.86GHz	O
and	O
2.0GHz	O
respectively	O
)	O
.	O
</s>
<s>
The	O
3.0GHz	O
X5365	O
arrived	O
in	O
July	O
2007	O
,	O
and	O
became	O
available	O
in	O
the	O
Apple	B-Device
Mac	I-Device
Pro	I-Device
on	O
April	O
4	O
,	O
2007	O
.	O
</s>
<s>
On	O
November	O
11	O
,	O
2007	O
Intel	O
presented	O
Yorkfield-based	O
Xeons	B-Device
–	O
called	O
Harpertown	O
(	O
product	O
code	O
80574	O
)	O
–	O
to	O
the	O
public	O
.	O
</s>
<s>
This	O
family	O
consists	O
of	O
dual	O
die	O
quad-core	B-Architecture
CPUs	O
manufactured	O
on	O
a	O
45	O
nm	O
process	O
and	O
featuring	O
1066MHz	O
,	O
1333MHz	O
,	O
1600MHz	O
front-side	O
buses	O
,	O
with	O
TDP	B-General_Concept
rated	O
from	O
40W	O
to	O
150W	O
depending	O
on	O
the	O
model	O
.	O
</s>
<s>
These	O
processors	O
fit	O
in	O
the	O
LGA	B-Device
771	I-Device
package	O
.	O
</s>
<s>
All	O
models	O
feature	O
Intel	O
64	O
(	O
Intel	O
's	O
x86-64	B-Device
implementation	O
)	O
,	O
the	O
XD	B-General_Concept
bit	I-General_Concept
,	O
and	O
Virtualization	B-General_Concept
Technology	I-General_Concept
.	O
</s>
<s>
The	O
supplementary	O
character	O
in	O
front	O
of	O
the	O
model-number	O
represents	O
the	O
thermal	O
rating	O
:	O
an	O
L	O
depicts	O
a	O
TDP	B-General_Concept
of	O
40W	O
or	O
50W	O
,	O
an	O
E	O
depicts	O
80W	O
whereas	O
an	O
X	O
is	O
120W	O
TDP	B-General_Concept
or	O
above	O
.	O
</s>
<s>
The	O
speed	O
of	O
3.00GHz	O
comes	O
as	O
four	O
models	O
,	O
two	O
models	O
with	O
80W	O
TDP	B-General_Concept
two	O
other	O
models	O
with	O
120W	O
TDP	B-General_Concept
with	O
1333MHz	O
or	O
1600MHz	O
front-side	B-Architecture
bus	I-Architecture
respectively	O
.	O
</s>
<s>
The	O
fastest	O
Harpertown	O
is	O
the	O
X5492	O
whose	O
TDP	B-General_Concept
of	O
150W	O
is	O
higher	O
than	O
those	O
of	O
the	O
Prescott-based	O
Xeon	B-Device
DP	O
but	O
having	O
twice	O
as	O
many	O
cores	B-Architecture
.	O
</s>
<s>
(	O
The	O
X5482	O
is	O
also	O
sold	O
under	O
the	O
name	O
"	O
Core	B-Device
2	I-Device
Extreme	O
QX9775	O
"	O
for	O
use	O
in	O
the	O
Intel	B-Device
Skulltrail	I-Device
system	O
.	O
)	O
</s>
<s>
Intel	O
1600MHz	O
front-side	B-Architecture
bus	I-Architecture
Xeon	B-Device
processors	O
will	O
drop	O
into	O
the	O
Intel	O
5400	O
(	O
Seaburg	O
)	O
chipset	B-Device
whereas	O
several	O
mainboards	O
featuring	O
the	O
Intel	O
5000/5200	O
-chipset	O
are	O
enabled	O
to	O
run	O
the	O
processors	O
with	O
a	O
1333MHz	O
front-side	B-Architecture
bus	I-Architecture
speed	O
.	O
</s>
<s>
The	O
7300	O
series	O
,	O
codenamed	O
Tigerton	O
(	O
product	O
code	O
80565	O
)	O
is	O
a	O
four-socket	O
(	O
packaged	O
in	O
Socket	B-Device
604	I-Device
)	O
and	O
more	O
capable	O
quad-core	B-Architecture
processor	I-Architecture
,	O
consisting	O
of	O
two	O
dual	B-Architecture
core	I-Architecture
Core2	O
architecture	O
silicon	O
chips	O
on	O
a	O
single	O
ceramic	O
module	O
,	O
similar	O
to	O
Intel	O
's	O
Xeon	B-Device
5300	O
series	O
Clovertown	B-Device
processor	O
modules	O
.	O
</s>
<s>
Intel	O
claims	O
the	O
7300	O
series	O
Xeons	B-Device
offer	O
more	O
than	O
twice	O
the	O
performance	O
per	O
watt	O
as	O
Intel	O
's	O
previous	O
generation	O
7100	O
series	O
.	O
</s>
<s>
The	O
7300	O
series	O
 '	O
Caneland	O
chipset	B-Device
provides	O
a	O
point	O
to	O
point	O
interface	O
allowing	O
the	O
full	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
bandwidth	O
per	O
processor	O
.	O
</s>
<s>
The	O
7xxx	O
series	O
is	O
aimed	O
at	O
the	O
large	O
server	B-Application
market	O
,	O
supporting	O
configurations	O
of	O
up	O
to	O
32CPUs	O
per	O
host	O
.	O
</s>
<s>
Dunnington	O
–	O
the	O
last	O
CPU	O
of	O
the	O
Penryn	B-Device
generation	O
and	O
Intel	O
's	O
first	O
multi-core	B-Architecture
(	O
above	O
two	O
)	O
die	O
–	O
features	O
a	O
single-die	O
six	O
-	O
(	O
or	O
hexa	O
-	O
)	O
core	B-Device
design	O
with	O
three	O
unified	O
3MB	O
L2	O
caches	B-General_Concept
(	O
resembling	O
three	O
merged	O
45	O
nm	O
dual-core	B-Architecture
Wolfdale	B-Device
dies	O
)	O
,	O
and	O
96kB	O
L1	O
cache	B-General_Concept
(	O
Data	O
)	O
and	O
16MB	O
of	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
It	O
features	O
1066MHz	O
FSB	B-Architecture
,	O
fits	O
into	O
the	O
Tigerton	O
's	O
mPGA604	B-Device
socket	O
,	O
and	O
is	O
compatible	O
with	O
both	O
the	O
Intel	O
Caneland	O
and	O
IBM	O
X4	O
chipsets	B-Device
.	O
</s>
<s>
These	O
processors	O
support	O
DDR2-1066	O
(	O
533MHz	O
)	O
,	O
and	O
have	O
a	O
maximum	O
TDP	B-General_Concept
below	O
130W	O
.	O
</s>
<s>
It	O
was	O
followed	O
shortly	O
by	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Xeon	B-Device
3400-series	O
processors	O
based	O
on	O
Lynnfield	O
fill	O
the	O
gap	O
between	O
the	O
previous	O
3300-series	O
"	O
Yorkfield	B-Device
"	O
processors	O
and	O
the	O
newer	O
3500-series	O
"	O
Bloomfield	O
"	O
.	O
</s>
<s>
Like	O
Bloomfield	O
,	O
they	O
are	O
quad-core	B-Architecture
single-package	O
processors	O
based	O
on	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
,	O
but	O
were	O
introduced	O
almost	O
a	O
year	O
later	O
,	O
in	O
September	O
2009	O
.	O
</s>
<s>
The	O
same	O
processors	O
are	O
marketed	O
for	O
mid-range	O
to	O
high-end	O
desktops	O
systems	O
as	O
Core	B-Device
i5	I-Device
and	O
Core	B-Device
i7	I-Device
.	O
</s>
<s>
They	O
have	O
two	O
integrated	O
memory	O
channels	O
as	O
well	O
as	O
PCI	O
Express	O
and	O
Direct	B-Architecture
Media	I-Architecture
Interface	I-Architecture
(	O
DMI	O
)	O
links	O
,	O
but	O
no	O
QuickPath	B-Architecture
Interconnect	I-Architecture
(	O
QPI	B-Architecture
)	O
interface	O
.	O
</s>
<s>
At	O
low	O
end	O
of	O
the	O
3400-series	O
is	O
not	O
a	O
Lynnfield	O
but	O
a	O
Clarkdale	O
processor	O
,	O
which	O
is	O
also	O
used	O
in	O
the	O
Core	B-Device
i3-500	O
and	O
Core	B-Device
i5-600	O
processors	O
as	O
well	O
as	O
the	O
Celeron	B-Device
G1000	O
and	O
G6000	O
Pentium	O
series	O
.	O
</s>
<s>
A	O
single	O
model	O
was	O
released	O
in	O
March	O
2010	O
,	O
the	O
Xeon	B-Device
L3406	O
.	O
</s>
<s>
Compared	O
to	O
all	O
other	O
Clarkdale-based	O
products	O
,	O
this	O
one	O
does	O
not	O
support	O
integrated	O
graphics	O
,	O
but	O
has	O
a	O
much	O
lower	O
thermal	B-General_Concept
design	I-General_Concept
power	I-General_Concept
of	O
just	O
30	O
W	O
.	O
Compared	O
to	O
the	O
Lynnfield-based	O
Xeon	B-Device
3400	O
models	O
,	O
it	O
only	O
offers	O
two	O
cores	B-Architecture
.	O
</s>
<s>
Bloomfield	O
is	O
the	O
codename	O
for	O
the	O
successor	O
to	O
the	O
Xeon	B-Device
Core	B-Device
microarchitecture	I-Device
,	O
is	O
based	O
on	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
and	O
uses	O
the	O
same	O
45	O
nm	O
manufacturing	O
methods	O
as	O
Intel	O
's	O
Penryn	B-Device
.	O
</s>
<s>
The	O
first	O
processor	O
released	O
with	O
the	O
Nehalem	B-Device
architecture	O
is	O
the	O
desktop	O
Intel	B-Device
Core	I-Device
i7	I-Device
,	O
which	O
was	O
released	O
in	O
November	O
2008	O
.	O
</s>
<s>
This	O
is	O
the	O
server	B-Application
version	O
for	O
single	O
CPU	O
systems	O
.	O
</s>
<s>
This	O
is	O
a	O
single-socket	O
Intel	B-Device
Xeon	I-Device
processor	O
.	O
</s>
<s>
The	O
performance	O
improvements	O
over	O
previous	O
Xeon	B-Device
processors	O
are	O
based	O
mainly	O
on	O
:	O
</s>
<s>
Simultaneous	O
multithreading	B-Operating_System
by	O
multiple	O
cores	B-Architecture
and	O
hyper-threading	B-Operating_System
(	O
2×	O
per	O
core	B-Device
)	O
.	O
</s>
<s>
Gainestown	O
or	O
Nehalem-EP	O
,	O
the	O
successor	O
to	O
the	O
Xeon	B-Device
Core	B-Device
microarchitecture	I-Device
,	O
is	O
based	O
on	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
and	O
uses	O
the	O
same	O
45	O
nm	O
manufacturing	O
methods	O
as	O
Intel	O
's	O
Penryn	B-Device
.	O
</s>
<s>
The	O
first	O
processor	O
released	O
with	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
is	O
the	O
desktop	O
Intel	B-Device
Core	I-Device
i7	I-Device
,	O
which	O
was	O
released	O
in	O
November	O
2008	O
.	O
</s>
<s>
Server	B-Application
processors	O
of	O
the	O
Xeon	B-Device
55xx	O
range	O
were	O
first	O
supplied	O
to	O
testers	O
in	O
December	O
2008	O
.	O
</s>
<s>
The	O
performance	O
improvements	O
over	O
previous	O
Xeon	B-Device
processors	O
are	O
based	O
mainly	O
on	O
:	O
</s>
<s>
Integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
supporting	O
three	O
memory	O
channels	O
of	O
DDR3	O
SDRAM	O
.	O
</s>
<s>
A	O
new	O
point-to-point	O
processor	O
interconnect	O
QuickPath	B-Architecture
,	O
replacing	O
the	O
legacy	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
.	O
</s>
<s>
Gainestown	O
has	O
two	O
QuickPath	B-Architecture
interfaces	O
.	O
</s>
<s>
Hyper-threading	B-Operating_System
(	O
2×	O
per	O
core	B-Device
,	O
starting	O
from	O
5518	O
)	O
,	O
that	O
was	O
already	O
present	O
in	O
pre-Core	O
Duo	O
processors	O
.	O
</s>
<s>
Jasper	O
Forest	O
is	O
a	O
Nehalem-based	O
embedded	B-Architecture
processor	I-Architecture
with	O
PCI	O
Express	O
connections	O
on-die	O
,	O
core	B-Device
counts	O
from	O
1	O
to	O
4	O
cores	B-Architecture
and	O
power	O
envelopes	O
from	O
23	O
to	O
85	O
watts	O
.	O
</s>
<s>
The	O
uni-processor	O
version	O
without	O
QPI	B-Architecture
comes	O
as	O
LC35xx	O
and	O
EC35xx	O
,	O
while	O
the	O
dual-processor	O
version	O
is	O
sold	O
as	O
LC55xx	O
and	O
EC55xx	O
and	O
uses	O
QPI	B-Architecture
for	O
communication	O
between	O
the	O
processors	O
.	O
</s>
<s>
Both	O
versions	O
use	O
a	O
DMI	O
link	O
to	O
communicate	O
with	O
the	O
3420	O
that	O
is	O
also	O
used	O
in	O
the	O
3400-series	O
Lynfield	O
Xeon	B-Device
processors	O
,	O
but	O
use	O
an	O
LGA	B-Device
1366	I-Device
package	O
that	O
is	O
otherwise	O
used	O
for	O
processors	O
with	O
QPI	B-Architecture
but	O
no	O
DMI	O
or	O
PCI	O
Express	O
links	O
.	O
</s>
<s>
The	O
Celeron	B-Device
P1053	O
belongs	O
into	O
the	O
same	O
family	O
as	O
the	O
LC35xx	O
series	O
,	O
but	O
lacks	O
some	O
RAS	B-General_Concept
features	O
that	O
are	O
present	O
in	O
the	O
Xeon	B-Device
version	O
.	O
</s>
<s>
Gulftown	O
or	O
Westmere-EP	O
,	O
a	O
six-core	O
32nm	O
architecture	O
Westmere-based	O
processor	O
,	O
is	O
the	O
basis	O
for	O
the	O
Xeon	B-Device
36xx	O
and	O
56xx	O
series	O
and	O
the	O
Core	B-Device
i7-980X	O
.	O
</s>
<s>
Beckton	O
or	O
Nehalem-EX	O
(	O
EXpandable	O
server	B-Application
market	O
)	O
is	O
a	O
Nehalem-based	O
processor	O
with	O
up	O
to	O
eight	O
cores	B-Architecture
and	O
uses	O
buffering	O
inside	O
the	O
chipset	B-Device
to	O
support	O
up	O
to	O
16	O
standard	O
DDR3	O
DIMMS	O
per	O
CPU	O
socket	O
without	O
requiring	O
the	O
use	O
of	O
FB-DIMMS	O
.	O
</s>
<s>
Unlike	O
all	O
previous	O
Xeon	B-Device
MP	I-Device
processors	O
,	O
Nehalem-EX	O
uses	O
the	O
new	O
LGA	B-Device
1567	I-Device
package	O
,	O
replacing	O
the	O
Socket	B-Device
604	I-Device
used	O
in	O
the	O
previous	O
models	O
,	O
up	O
to	O
Xeon	B-Device
7400	O
"	O
Dunnington	O
"	O
.	O
</s>
<s>
The	O
75xx	O
models	O
have	O
four	O
QuickPath	B-Architecture
interfaces	O
,	O
so	O
it	O
can	O
be	O
used	O
in	O
up-to	O
eight-socket	O
configurations	O
,	O
while	O
the	O
65xx	O
models	O
are	O
only	O
for	O
up	O
to	O
two	O
sockets	O
.	O
</s>
<s>
Designed	O
by	O
the	O
Digital	O
Enterprise	O
Group	O
(	O
DEG	O
)	O
Santa	O
Clara	O
and	O
Hudson	O
Design	O
Teams	O
,	O
Beckton	O
is	O
manufactured	O
on	O
the	O
P1266	O
(	O
45nm	B-Algorithm
)	O
technology	O
.	O
</s>
<s>
Its	O
launch	O
in	O
March	O
2010	O
coincided	O
with	O
that	O
of	O
its	O
direct	O
competitor	O
,	O
AMD	O
's	O
Opteron	B-General_Concept
6xxx	O
"	O
Magny-Cours	O
"	O
.	O
</s>
<s>
Most	O
models	O
limit	O
the	O
number	O
of	O
cores	B-Architecture
and	O
QPI	B-Architecture
links	O
as	O
well	O
as	O
the	O
L3	O
Cache	B-General_Concept
size	O
in	O
order	O
to	O
get	O
a	O
broader	O
range	O
of	O
products	O
out	O
of	O
the	O
single	O
chip	O
design	O
.	O
</s>
<s>
Westmere-EX	O
is	O
the	O
follow-on	O
to	O
Beckton/Nehalem	O
-EX	O
and	O
the	O
first	O
Intel	O
Chip	O
to	O
have	O
ten	O
CPU	B-Architecture
cores	I-Architecture
.	O
</s>
<s>
The	O
microarchitecture	O
is	O
the	O
same	O
as	O
in	O
the	O
six-core	O
Gulftown/Westmere	O
-EP	O
processor	O
,	O
but	O
it	O
uses	O
the	O
LGA	B-Device
1567	I-Device
package	O
like	O
Beckton	O
to	O
support	O
up	O
to	O
eight	O
sockets	O
.	O
</s>
<s>
Starting	O
with	O
Westmere-EX	O
,	O
the	O
naming	O
scheme	O
has	O
changed	O
once	O
again	O
,	O
with	O
"	O
E7-xxxx	O
"	O
now	O
signifying	O
the	O
high-end	O
line	O
of	O
Xeon	B-Device
processors	O
using	O
a	O
package	O
that	O
supports	O
larger	O
than	O
two-CPU	O
configurations	O
,	O
formerly	O
the	O
7xxx	O
series	O
.	O
</s>
<s>
The	O
Xeon	B-Device
E3-12xx	O
line	O
of	O
processors	O
,	O
introduced	O
in	O
April	O
2011	O
,	O
uses	O
the	O
Sandy	B-Device
Bridge	I-Device
chips	O
that	O
are	O
also	O
the	O
base	O
for	O
the	O
Core	B-Device
i3/i5/i7	O
-2xxx	O
and	O
Celeron/Pentium	O
Gxxx	O
products	O
using	O
the	O
same	O
LGA	B-Device
1155	I-Device
socket	O
,	O
but	O
with	O
a	O
different	O
set	O
of	O
features	O
disabled	O
.	O
</s>
<s>
Notably	O
,	O
the	O
Xeon	B-Device
variants	O
include	O
support	O
for	O
ECC	B-General_Concept
memory	I-General_Concept
,	O
VT-d	O
and	O
trusted	B-Device
execution	I-Device
that	O
are	O
not	O
present	O
on	O
the	O
consumer	O
models	O
,	O
while	O
only	O
some	O
Xeon	B-Device
E3	O
enable	O
the	O
integrated	O
GPU	B-Application
that	O
is	O
present	O
on	O
Sandy	B-Device
Bridge	I-Device
.	O
</s>
<s>
Like	O
its	O
Xeon	B-Device
3400-series	O
predecessors	O
,	O
the	O
Xeon	B-Device
E3	O
only	O
supports	O
operation	O
with	O
a	O
single	O
CPU	O
socket	O
and	O
is	O
targeted	O
at	O
entry-level	O
workstations	B-Device
and	O
servers	O
.	O
</s>
<s>
Xeon	B-Device
E3-12xx	O
v2	O
is	O
a	O
minor	O
update	O
of	O
the	O
Sandy	O
Bridge-based	O
E3-12xx	O
,	O
using	O
the	O
22nm	O
shrink	O
,	O
and	O
providing	O
slightly	O
better	O
performance	O
while	O
remaining	O
backwards	O
compatible	O
.	O
</s>
<s>
They	O
were	O
released	O
in	O
May	O
2012	O
and	O
mirror	O
the	O
desktop	O
Core	B-Device
i3/i5/i7	O
-3xxx	O
parts	O
.	O
</s>
<s>
The	O
Xeon	B-Device
E5-16xx	O
processors	O
follow	O
the	O
previous	O
Xeon	B-Device
3500/3600	O
-series	O
products	O
as	O
the	O
high-end	O
single-socket	O
platform	O
,	O
using	O
the	O
LGA	B-Device
2011	I-Device
package	O
introduced	O
with	O
this	O
processor	O
.	O
</s>
<s>
The	O
CPU	B-Architecture
chips	I-Architecture
have	O
no	O
integrated	O
GPU	B-Application
but	O
eight	O
CPU	B-Architecture
cores	I-Architecture
,	O
some	O
of	O
which	O
are	O
disabled	O
in	O
the	O
entry-level	O
products	O
.	O
</s>
<s>
The	O
Xeon	B-Device
E5-26xx	O
line	O
has	O
the	O
same	O
features	O
but	O
also	O
enables	O
multi-socket	O
operation	O
like	O
the	O
earlier	O
Xeon	B-Device
5000-series	O
and	O
Xeon	B-Device
7000-series	O
processors	O
.	O
</s>
<s>
The	O
Xeon	B-Device
E5	O
v2	O
line	O
was	O
an	O
update	O
,	O
released	O
in	O
September	O
2013	O
to	O
replace	O
the	O
original	O
Xeon	B-Device
E5	O
processors	O
with	O
a	O
variant	O
based	O
on	O
the	O
Ivy	B-Device
Bridge	I-Device
shrink	O
.	O
</s>
<s>
The	O
maximum	O
number	O
of	O
CPU	B-Architecture
cores	I-Architecture
was	O
raised	O
to	O
12	O
per	O
processor	O
module	O
and	O
the	O
total	O
L3	O
cache	B-General_Concept
was	O
upped	O
to	O
30MB	O
.	O
</s>
<s>
The	O
consumer	O
version	O
of	O
the	O
Xeon	B-Device
E5-16xx	O
v2	O
processor	O
is	O
the	O
Core	O
i7-48xx	O
and	O
49xx	O
.	O
</s>
<s>
The	O
Xeon	B-Device
E7	O
v2	O
line	O
was	O
an	O
update	O
,	O
released	O
in	O
February	O
2014	O
to	O
replace	O
the	O
original	O
Xeon	B-Device
E7	O
processors	O
with	O
a	O
variant	O
based	O
on	O
the	O
Ivy	B-Device
Bridge	I-Device
shrink	O
.	O
</s>
<s>
There	O
was	O
no	O
Sandy	B-Device
Bridge	I-Device
version	O
of	O
these	O
processors	O
.	O
</s>
<s>
Introduced	O
in	O
May	O
2013	O
,	O
Xeon	B-Device
E3-12xx	O
v3	O
is	O
the	O
first	O
Xeon	B-Device
series	O
based	O
on	O
the	O
Haswell	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
It	O
uses	O
the	O
new	O
LGA	O
1150	O
socket	O
,	O
which	O
was	O
introduced	O
with	O
the	O
desktop	O
Core	O
i5/i7	O
Haswell	B-Device
processors	O
,	O
incompatible	O
with	O
the	O
LGA	B-Device
1155	I-Device
that	O
was	O
used	O
in	O
XeonE3	O
and	O
E3v2	O
.	O
</s>
<s>
As	O
before	O
,	O
the	O
main	O
difference	O
between	O
the	O
desktop	O
and	O
server	B-Application
versions	O
is	O
added	O
support	O
for	O
ECC	B-General_Concept
memory	I-General_Concept
in	O
the	O
Xeon-branded	O
parts	O
.	O
</s>
<s>
Introduced	O
in	O
September	O
2014	O
,	O
Xeon	B-Device
E5-16xx	O
v3	O
and	O
Xeon	B-Device
E5-26xx	O
v3	O
series	O
use	O
the	O
new	O
LGA	O
2011-v3	O
socket	O
,	O
which	O
is	O
incompatible	O
with	O
the	O
LGA2011	B-Device
socket	O
used	O
by	O
earlier	O
XeonE5	O
and	O
E5v2	O
generations	O
based	O
on	O
Sandy	B-Device
Bridge	I-Device
and	O
Ivy	B-Device
Bridge	I-Device
microarchitectures	O
.	O
</s>
<s>
Some	O
of	O
the	O
main	O
benefits	O
of	O
this	O
generation	O
,	O
compared	O
to	O
the	O
previous	O
one	O
,	O
are	O
improved	O
power	O
efficiency	O
,	O
higher	O
core	B-Device
counts	O
,	O
and	O
bigger	O
last	O
level	O
caches	B-General_Concept
(	O
LLCs	O
)	O
.	O
</s>
<s>
Following	O
the	O
already	O
used	O
nomenclature	O
,	O
Xeon	B-Device
E5-26xx	O
v3	O
series	O
allows	O
dual-socket	O
operation	O
.	O
</s>
<s>
One	O
of	O
the	O
new	O
features	O
of	O
this	O
generation	O
is	O
that	O
Xeon	B-Device
E5v3	O
models	O
with	O
more	O
than	O
10	O
cores	B-Architecture
support	O
cluster	O
on	O
die	O
(	O
COD	O
)	O
operation	O
mode	O
,	O
allowing	O
CPU	O
's	O
multiple	O
columns	O
of	O
cores	B-Architecture
and	O
LLC	O
slices	O
to	O
be	O
logically	O
divided	O
into	O
what	O
is	O
presented	O
as	O
two	O
non-uniform	B-Operating_System
memory	I-Operating_System
access	I-Operating_System
(	O
NUMA	O
)	O
CPUs	O
to	O
the	O
operating	O
system	O
.	O
</s>
<s>
Introduced	O
in	O
May	O
2015	O
,	O
Xeon	B-Device
E7-48xx	O
v3	O
and	O
Xeon	B-Device
E7-88xx	O
v3	O
series	O
provide	O
higher	O
core	B-Device
counts	O
,	O
higher	O
per-core	O
performance	O
and	O
improved	O
reliability	O
features	O
,	O
compared	O
to	O
the	O
previous	O
Xeon	B-Device
E7v2	O
generation	O
.	O
</s>
<s>
Following	O
the	O
usual	O
SKU	O
nomenclature	O
,	O
Xeon	B-Device
E7-48xxv3	O
and	O
E7-88xxv3	O
series	O
allow	O
multi-socket	O
operation	O
,	O
supporting	O
up	O
to	O
quad	O
-	O
and	O
eight-socket	O
configurations	O
,	O
respectively	O
.	O
</s>
<s>
These	O
processors	O
use	O
the	O
LGA2011	B-Device
(	O
R1	O
)	O
socket	O
.	O
</s>
<s>
Xeon	B-Device
E7-48xxv3	O
and	O
E7-88xxv3	O
series	O
contain	O
a	O
quad-channel	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
(	O
IMC	O
)	O
,	O
supporting	O
both	O
DDR3	O
and	O
DDR4	O
LRDIMM	O
or	O
RDIMM	B-General_Concept
memory	O
modules	O
through	O
the	O
use	O
of	O
Jordan	O
Creek	O
(	O
DDR3	O
)	O
or	O
Jordan	O
Creek	O
2	O
(	O
DDR4	O
)	O
memory	O
buffer	O
chips	O
.	O
</s>
<s>
Xeon	B-Device
E7-48xxv3	O
and	O
E7-88xxv3	O
series	O
also	O
contain	O
functional	O
bug-free	O
support	O
for	O
Transactional	B-Operating_System
Synchronization	I-Operating_System
Extensions	I-Operating_System
(	O
TSX	O
)	O
,	O
which	O
was	O
disabled	O
via	O
a	O
microcode	B-Device
update	O
in	O
August	O
2014	O
for	O
Haswell-E	O
,	O
Haswell-WS	O
(	O
E3-12xx	O
v3	O
)	O
and	O
Haswell-EP	O
(	O
E5-16xx/26xx	O
v3	O
)	O
models	O
,	O
due	O
to	O
a	O
bug	O
that	O
was	O
discovered	O
in	O
the	O
TSX	O
implementation	O
.	O
</s>
<s>
Introduced	O
in	O
June	O
2015	O
,	O
Xeon	B-Device
E3-12xx	O
v4	O
is	O
the	O
first	O
Xeon	B-Device
series	O
based	O
on	O
the	O
Broadwell	B-General_Concept
micro	O
architecture	O
.	O
</s>
<s>
It	O
uses	O
LGA	O
1150	O
socket	O
,	O
which	O
was	O
introduced	O
with	O
the	O
desktop	O
Core	O
i5/i7	O
Haswell	B-Device
processors	O
.	O
</s>
<s>
As	O
before	O
,	O
the	O
main	O
difference	O
between	O
the	O
desktop	O
and	O
server	B-Application
versions	O
is	O
added	O
support	O
for	O
ECC	B-General_Concept
memory	I-General_Concept
in	O
the	O
Xeon-branded	O
parts	O
.	O
</s>
<s>
Introduced	O
in	O
October	O
2015	O
,	O
Xeon	B-Device
E3-12xx	O
v5	O
is	O
the	O
first	O
Xeon	B-Device
series	O
based	O
on	O
the	O
Skylake	B-Architecture
microarchitecture	I-Architecture
.	O
</s>
<s>
It	O
uses	O
new	O
LGA	O
1151	O
socket	O
,	O
which	O
was	O
introduced	O
with	O
the	O
desktop	O
Core	O
i5/i7	O
Skylake	B-Architecture
processors	O
.	O
</s>
<s>
Although	O
it	O
uses	O
the	O
same	O
socket	O
as	O
consumer	O
processors	O
,	O
it	O
is	O
limited	O
to	O
the	O
C200	O
server	B-Application
chipset	B-Device
series	O
and	O
will	O
not	O
work	O
with	O
consumer	O
chipsets	B-Device
like	O
Z170	O
.	O
</s>
<s>
As	O
before	O
,	O
the	O
main	O
difference	O
between	O
the	O
desktop	O
and	O
server	B-Application
versions	O
is	O
added	O
support	O
for	O
ECC	B-General_Concept
memory	I-General_Concept
in	O
the	O
Xeon-branded	O
parts	O
.	O
</s>
<s>
Introduced	O
in	O
January	O
2017	O
,	O
Xeon	B-Device
E3-12xx	O
v6	O
is	O
the	O
first	O
Xeon	B-Device
series	O
based	O
on	O
the	O
Kaby	O
Lake	O
microarchitecture	O
.	O
</s>
<s>
It	O
uses	O
the	O
same	O
LGA	O
1151	O
socket	O
,	O
which	O
was	O
introduced	O
with	O
the	O
desktop	O
Core	O
i5/i7	O
Skylake	B-Architecture
processors	O
.	O
</s>
<s>
As	O
before	O
,	O
the	O
main	O
difference	O
between	O
the	O
desktop	O
and	O
server	B-Application
versions	O
is	O
added	O
support	O
for	O
ECC	B-General_Concept
memory	I-General_Concept
and	O
improved	O
energy	O
efficiency	O
in	O
the	O
Xeon-branded	O
parts	O
.	O
</s>
<s>
(	O
Threads	B-Operating_System
)	O
Base	O
CPUclock	O
rate	O
Max	O
.	O
</s>
<s>
(	O
Threads	B-Operating_System
)	O
Base	O
CPUclock	O
rate	O
Max	O
.	O
</s>
<s>
By	O
2013	O
Xeon	B-Device
processors	O
were	O
ubiquitous	O
in	O
supercomputers	O
—	O
more	O
than	O
80%	O
of	O
the	O
TOP500	B-Operating_System
machines	O
in	O
2013	O
used	O
them	O
.	O
</s>
<s>
For	O
the	O
fastest	O
machines	O
,	O
much	O
of	O
the	O
performance	O
comes	O
from	O
compute	O
accelerators	O
;	O
Intel	O
's	O
entry	O
into	O
that	O
market	O
was	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
,	O
the	O
first	O
machines	O
using	O
it	O
appeared	O
in	O
June	O
2012	O
and	O
by	O
June	O
2013	O
it	O
was	O
used	O
in	O
the	O
fastest	B-Operating_System
computer	I-Operating_System
in	O
the	O
world	O
.	O
</s>
<s>
The	O
first	O
Xeon-based	O
machines	O
in	O
the	O
top-10	O
appeared	O
in	O
November	O
2002	O
,	O
two	O
clusters	O
at	O
Lawrence	O
Livermore	O
National	O
Laboratory	O
and	O
at	O
NOAA	O
.	O
</s>
<s>
The	O
first	O
Xeon-based	O
machine	O
to	O
be	O
in	O
the	O
first	O
place	O
of	O
the	O
TOP500	B-Operating_System
was	O
the	O
Chinese	O
Tianhe-IA	B-Device
in	O
November	O
2010	O
,	O
which	O
used	O
a	O
mixed	O
Xeon-Nvidia	O
GPU	B-Application
configuration	O
;	O
it	O
was	O
overtaken	O
by	O
the	O
Japanese	O
K	B-Device
computer	I-Device
in	O
2012	O
,	O
but	O
the	O
Tianhe-2	B-Device
system	O
using	O
12-core	O
Xeon	B-Device
E5-2692	O
processors	O
and	O
Xeon	B-General_Concept
Phi	I-General_Concept
cards	O
occupied	O
the	O
first	O
place	O
in	O
both	O
TOP500	B-Operating_System
lists	O
of	O
2013	O
.	O
</s>
<s>
Xeon	B-Device
processor-based	O
systems	O
are	O
among	O
the	O
top	O
20	O
fastest	O
systems	O
by	O
memory	O
bandwidth	O
as	O
measured	O
by	O
the	O
STREAM	O
benchmark	O
.	O
</s>
<s>
An	O
Intel	B-Device
Xeon	I-Device
virtual	O
SMP	B-Operating_System
system	O
using	O
ScaleMP	O
's	O
Versatile	O
SMP	B-Operating_System
(	O
vSMP	O
)	O
architecture	O
with	O
128	O
cores	B-Architecture
and	O
1TiB	O
RAM	O
.	O
</s>
<s>
This	O
system	O
aggregates	O
16	O
Stoakley	O
platform	O
(	O
Seaburg	O
chipset	B-Device
)	O
systems	O
with	O
total	O
of	O
32	O
Harpertown	O
processors	O
.	O
</s>
