<s>
The	O
Xenos	B-Device
is	O
a	O
custom	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
designed	O
by	O
ATI	O
(	O
now	O
taken	O
over	O
by	O
AMD	O
)	O
,	O
used	O
in	O
the	B-Operating_System
Xbox	I-Operating_System
360	I-Operating_System
video	B-Device
game	I-Device
console	I-Device
developed	O
and	O
produced	O
for	O
Microsoft	O
.	O
</s>
<s>
Developed	O
under	O
the	O
codename	O
"	O
C1	O
"	O
,	O
it	O
is	O
in	O
many	O
ways	O
related	O
to	O
the	O
R520	B-Device
architecture	O
and	O
therefore	O
very	O
similar	O
to	O
an	O
ATI	B-Device
Radeon	I-Device
X1800	B-Device
XT	O
series	O
of	O
PC	O
graphics	B-Device
cards	I-Device
as	O
far	O
as	O
features	O
and	O
performance	O
are	O
concerned	O
.	O
</s>
<s>
However	O
,	O
the	O
Xenos	B-Device
introduced	O
new	O
design	O
ideas	O
that	O
were	O
later	O
adopted	O
in	O
the	O
TeraScale	B-Architecture
microarchitecture	I-Architecture
,	O
such	O
as	O
the	O
unified	O
shader	O
architecture	O
.	O
</s>
<s>
The	O
package	O
contains	O
two	O
separate	O
dies	O
,	O
the	O
GPU	B-Architecture
and	O
an	O
eDRAM	O
(	O
manufactured	O
by	O
NEC	O
)	O
,	O
featuring	O
a	O
total	O
of	O
337	O
million	O
transistors	O
.	O
</s>
<s>
The	O
chip	O
is	O
based	O
on	O
TeraScale	B-Architecture
microarchitecture	I-Architecture
,	O
the	O
shader	O
units	O
are	O
organized	O
in	O
three	O
SIMD	B-Device
groups	O
with	O
16	O
processors	O
per	O
group	O
,	O
for	O
a	O
total	O
of	O
48	O
processors	O
.	O
</s>
<s>
Each	O
of	O
these	O
processors	O
is	O
composed	O
of	O
a	O
5-wide	O
vector	O
unit	O
(	O
total	O
5	O
FP32	O
ALUs	B-General_Concept
)	O
,	O
resulting	O
in	O
240	O
units	O
,	O
that	O
can	O
serially	O
execute	O
up	O
to	O
two	O
instructions	O
per	O
cycle	O
(	O
a	O
multiply	O
and	O
an	O
addition	O
)	O
.	O
</s>
<s>
All	O
processors	O
in	O
a	O
SIMD	B-Device
group	O
execute	O
the	O
same	O
instruction	O
,	O
so	O
in	O
total	O
up	O
to	O
three	O
instruction	O
threads	O
can	O
be	O
simultaneously	O
under	O
execution	O
.	O
</s>
<s>
240	O
vector	O
units	O
floating-point	B-Algorithm
vector	O
processors	O
for	O
shader	O
execution	O
,	O
divided	O
in	O
three	O
dynamically	O
scheduled	O
SIMD	B-Device
groups	O
of	O
80	O
units	O
each	O
.	O
</s>
<s>
NEC	O
designed	O
eDRAM	O
die	O
includes	O
additional	O
logic	O
(	O
192	O
parallel	O
pixel	B-Algorithm
processors	O
)	O
for	O
color	O
,	O
alpha	B-Algorithm
compositing	I-Algorithm
,	O
alpha	B-Algorithm
blending	I-Algorithm
,	O
Z/stencil	O
buffering	O
,	O
and	O
anti-aliasing	B-Algorithm
called	O
"	O
Intelligent	O
Memory	O
"	O
,	O
giving	O
developers	O
4-sample	O
anti-aliasing	B-Algorithm
at	O
very	O
little	O
performance	O
cost	O
.	O
</s>
<s>
Procedural	O
Synthesis	O
Technology	O
(	O
XPS	O
)	O
:	O
During	O
read	O
streaming	O
into	O
the	O
CPU	B-Device
,	O
a	O
custom	O
prefetch	O
instruction	O
,	O
extended	O
data	O
cache	O
block	O
touch	O
(	O
xDCBT	O
)	O
prefetches	B-General_Concept
data	O
directly	O
to	O
the	O
L1	O
data	O
cache	O
of	O
the	O
intended	O
core	O
,	O
which	O
skips	O
putting	O
the	O
data	O
in	O
the	O
L2	O
cache	O
to	O
avoid	O
thrashing	O
the	O
L2	O
cache	O
.	O
</s>
<s>
The	O
system	O
allows	O
for	O
the	O
GPU	B-Architecture
to	O
directly	O
read	O
data	O
produced	O
by	O
the	O
CPU	B-Device
without	O
going	O
to	O
main	O
memory	O
.	O
</s>
<s>
In	O
this	O
specific	O
case	O
of	O
data	O
streaming	O
,	O
called	O
Xbox	B-Operating_System
procedural	O
synthesis	O
(	O
XPS	O
)	O
,	O
the	O
CPU	B-Device
is	O
effectively	O
a	O
data	O
decompressor	O
,	O
generating	O
geometry	O
on-the-fly	O
for	O
consumption	O
by	O
the	O
GPU	B-Architecture
3D	O
core	O
.	O
</s>
<s>
Cooling	B-General_Concept
:	O
Both	O
the	O
GPU	B-Architecture
and	O
CPU	B-Device
of	O
the	O
console	O
have	O
heatsinks	O
.	O
</s>
<s>
The	O
GPU	B-Architecture
's	O
heatsink	O
uses	O
heatpipe	O
technology	O
,	O
to	O
conduct	O
heat	O
from	O
the	O
GPU	B-Architecture
and	O
eDRAM	O
die	O
to	O
the	O
fins	O
of	O
the	O
heatsink	O
.	O
</s>
<s>
The	O
new	O
XCGPU	O
chipset	O
redesign	O
is	O
featured	O
in	O
both	O
the	B-Operating_System
Xbox	I-Operating_System
360	I-Operating_System
S	O
and	O
the	B-Operating_System
Xbox	I-Operating_System
360	I-Operating_System
E	O
and	O
integrates	O
the	O
CPU	B-Device
(	O
Xenon	B-Device
)	O
and	O
GPU	B-Architecture
(	O
Xenos	B-Device
)	O
in	O
one	O
package	O
and	O
is	O
actively	O
cooled	O
by	O
a	O
single	O
heatsink	O
rather	O
than	O
two	O
.	O
</s>
