<s>
The	O
XOP	O
(	O
eXtended	O
Operations	O
)	O
instruction	B-General_Concept
set	I-General_Concept
,	O
announced	O
by	O
AMD	O
on	O
May	O
1	O
,	O
2009	O
,	O
is	O
an	O
extension	O
to	O
the	O
128-bit	O
SSE	B-General_Concept
core	O
instructions	O
in	O
the	O
x86	B-Operating_System
and	O
AMD64	B-Device
instruction	B-General_Concept
set	I-General_Concept
for	O
the	O
Bulldozer	O
processor	O
core	O
,	O
which	O
was	O
released	O
on	O
October	O
12	O
,	O
2011	O
.	O
</s>
<s>
The	O
XOP	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
contains	O
several	O
different	O
types	O
of	O
vector	O
instructions	O
since	O
it	O
was	O
originally	O
intended	O
as	O
a	O
major	O
upgrade	O
to	O
SSE	B-General_Concept
.	O
</s>
<s>
XOP	O
is	O
a	O
revised	O
subset	O
of	O
what	O
was	O
originally	O
intended	O
as	O
SSE5	B-General_Concept
.	O
</s>
<s>
It	O
was	O
changed	O
to	O
be	O
similar	O
but	O
not	O
overlapping	O
with	O
AVX	B-General_Concept
,	O
parts	O
that	O
overlapped	O
with	O
AVX	B-General_Concept
were	O
removed	O
or	O
moved	O
to	O
separate	O
standards	O
such	O
as	O
FMA4	B-General_Concept
(	O
floating-point	O
vector	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
)	O
and	O
CVT16	B-Device
(	O
Half-precision	O
floating-point	O
conversion	O
implemented	O
as	O
F16C	B-Device
by	O
Intel	O
)	O
.	O
</s>
<s>
All	O
SSE5	B-General_Concept
instructions	O
that	O
were	O
equivalent	O
or	O
similar	O
to	O
instructions	O
in	O
the	O
AVX	B-General_Concept
and	O
FMA4	B-General_Concept
instruction	I-General_Concept
sets	I-General_Concept
announced	O
by	O
Intel	O
have	O
been	O
changed	O
to	O
use	O
the	O
coding	O
proposed	O
by	O
Intel	O
.	O
</s>
<s>
Integer	O
instructions	O
equivalents	O
in	O
AVX	B-General_Concept
were	O
classified	O
as	O
the	O
XOP	O
extension	O
.	O
</s>
<s>
The	O
XOP	O
instructions	O
have	O
an	O
opcode	O
byte	O
8F	O
(	O
hexadecimal	O
)	O
,	O
but	O
otherwise	O
almost	O
identical	O
coding	O
scheme	O
as	O
AVX	B-General_Concept
with	O
the	O
3-byte	O
VEX	B-General_Concept
prefix	I-General_Concept
.	O
</s>
<s>
The	O
use	O
of	O
the	O
8F	O
byte	O
requires	O
that	O
the	O
m-bits	O
(	O
see	O
VEX	B-General_Concept
coding	I-General_Concept
scheme	I-General_Concept
)	O
have	O
a	O
value	O
larger	O
than	O
or	O
equal	O
to	O
8	O
in	O
order	O
to	O
avoid	O
overlap	O
with	O
existing	O
instructions	O
.	O
</s>
<s>
A	O
similar	O
compatibility	O
issue	O
is	O
the	O
difference	O
between	O
the	O
FMA3	B-General_Concept
and	I-General_Concept
FMA4	I-General_Concept
instruction	B-General_Concept
sets	I-General_Concept
.	O
</s>
<s>
Intel	O
initially	O
proposed	O
FMA4	B-General_Concept
in	O
AVX/FMA	O
specification	O
version	O
3	O
to	O
supersede	O
the	O
3-operand	O
FMA	O
proposed	O
by	O
AMD	O
in	O
SSE5	B-General_Concept
.	O
</s>
<s>
After	O
AMD	O
adopted	O
FMA4	B-General_Concept
,	O
Intel	O
canceled	O
FMA4	B-General_Concept
support	O
and	O
reverted	O
to	O
FMA3	B-General_Concept
in	O
the	O
AVX/FMA	O
specification	O
version	O
5	O
(	O
See	O
FMA	O
history	O
)	O
.	O
</s>
<s>
In	O
March	O
2015	O
,	O
AMD	O
explicitly	O
revealed	O
in	O
the	O
description	O
of	O
the	O
patch	O
for	O
the	O
GNU	O
Binutils	O
package	O
that	O
Zen	O
,	O
its	O
third-generation	O
x86-64	B-Device
architecture	O
in	O
its	O
first	O
iteration	O
(	O
znver1	O
–	O
Zen	O
,	O
version	O
1	O
)	O
,	O
will	O
not	O
support	O
TBM	O
,	O
FMA4	B-General_Concept
,	O
XOP	O
and	O
LWP	O
instructions	O
developed	O
specifically	O
for	O
the	O
"	O
Bulldozer	O
"	O
family	O
of	O
micro-architectures	O
.	O
</s>
<s>
These	O
are	O
integer	O
version	O
of	O
the	O
FMA	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
.	O
</s>
<s>
These	O
are	O
all	O
four	O
operand	O
instructions	O
similar	O
to	O
FMA4	B-General_Concept
and	O
they	O
all	O
operate	O
on	O
signed	O
integers	O
.	O
</s>
<s>
Six	O
additional	O
horizontal	O
addition	O
and	O
subtraction	O
instructions	O
can	O
be	O
found	O
in	O
SSSE3	B-General_Concept
,	O
but	O
they	O
operate	O
on	O
two	O
input	O
vectors	O
and	O
only	O
does	O
two	O
and	O
two	O
operations	O
.	O
</s>
<s>
This	O
result	O
can	O
be	O
used	O
directly	O
in	O
VPCMOV	O
instruction	O
for	O
a	O
vectorized	O
conditional	B-General_Concept
move	I-General_Concept
.	O
</s>
<s>
VPCMOV	O
works	O
as	O
bitwise	O
variant	O
of	O
the	O
blend	O
instructions	O
in	O
SSE4	B-General_Concept
.	O
</s>
<s>
When	O
used	O
together	O
with	O
the	O
XOP	O
vector	O
comparison	O
instructions	O
above	O
this	O
can	O
be	O
used	O
to	O
implement	O
a	O
vectorized	O
ternary	O
move	O
,	O
or	O
if	O
the	O
second	O
input	O
is	O
the	O
same	O
as	O
the	O
destination	O
,	O
a	O
conditional	B-General_Concept
move	I-General_Concept
(	O
CMOV	O
)	O
.	O
</s>
<s>
The	O
shift	O
instructions	O
here	O
differ	O
from	O
those	O
in	O
SSE2	B-General_Concept
in	O
that	O
they	O
can	O
shift	O
each	O
unit	O
with	O
a	O
different	O
amount	O
using	O
a	O
vector	O
register	O
interpreted	O
as	O
packed	O
signed	O
integers	O
.	O
</s>
<s>
VPPERM	O
is	O
a	O
single	O
instruction	O
that	O
combines	O
the	O
SSSE3	B-General_Concept
instruction	O
PALIGNR	O
and	O
PSHUFB	O
and	O
adds	O
more	O
to	O
both	O
.	O
</s>
<s>
Some	O
compare	O
it	O
the	O
Altivec	B-General_Concept
instruction	O
VPERM	O
.	O
</s>
<s>
The	O
VPERMIL2PD	O
and	O
VPERMIL2PS	O
instructions	O
are	O
two	O
source	O
versions	O
of	O
the	O
VPERMILPD	O
and	O
VPERMILPS	O
instructions	O
in	O
AVX	B-General_Concept
which	O
means	O
like	O
VPPERM	O
they	O
can	O
select	O
output	O
from	O
any	O
of	O
the	O
fields	O
in	O
the	O
two	O
inputs	O
.	O
</s>
