<s>
The	O
XAP	B-Device
processor	I-Device
is	O
a	O
RISC	B-Architecture
processor	I-Architecture
architecture	O
developed	O
by	O
Cambridge	O
Consultants	O
since	O
1994	O
.	O
</s>
<s>
XAP	B-Device
processors	I-Device
are	O
a	O
family	O
of	O
16-bit	B-Device
and	O
32-bit	O
cores	O
,	O
all	O
of	O
which	O
are	O
intended	O
for	O
use	O
in	O
an	O
application-specific	O
integrated	O
circuit	O
or	O
ASIC	O
chip	O
design	O
.	O
</s>
<s>
XAP	B-Device
processors	I-Device
were	O
designed	O
for	O
use	O
in	O
mixed-signal	O
integrated	O
circuits	O
for	O
sensor	O
or	O
wireless	O
applications	O
including	O
Bluetooth	B-Protocol
,	O
Zigbee	B-Protocol
,	O
GPS	O
,	O
RFID	B-Application
or	O
Near	O
Field	O
Communication	O
chips	O
.	O
</s>
<s>
There	O
are	O
other	O
applications	O
where	O
XAP	B-Device
processors	I-Device
have	O
been	O
used	O
to	O
good	O
effect	O
,	O
such	O
as	O
wireless	B-Architecture
sensor	I-Architecture
networks	I-Architecture
and	O
medical	O
devices	O
,	O
e.g.	O
</s>
<s>
The	O
XAP	O
soft	B-Device
microprocessor	I-Device
has	O
been	O
implemented	O
in	O
several	O
on-chip	O
design	O
styles	O
,	O
including	O
self-timed	O
asynchronous	B-Application
circuit	I-Application
,	O
</s>
<s>
fully	O
synchronous	B-Application
circuit	I-Application
,	O
</s>
<s>
The	O
first	O
XAP	B-Device
processor	I-Device
was	O
XAP1	O
,	O
designed	O
in	O
1994	O
and	O
used	O
for	O
a	O
number	O
of	O
wireless	O
and	O
sensor	O
ASIC	O
projects	O
at	O
Cambridge	O
Consultants	O
.	O
</s>
<s>
It	O
was	O
a	O
very	O
small	O
,	O
3,000	O
-gate	O
,	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
16-bit	B-Device
processor	I-Device
with	O
a	O
16-bit	B-Device
data	B-General_Concept
bus	I-General_Concept
and	O
an	O
18-bit	O
instruction	B-General_Concept
bus	I-General_Concept
intended	O
for	O
running	O
programs	O
stored	O
in	O
on-chip	O
read-only	B-Device
memory	I-Device
or	O
ROM	B-Device
.	O
</s>
<s>
Data	O
and	O
instructions	O
were	O
each	O
addressed	O
by	O
separate	O
16-bit	B-Device
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
It	O
also	O
had	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
and	O
16-bit	B-Device
data	O
,	O
and	O
it	O
adopted	O
a	O
more	O
conventional	O
16-bit	B-Device
instruction	B-General_Concept
width	I-General_Concept
suitable	O
for	O
program	O
storage	O
in	O
Flash	B-Device
or	O
other	O
off-chip	O
memories	O
.	O
</s>
<s>
Large	O
programs	O
were	O
accommodated	O
by	O
a	O
24-bit	O
address	B-Architecture
bus	I-Architecture
for	O
instructions	O
and	O
there	O
was	O
a	O
16-bit	B-Device
address	B-Architecture
bus	I-Architecture
for	O
data	O
.	O
</s>
<s>
XAP2	O
was	O
a	O
12,000	O
-gate	O
processor	B-General_Concept
with	O
support	O
for	O
interrupts	B-Application
and	O
a	O
software	O
tool	O
chain	O
including	O
a	O
C	B-Language
compiler	B-Language
and	O
the	O
XAPASM	O
assembler	B-Language
for	O
its	O
assembly	B-Language
language	I-Language
.	O
</s>
<s>
XAP2	O
was	O
also	O
used	O
in	O
Cambridge	O
Consultants	O
 '	O
ASIC	O
designs	O
,	O
and	O
it	O
was	O
also	O
provided	O
to	O
other	O
semiconductor	O
companies	O
as	O
a	O
semiconductor	B-Architecture
intellectual	I-Architecture
property	I-Architecture
core	I-Architecture
,	O
or	O
IP	B-Architecture
core	I-Architecture
.	O
</s>
<s>
XAP2	O
was	O
adopted	O
by	O
three	O
fabless	B-Algorithm
semiconductor	I-Algorithm
companies	I-Algorithm
that	O
emerged	O
from	O
Cambridge	O
Consultants	O
:	O
CSR	O
plc	O
(	O
Cambridge	O
Silicon	O
Radio	O
)	O
is	O
the	O
main	O
provider	O
of	O
Bluetooth	B-Protocol
chips	O
for	O
mobile	O
phones	O
and	O
headsets	O
;	O
Ember	O
Corporation	O
is	O
a	O
leading	O
supplier	O
of	O
Zigbee	B-Protocol
chips	O
;	O
and	O
Cyan	O
Technology	O
supplies	O
XAP2-powered	O
microcontrollers	B-Architecture
.	O
</s>
<s>
As	O
a	O
consequence	O
and	O
combined	O
with	O
other	O
licensees	O
and	O
Cambridge	O
Consultants’	O
ASIC	O
projects	O
,	O
there	O
are	O
now	O
over	O
one	O
billion	O
(	O
1,000	O
million	O
)	O
XAP	B-Device
processors	I-Device
in	O
use	O
worldwide	O
.	O
</s>
<s>
XAP3	O
was	O
an	O
experimental	O
32-bit	O
processor	B-General_Concept
designed	O
at	O
Cambridge	O
Consultants	O
in	O
2003	O
.	O
</s>
<s>
It	O
was	O
optimised	O
for	O
low	O
cost	O
,	O
low	O
energy	O
ASIC	O
implementations	O
using	O
modern	O
CMOS	B-Device
semiconductor	O
process	O
technologies	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
was	O
optimised	O
for	O
GNU	O
GCC	O
to	O
achieve	O
high	O
code	O
density	O
.	O
</s>
<s>
The	O
XAP3	O
was	O
the	O
first	O
of	O
Cambridge	O
Consultants’	O
processors	O
to	O
use	O
a	O
Von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
with	O
a	O
logically	O
shared	O
address	O
space	O
for	O
Program	O
and	O
Data	O
.	O
</s>
<s>
The	O
physical	O
program	B-Device
memory	I-Device
could	O
be	O
Flash	B-Device
or	O
one-time	O
programmable	O
EPROM	B-General_Concept
or	O
SRAM	O
.	O
</s>
<s>
The	O
XAP3	O
's	O
instruction	B-General_Concept
set	I-General_Concept
with	O
the	O
GCC	O
compiler	B-Language
produced	O
very	O
high	O
code	O
density	O
.	O
</s>
<s>
This	O
reduced	O
the	O
size	O
of	O
the	O
program	B-Device
memory	I-Device
,	O
which	O
reduced	O
the	O
chip	O
unit	O
cost	O
and	O
reduced	O
the	O
energy	O
consumption	O
.	O
</s>
<s>
In	O
2005	O
,	O
further	O
project	O
requirements	O
saw	O
a	O
new	O
16-bit	B-Device
processor	I-Device
,	O
the	O
XAP4	O
,	O
designed	O
to	O
supersede	O
the	O
XAP2	O
taking	O
into	O
account	O
the	O
experience	O
gained	O
on	O
XAP3	O
and	O
the	O
evolving	O
requirements	O
of	O
ASIC	O
designs	O
.	O
</s>
<s>
XAP4	O
is	O
a	O
very	O
small	O
,	O
12,000	O
-gate	O
,	O
Von	B-Architecture
Neumann	I-Architecture
bus	I-Architecture
,	O
16-bit	B-Device
processor	I-Device
core	O
capable	O
of	O
addressing	O
a	O
total	O
of	O
64Kbytes	O
of	O
memory	O
for	O
programs	O
,	O
data	O
and	O
peripherals	O
.	O
</s>
<s>
XAP4	O
was	O
designed	O
for	O
use	O
in	O
modern	O
ASIC	O
or	O
microcontroller	B-Architecture
applications	O
capable	O
of	O
processing	O
real-world	O
data	O
captured	O
by	O
an	O
analog-to-digital	O
converter	O
(	O
ADC	O
)	O
or	O
similar	O
sources	O
.	O
</s>
<s>
The	O
processor	B-General_Concept
's	O
16-bit	B-Device
integer	O
word	O
supports	O
the	O
precision	O
of	O
most	O
ADCs	O
without	O
carrying	O
the	O
overhead	O
of	O
a	O
32-bit	O
processor	B-General_Concept
.	O
</s>
<s>
XAP4	O
also	O
offers	O
a	O
migration	O
path	O
from	O
8-bit	O
processors	O
,	O
such	O
as	O
8051	B-Architecture
,	O
in	O
applications	O
that	O
need	O
increased	O
performance	O
and	O
program	O
size	O
,	O
but	O
cannot	O
justify	O
the	O
cost	O
and	O
overhead	O
of	O
a	O
32-bit	O
processor	B-General_Concept
.	O
</s>
<s>
The	O
XAP4	O
registers	O
(	O
all	O
16-bit	B-Device
)	O
are	O
;	O
8	O
General	O
Purpose	O
,	O
Program	O
Counter	O
,	O
Vector	O
Pointer	O
,	O
FLAGS	O
,	O
INFO	O
,	O
BRKE	O
,	O
2	O
Breakpoint	O
.	O
</s>
<s>
The	O
XAP4	O
compile	B-Language
chain	O
is	O
based	O
on	O
GNU	O
GCC	O
and	O
Binutils	O
.	O
</s>
<s>
XAP5	O
is	O
a	O
16-bit	B-Device
processor	I-Device
with	O
a	O
24-bit	O
address	B-Architecture
bus	I-Architecture
making	O
it	O
capable	O
of	O
running	O
programs	O
from	O
memory	O
up	O
to	O
16	O
MBytes	O
.	O
</s>
<s>
XAP4	O
and	O
XAP5	O
are	O
both	O
implemented	O
with	O
a	O
two-stage	O
instruction	B-General_Concept
pipeline	I-General_Concept
,	O
which	O
maximises	O
their	O
performance	O
when	O
clocked	O
at	O
low	O
frequencies	O
.	O
</s>
<s>
This	O
is	O
tailored	O
to	O
the	O
requirements	O
of	O
small	O
,	O
low-energy	O
ASICs	O
as	O
it	O
minimises	O
processor	B-General_Concept
hardware	O
size	O
(	O
the	O
XAP5	O
core	O
uses	O
18,000	O
-gates	O
)	O
,	O
and	O
it	O
fits	O
designs	O
that	O
are	O
clocked	O
relatively	O
slowly	O
to	O
reduce	O
an	O
ASIC	O
's	O
dynamic	O
power	O
consumption	O
and	O
run	O
programs	O
direct	O
from	O
Flash	B-Device
or	O
OTP	O
memory	O
that	O
has	O
a	O
slow	O
access	O
time	O
.	O
</s>
<s>
Typical	O
clock	O
speeds	O
for	O
XAP5	O
are	O
in	O
the	O
range	O
of	O
16	O
to	O
100MHz	O
on	O
a	O
0.13	B-Algorithm
process	I-Algorithm
.	O
</s>
<s>
XAP5	O
has	O
particular	O
design	O
features	O
making	O
it	O
suitable	O
for	O
executing	O
programs	O
from	O
Flash	B-Device
including	O
a	O
Vector	O
Pointer	O
and	O
an	O
Address	O
Translation	O
Window	O
,	O
which	O
combine	O
to	O
allow	O
in-place	O
execution	O
of	O
programs	O
and	O
relocation	O
of	O
programs	O
regardless	O
of	O
where	O
they	O
are	O
stored	O
in	O
physical	O
memory	O
.	O
</s>
<s>
The	O
XAP5	O
compile	B-Language
chain	O
is	O
based	O
on	O
GNU	O
GCC	O
and	O
Binutils	O
.	O
</s>
<s>
XAP6	O
is	O
a	O
32-bit	O
processor	B-General_Concept
and	O
was	O
launched	O
in	O
2013	O
.	O
</s>
<s>
The	O
XAP6a	O
implementation	O
has	O
a	O
three-stage	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
Like	O
all	O
the	O
XAP	B-Device
processors	I-Device
,	O
the	O
XAP6	O
has	O
been	O
optimised	O
for	O
low-cost	O
,	O
low-energy	O
and	O
easy	O
verification	O
.	O
</s>
<s>
XAP6	O
is	O
tailored	O
for	O
small	O
low-energy	O
ASICs	O
and	O
minimises	O
processor	B-General_Concept
hardware	O
size	O
(	O
the	O
XAP6	O
core	O
uses	O
30,000	O
-gates	O
)	O
.	O
</s>
<s>
The	O
XAP6	O
compile	B-Language
chain	O
is	O
based	O
on	O
GNU	O
GCC	O
and	O
Binutils	O
.	O
</s>
<s>
XAP4	O
,	O
XAP5	O
and	O
XAP6	O
are	O
all	O
designed	O
with	O
a	O
load-store	O
RISC	B-Architecture
architecture	O
that	O
is	O
complemented	O
with	O
multi-cycle	O
instructions	O
for	O
multiplication	O
,	O
division	O
,	O
block	O
copy/store	O
and	O
function	O
entry/exit	O
for	O
maximum	O
efficiency	O
.	O
</s>
<s>
Cambridge	O
Consultants’	O
engineers	O
recognised	O
the	O
requirement	O
for	O
these	O
processors	O
to	O
run	O
real-time	B-Operating_System
operating	I-Operating_System
systems	I-Operating_System
capable	O
of	O
handling	O
pre-emptive	B-Operating_System
events	I-Operating_System
and	O
with	O
a	O
fast	O
interrupt	B-Application
response	O
.	O
</s>
<s>
Consequently	O
the	O
processors	O
are	O
designed	O
with	O
hardware	O
and	O
instruction	B-General_Concept
set	I-General_Concept
support	O
for	O
protected	O
software	O
operating	O
modes	O
that	O
partition	O
user	O
code	O
from	O
privileged	O
operating	O
system	O
and	O
interrupt	B-Application
handler	O
code	O
.	O
</s>
<s>
The	O
XAP	B-Device
processor	I-Device
hardware	O
manages	O
the	O
mode	O
transitions	O
and	O
call	B-General_Concept
stack	I-General_Concept
in	O
response	O
to	O
events	O
and	O
this	O
approach	O
ensures	O
a	O
fast	O
and	O
deterministic	O
interrupt	B-Application
response	O
.	O
</s>
<s>
The	O
protected	O
operating	O
modes	O
enable	O
a	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
to	O
be	O
designed	O
that	O
is	O
a	O
secure	O
or	O
trustworthy	O
system	O
and	O
offers	O
high	O
availability	O
.	O
</s>
<s>
The	O
current	O
XAP	B-Device
processors	I-Device
are	O
designed	O
using	O
the	O
Verilog	B-Language
hardware	O
description	O
language	O
and	O
provided	O
as	O
RTL	O
code	O
ready	O
for	O
logic	O
simulation	O
and	O
logic	O
synthesis	O
with	O
a	O
test	O
bench	O
.	O
</s>
