<s>
On	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
,	O
a	O
debug	B-Device
register	I-Device
is	O
a	O
register	O
used	O
by	O
a	O
processor	O
for	O
program	B-Application
debugging	O
.	O
</s>
<s>
There	O
are	O
six	O
debug	B-Device
registers	I-Device
,	O
named	O
DR0	O
...	O
DR7	O
,	O
with	O
DR4	O
and	O
DR5	O
as	O
obsolete	O
synonyms	O
for	O
DR6	O
and	O
DR7	O
.	O
</s>
<s>
The	O
debug	B-Device
registers	I-Device
allow	O
programmers	O
to	O
selectively	O
enable	O
various	O
debug	O
conditions	O
associated	O
with	O
a	O
set	O
of	O
four	O
debug	O
addresses	O
.	O
</s>
<s>
Two	O
of	O
these	O
registers	B-General_Concept
are	O
used	O
to	O
control	O
debug	O
features	O
.	O
</s>
<s>
These	O
registers	B-General_Concept
are	O
accessed	O
by	O
variants	O
of	O
the	O
MOV	O
instruction	O
.	O
</s>
<s>
A	O
debug	B-Device
register	I-Device
may	O
be	O
either	O
the	O
source	O
operand	O
or	O
destination	O
operand	O
.	O
</s>
<s>
The	O
debug	B-Device
registers	I-Device
are	O
privileged	O
resources	O
;	O
the	O
MOV	O
instructions	O
that	O
access	O
them	O
can	O
only	O
be	O
executed	O
at	O
privilege	B-Device
level	I-Device
zero	O
.	O
</s>
<s>
An	O
attempt	O
to	O
read	O
or	O
write	O
the	O
debug	B-Device
registers	I-Device
when	O
executing	O
at	O
any	O
other	O
privilege	B-Device
level	I-Device
causes	O
a	O
general	B-Operating_System
protection	I-Operating_System
fault	I-Operating_System
.	O
</s>
<s>
Each	O
of	O
these	O
registers	B-General_Concept
contains	O
the	O
linear	B-General_Concept
address	I-General_Concept
associated	O
with	O
one	O
of	O
four	O
breakpoint	O
conditions	O
.	O
</s>
<s>
The	O
debug	O
address	B-General_Concept
registers	I-General_Concept
are	O
effective	O
whether	O
or	O
not	O
paging	B-Architecture
is	O
enabled	O
.	O
</s>
<s>
The	O
addresses	O
in	O
these	O
registers	B-General_Concept
are	O
linear	O
addresses	O
.	O
</s>
<s>
If	O
paging	B-Architecture
is	O
enabled	O
,	O
the	O
linear	O
addresses	O
are	O
translated	O
into	O
physical	O
addresses	O
by	O
the	O
processor	O
's	O
paging	B-General_Concept
mechanism	I-General_Concept
.	O
</s>
<s>
If	O
paging	B-Architecture
is	O
not	O
enabled	O
,	O
these	O
linear	O
addresses	O
are	O
the	O
same	O
as	O
physical	O
addresses	O
.	O
</s>
<s>
Note	O
that	O
when	O
paging	B-Architecture
is	O
enabled	O
,	O
different	O
tasks	O
may	O
have	O
different	O
linear-to-physical	O
address	O
mappings	O
.	O
</s>
<s>
When	O
this	O
is	O
the	O
case	O
,	O
an	O
address	O
in	O
a	O
debug	O
address	B-General_Concept
register	I-General_Concept
may	O
be	O
relevant	O
to	O
one	O
task	O
but	O
not	O
to	O
another	O
.	O
</s>
<s>
For	O
this	O
reason	O
the	O
x86	B-Operating_System
has	O
both	O
global	O
and	O
local	O
enable	O
bits	O
in	O
DR7	O
.	O
</s>
<s>
13	O
BD	O
Debug	B-Device
Register	I-Device
Access	O
Detected	O
(	O
see	O
also	O
DR7	O
,	O
bit	O
13	O
)	O
.	O
</s>
<s>
14	O
BS	O
Single-Step	O
execution	O
(	O
enabled	O
by	O
EFLAGS.TF	B-General_Concept
)	O
15	O
BT	O
Task	O
Switch	O
breakpoint.Occurs	O
when	O
a	O
task	O
switch	O
is	O
done	O
with	O
a	O
TSS	B-Device
that	O
has	O
the	O
T	O
(	O
debug	O
trap	O
flag	O
)	O
bit	O
set	O
.	O
</s>
<s>
16	O
RTM	O
(	O
Processors	O
with	O
Intel	B-Operating_System
TSX	I-Operating_System
only	O
)	O
Cleared	O
to	O
0	O
by	O
the	O
processor	O
for	O
debug	O
exceptions	O
inside	O
RTM	O
transactions	O
,	O
set	O
to	O
1	O
for	O
all	O
debug	O
exceptions	O
outside	O
transactions.On	O
processors	O
without	O
TSX	O
,	O
bit	O
16	O
of	O
DR6	O
is	O
a	O
read-only	O
bit	O
,	O
acting	O
in	O
the	O
same	O
way	O
as	O
bits	O
31:17	O
.	O
</s>
<s>
The	O
debug	O
control	B-Operating_System
register	I-Operating_System
is	O
used	O
to	O
selectively	O
enable	O
the	O
four	O
address	O
breakpoint	O
conditions	O
,	O
and	O
to	O
specify	O
the	O
type	O
and	O
size	O
of	O
each	O
of	O
the	O
four	O
breakpoints	O
.	O
</s>
<s>
10	O
11	O
RTM	O
(	O
Processors	O
with	O
Intel	B-Operating_System
TSX	I-Operating_System
only	O
)	O
Enable	O
advanced	O
debugging	O
of	O
RTM	O
transactions	O
(	O
only	O
if	O
DEBUGCTL	O
bit	O
15	O
is	O
also	O
set	O
)	O
On	O
other	O
processors	O
:	O
reserved	O
,	O
read-only	O
,	O
read	O
as	O
0	O
and	O
should	O
be	O
written	O
as	O
0	O
.	O
</s>
<s>
Not	O
real	O
registers	B-General_Concept
.	O
</s>
<s>
On	O
processors	O
that	O
support	O
the	O
CR4.DE	O
bit	O
(	O
Intel	B-General_Concept
Pentium	I-General_Concept
and	O
later	O
)	O
,	O
their	O
behaviour	O
is	O
controlled	O
by	O
CR4.DE	O
:	O
</s>
