<s>
Bit	B-Device
manipulation	I-Device
instructions	I-Device
sets	I-Device
(	O
BMI	O
sets	O
)	O
are	O
extensions	O
to	O
the	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
for	O
microprocessors	B-Architecture
from	O
Intel	O
and	O
AMD	O
.	O
</s>
<s>
The	O
purpose	O
of	O
these	O
instruction	B-General_Concept
sets	I-General_Concept
is	O
to	O
improve	O
the	O
speed	O
of	O
bit	B-Algorithm
manipulation	I-Algorithm
.	O
</s>
<s>
All	O
the	O
instructions	O
in	O
these	O
sets	O
are	O
non-SIMD	O
and	O
operate	O
only	O
on	O
general-purpose	O
registers	B-General_Concept
.	O
</s>
<s>
There	O
are	O
two	O
sets	O
published	O
by	O
Intel	O
:	O
BMI	O
(	O
now	O
referred	O
to	O
as	O
BMI1	O
)	O
and	O
BMI2	O
;	O
they	O
were	O
both	O
introduced	O
with	O
the	O
Haswell	B-Device
microarchitecture	I-Device
with	O
BMI1	O
matching	O
features	O
offered	O
by	O
AMD	O
's	O
ABM	O
instruction	B-General_Concept
set	I-General_Concept
and	O
BMI2	O
extending	O
them	O
.	O
</s>
<s>
Another	O
two	O
sets	O
were	O
published	O
by	O
AMD	O
:	O
ABM	O
(	O
Advanced	O
Bit	B-Algorithm
Manipulation	I-Algorithm
,	O
which	O
is	O
also	O
a	O
subset	O
of	O
SSE4a	O
implemented	O
by	O
Intel	O
as	O
part	O
of	O
SSE4.2	O
and	O
BMI1	O
)	O
,	O
and	O
TBM	O
(	O
Trailing	O
Bit	B-Algorithm
Manipulation	I-Algorithm
,	O
an	O
extension	O
introduced	O
with	O
Piledriver-based	O
processors	O
as	O
an	O
extension	O
to	O
BMI1	O
,	O
but	O
dropped	O
again	O
in	O
Zen-based	O
processors	O
)	O
.	O
</s>
<s>
AMD	O
was	O
the	O
first	O
to	O
introduce	O
the	O
instructions	O
that	O
now	O
form	O
Intel	O
's	O
BMI1	O
as	O
part	O
of	O
its	O
ABM	O
(	O
Advanced	O
Bit	B-Algorithm
Manipulation	I-Algorithm
)	O
instruction	B-General_Concept
set	I-General_Concept
,	O
then	O
later	O
added	O
support	O
for	O
Intel	O
's	O
new	O
BMI2	O
instructions	O
.	O
</s>
<s>
While	O
Intel	O
considers	O
POPCNT	O
as	O
part	O
of	O
SSE4.2	O
and	O
LZCNT	B-Algorithm
as	O
part	O
of	O
BMI1	O
,	O
both	O
Intel	O
and	O
AMD	O
advertise	O
the	O
presence	O
of	O
these	O
two	O
instructions	O
individually	O
.	O
</s>
<s>
POPCNT	O
has	O
a	O
separate	O
CPUID	B-Architecture
flag	O
of	O
the	O
same	O
name	O
,	O
and	O
Intel	O
and	O
AMD	O
use	O
AMD	O
's	O
ABM	O
flag	O
to	O
indicate	O
LZCNT	B-Algorithm
support	O
(	O
since	O
LZCNT	B-Algorithm
combined	O
with	O
BMI1	O
and	O
BMI2	O
completes	O
the	O
expanded	O
ABM	O
instruction	B-General_Concept
set	I-General_Concept
)	O
.	O
</s>
<s>
LZCNT	B-Algorithm
is	O
related	O
to	O
the	O
Bit	B-Algorithm
Scan	I-Algorithm
Reverse	I-Algorithm
(	O
BSR	O
)	O
instruction	O
,	O
but	O
sets	O
the	O
ZF	O
(	O
if	O
the	O
result	O
is	O
zero	O
)	O
and	O
CF	O
(	O
if	O
the	O
source	O
is	O
zero	O
)	O
flags	O
rather	O
than	O
setting	O
the	O
ZF	O
(	O
if	O
the	O
source	O
is	O
zero	O
)	O
.	O
</s>
<s>
For	O
a	O
non-zero	O
argument	O
,	O
sum	O
of	O
LZCNT	B-Algorithm
and	O
BSR	O
results	O
is	O
argument	O
bit	O
width	O
minus	O
1	O
(	O
for	O
example	O
,	O
if	O
32-bit	O
argument	O
is	O
0x000f0000	O
,	O
LZCNT	B-Algorithm
gives	O
12	O
,	O
and	O
BSR	O
gives	O
19	O
)	O
.	O
</s>
<s>
The	O
encoding	O
of	O
LZCNT	B-Algorithm
is	O
such	O
that	O
if	O
ABM	O
is	O
not	O
supported	O
,	O
then	O
the	O
BSR	O
instruction	O
is	O
executed	O
instead	O
.	O
</s>
<s>
The	O
instructions	O
below	O
are	O
those	O
enabled	O
by	O
the	O
BMI	O
bit	O
in	O
CPUID	B-Architecture
.	O
</s>
<s>
Intel	O
officially	O
considers	O
LZCNT	B-Algorithm
as	O
part	O
of	O
BMI	O
,	O
but	O
advertises	O
LZCNT	B-Algorithm
support	O
using	O
the	O
ABM	O
CPUID	B-Architecture
feature	O
flag	O
.	O
</s>
<s>
BMI1	O
is	O
available	O
in	O
AMD	O
's	O
Jaguar	O
,	O
Piledriver	O
and	O
newer	O
processors	O
,	O
and	O
in	O
Intel	O
's	O
Haswell	B-Device
and	O
newer	O
processors	O
.	O
</s>
<s>
TZCNT	O
is	O
almost	O
identical	O
to	O
the	O
Bit	B-Algorithm
Scan	I-Algorithm
Forward	I-Algorithm
(	O
BSF	O
)	O
instruction	O
,	O
but	O
sets	O
the	O
ZF	O
(	O
if	O
the	O
result	O
is	O
zero	O
)	O
and	O
CF	O
(	O
if	O
the	O
source	O
is	O
zero	O
)	O
flags	O
rather	O
than	O
setting	O
the	O
ZF	O
(	O
if	O
the	O
source	O
is	O
zero	O
)	O
.	O
</s>
<s>
As	O
with	O
LZCNT	B-Algorithm
,	O
the	O
encoding	O
of	O
TZCNT	O
is	O
such	O
that	O
if	O
BMI1	O
is	O
not	O
supported	O
,	O
then	O
the	O
BSF	O
instruction	O
is	O
executed	O
instead	O
.	O
</s>
<s>
Intel	O
introduced	O
BMI2	O
together	O
with	O
BMI1	O
in	O
its	O
line	O
of	O
Haswell	B-Device
processors	O
.	O
</s>
<s>
While	O
what	O
these	O
instructions	O
do	O
is	O
similar	O
to	O
bit	O
level	O
gather-scatter	B-General_Concept
SIMD	B-Device
instructions	O
,	O
PDEP	O
and	O
PEXT	O
instructions	O
(	O
like	O
the	O
rest	O
of	O
the	O
BMI	O
instruction	B-General_Concept
sets	I-General_Concept
)	O
operate	O
on	O
general-purpose	O
registers	B-General_Concept
.	O
</s>
<s>
TBM	O
consists	O
of	O
instructions	O
complementary	O
to	O
the	O
instruction	B-General_Concept
set	I-General_Concept
started	O
by	O
BMI1	O
;	O
their	O
complementary	O
nature	O
means	O
they	O
do	O
not	O
necessarily	O
need	O
to	O
be	O
used	O
directly	O
but	O
can	O
be	O
generated	O
by	O
an	O
optimizing	O
compiler	O
when	O
supported	O
.	O
</s>
<s>
No	O
Intel	O
processors	O
(	O
at	O
least	O
through	O
Alder	B-Device
Lake	I-Device
)	O
support	O
TBM	O
.	O
</s>
