<s>
x86	B-Operating_System
(	O
also	O
known	O
as	O
80x86	B-Operating_System
or	O
the	O
8086	B-General_Concept
family	O
)	O
is	O
a	O
family	O
of	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	B-Architecture
)	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
initially	O
developed	O
by	O
Intel	O
based	O
on	O
the	O
Intel	B-General_Concept
8086	I-General_Concept
microprocessor	B-Architecture
and	O
its	O
8088	B-Device
variant	O
.	O
</s>
<s>
The	O
8086	B-General_Concept
was	O
introduced	O
in	O
1978	O
as	O
a	O
fully	O
16-bit	B-Device
extension	O
of	O
Intel	O
's	O
8-bit	O
8080	B-General_Concept
microprocessor	I-General_Concept
,	O
with	O
memory	B-Device
segmentation	I-Device
as	O
a	O
solution	O
for	O
addressing	O
more	O
memory	O
than	O
can	O
be	O
covered	O
by	O
a	O
plain	O
16-bit	B-Device
address	O
.	O
</s>
<s>
The	O
term	O
"	O
x86	B-Operating_System
"	O
came	O
into	O
being	O
because	O
the	O
names	O
of	O
several	O
successors	O
to	O
Intel	O
's	O
8086	B-General_Concept
processor	O
end	O
in	O
"	O
86	O
"	O
,	O
including	O
the	O
80186	B-Device
,	O
80286	B-General_Concept
,	O
80386	B-General_Concept
and	O
80486	B-General_Concept
processors	B-General_Concept
.	O
</s>
<s>
The	O
term	O
is	O
not	O
synonymous	O
with	O
IBM	B-Device
PC	I-Device
compatibility	O
,	O
as	O
this	O
implies	O
a	O
multitude	O
of	O
other	O
computer	B-Architecture
hardware	I-Architecture
.	O
</s>
<s>
Embedded	B-Architecture
systems	I-Architecture
and	O
general-purpose	O
computers	O
used	O
x86	B-Operating_System
chips	O
before	O
the	O
PC-compatible	O
market	O
started	O
,	O
some	O
of	O
them	O
before	O
the	O
IBM	B-Device
PC	I-Device
(	O
1981	O
)	O
debut	O
.	O
</s>
<s>
,	O
most	O
desktop	B-Device
and	O
laptop	B-Device
computers	I-Device
sold	O
are	O
based	O
on	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
family	O
,	O
while	O
mobile	O
categories	O
such	O
as	O
smartphones	B-Application
or	O
tablets	B-Device
are	O
dominated	O
by	O
ARM	B-Architecture
.	O
</s>
<s>
At	O
the	O
high	O
end	O
,	O
x86	B-Operating_System
continues	O
to	O
dominate	O
computation-intensive	O
workstation	B-Device
and	O
cloud	B-Architecture
computing	I-Architecture
segments	O
.	O
</s>
<s>
The	O
fastest	B-Operating_System
supercomputer	I-Operating_System
in	O
the	O
TOP500	B-Operating_System
list	O
for	O
June	O
2022	O
was	O
the	O
first	O
exascale	O
system	O
,	O
Frontier	B-Device
,	O
built	O
using	O
AMD	O
Epyc	O
CPUs	B-General_Concept
based	O
on	O
the	O
x86	B-Operating_System
ISA	B-General_Concept
;	O
it	O
broke	O
the	O
1	O
exaFLOPS	O
barrier	O
in	O
May	O
2022	O
.	O
</s>
<s>
In	O
the	O
1980s	O
and	O
early	O
1990s	O
,	O
when	O
the	O
8088	B-Device
and	O
80286	B-General_Concept
were	O
still	O
in	O
common	O
use	O
,	O
the	O
term	O
x86	B-Operating_System
usually	O
represented	O
any	O
8086-compatible	O
CPU	O
.	O
</s>
<s>
Today	O
,	O
however	O
,	O
x86	B-Operating_System
usually	O
implies	O
a	O
binary	O
compatibility	O
also	O
with	O
the	O
32-bit	O
instruction	B-General_Concept
set	I-General_Concept
of	O
the	O
80386	B-General_Concept
.	O
</s>
<s>
This	O
is	O
due	O
to	O
the	O
fact	O
that	O
this	O
instruction	B-General_Concept
set	I-General_Concept
has	O
become	O
something	O
of	O
a	O
lowest	O
common	O
denominator	O
for	O
many	O
modern	O
operating	B-General_Concept
systems	I-General_Concept
and	O
probably	O
also	O
because	O
the	O
term	O
became	O
common	O
after	O
the	O
introduction	O
of	O
the	O
80386	B-General_Concept
in	O
1985	O
.	O
</s>
<s>
A	O
few	O
years	O
after	O
the	O
introduction	O
of	O
the	O
8086	B-General_Concept
and	O
8088	B-Device
,	O
Intel	O
added	O
some	O
complexity	O
to	O
its	O
naming	O
scheme	O
and	O
terminology	O
as	O
the	O
"	O
iAPX	B-Device
"	O
of	O
the	O
ambitious	O
but	O
ill-fated	O
Intel	B-Device
iAPX	I-Device
432	I-Device
processor	O
was	O
tried	O
on	O
the	O
more	O
successful	O
8086	B-General_Concept
family	O
of	O
chips	O
,	O
applied	O
as	O
a	O
kind	O
of	O
system-level	O
prefix	O
.	O
</s>
<s>
An	O
8086	B-General_Concept
system	O
,	O
including	O
coprocessors	B-General_Concept
such	O
as	O
8087	B-Device
and	O
8089	B-Device
,	O
and	O
simpler	O
Intel-specific	O
system	O
chips	O
,	O
was	O
thereby	O
described	O
as	O
an	O
iAPX	B-General_Concept
86	I-General_Concept
system	O
.	O
</s>
<s>
There	O
were	O
also	O
terms	O
iRMX	O
(	O
for	O
operating	B-General_Concept
systems	I-General_Concept
)	O
,	O
iSBC	O
(	O
for	O
single-board	O
computers	O
)	O
,	O
and	O
iSBX	O
(	O
for	O
multimodule	O
boards	O
based	O
on	O
the	O
8086-architecture	O
)	O
,	O
all	O
together	O
under	O
the	O
heading	O
Microsystem	O
80	O
.	O
</s>
<s>
Although	O
the	O
8086	B-General_Concept
was	O
primarily	O
developed	O
for	O
embedded	B-Architecture
systems	I-Architecture
and	O
small	O
multi-user	O
or	O
single-user	O
computers	O
,	O
largely	O
as	O
a	O
response	O
to	O
the	O
successful	O
8080-compatible	O
Zilog	B-General_Concept
Z80	I-General_Concept
,	O
the	O
x86	B-Operating_System
line	O
soon	O
grew	O
in	O
features	O
and	O
processing	O
power	O
.	O
</s>
<s>
Today	O
,	O
x86	B-Operating_System
is	O
ubiquitous	O
in	O
both	O
stationary	O
and	O
portable	O
personal	B-Device
computers	I-Device
,	O
and	O
is	O
also	O
used	O
in	O
midrange	B-Device
computers	I-Device
,	O
workstations	B-Device
,	O
servers	O
,	O
and	O
most	O
new	O
supercomputer	B-Architecture
clusters	O
of	O
the	O
TOP500	B-Operating_System
list	O
.	O
</s>
<s>
A	O
large	O
amount	O
of	O
software	O
,	O
including	O
a	O
large	O
list	O
of	O
are	O
using	O
x86-based	O
hardware	B-Architecture
.	O
</s>
<s>
Modern	O
x86	B-Operating_System
is	O
relatively	O
uncommon	O
in	O
embedded	B-Architecture
systems	I-Architecture
,	O
however	O
,	O
and	O
small	O
low	O
power	O
applications	O
(	O
using	O
tiny	O
batteries	O
)	O
,	O
and	O
low-cost	O
microprocessor	B-Architecture
markets	O
,	O
such	O
as	O
home	O
appliances	O
and	O
toys	O
,	O
lack	O
significant	O
x86	B-Operating_System
presence	O
.	O
</s>
<s>
Simple	O
8	O
-	O
and	O
16-bit	B-Device
based	O
architectures	B-General_Concept
are	O
common	O
here	O
,	O
as	O
well	O
as	O
simpler	O
RISC	B-Architecture
architectures	I-Architecture
like	O
RISC-V	B-Device
,	O
although	O
the	O
x86-compatible	O
VIA	B-Device
C7	I-Device
,	O
VIA	B-Device
Nano	I-Device
,	O
AMD	O
's	O
Geode	B-Device
,	O
Athlon	B-Architecture
Neo	O
and	O
Intel	B-Device
Atom	I-Device
are	O
examples	O
of	O
32	O
-	O
and	O
64-bit	B-Device
designs	O
used	O
in	O
some	O
relatively	O
low-power	O
and	O
low-cost	O
segments	O
.	O
</s>
<s>
There	O
have	O
been	O
several	O
attempts	O
,	O
including	O
by	O
Intel	O
,	O
to	O
end	O
the	O
market	O
dominance	O
of	O
the	O
"	O
inelegant	O
"	O
x86	B-Operating_System
architecture	I-Operating_System
designed	O
directly	O
from	O
the	O
first	O
simple	O
8-bit	O
microprocessors	B-Architecture
.	O
</s>
<s>
Examples	O
of	O
this	O
are	O
the	O
iAPX	B-Device
432	I-Device
(	O
a	O
project	O
originally	O
named	O
the	O
Intel	O
8800	O
)	O
,	O
the	O
Intel	B-General_Concept
960	I-General_Concept
,	O
Intel	B-General_Concept
860	I-General_Concept
and	O
the	O
Intel/Hewlett	O
-Packard	O
Itanium	B-General_Concept
architecture	O
.	O
</s>
<s>
However	O
,	O
the	O
continuous	O
refinement	O
of	O
x86	B-Operating_System
microarchitectures	B-General_Concept
,	O
circuitry	O
and	O
semiconductor	B-Architecture
manufacturing	I-Architecture
would	O
make	O
it	O
hard	O
to	O
replace	O
x86	B-Operating_System
in	O
many	O
segments	O
.	O
</s>
<s>
AMD	O
's	O
64-bit	B-Device
extension	O
of	O
x86	B-Operating_System
(	O
which	O
Intel	O
eventually	O
responded	O
to	O
with	O
a	O
compatible	O
design	O
)	O
and	O
the	O
scalability	O
of	O
x86	B-Operating_System
chips	O
in	O
the	O
form	O
of	O
modern	O
multi-core	B-Architecture
CPUs	I-Architecture
,	O
is	O
underlining	O
x86	B-Operating_System
as	O
an	O
example	O
of	O
how	O
continuous	O
refinement	O
of	O
established	O
industry	O
standards	O
can	O
resist	O
the	O
competition	O
from	O
completely	O
new	O
architectures	B-General_Concept
.	O
</s>
<s>
The	O
table	O
below	O
lists	O
processor	O
models	O
and	O
model	O
series	O
implementing	O
various	O
architectures	B-General_Concept
in	O
the	O
x86	B-Operating_System
family	O
,	O
in	O
chronological	O
order	O
.	O
</s>
<s>
Each	O
line	O
item	O
is	O
characterized	O
by	O
significantly	O
improved	O
or	O
commercially	O
successful	O
processor	O
microarchitecture	B-General_Concept
designs	O
.	O
</s>
<s>
+Chronology	O
of	O
x86	B-Operating_System
processorsEraIntroductionProminent	O
CPU	O
modelsAddress	O
spaceNotable	O
featuresLinearVirtualPhysicalx86-16	O
1st	O
1978	O
Intel	B-General_Concept
8086	I-General_Concept
,	O
Intel	B-Device
8088	I-Device
(	O
1979	O
)	O
16-bit	B-Device
NA	O
20-bit	O
16-bit	B-Device
ISA	B-General_Concept
,	O
IBM	B-Device
PC	I-Device
(	O
8088	B-Device
)	O
,	O
IBM	B-Device
PC/XT	I-Device
(	O
8088	B-Device
)	O
1982	O
Intel	B-Device
80186	I-Device
,	O
Intel	O
80188NEC	O
V20/V30	O
(	O
1983	O
)	O
8086-2	B-General_Concept
ISA	B-General_Concept
,	O
embedded	O
(	O
80186/80188	B-Device
)	O
2nd	O
Intel	B-General_Concept
80286	I-General_Concept
and	O
clones	O
30-bit	O
24-bit	O
protected	B-Application
mode	I-Application
,	O
IBM	B-Device
PC/XT	I-Device
286	I-Device
,	O
IBM	O
PC/ATIA	O
-32	O
3rd	O
1985	O
Intel	B-General_Concept
80386	I-General_Concept
,	O
AMD	B-Device
Am386	I-Device
(	O
1991	O
)	O
32-bit	O
46-bit	O
32-bit	O
32-bit	O
ISA	B-General_Concept
,	O
paging	B-Architecture
,	O
IBM	B-Device
PS/2	I-Device
4th	O
(	O
pipelining	B-General_Concept
,	O
cache	B-General_Concept
)	O
1989	O
Intel	O
80486Cyrix	O
Cx486S	B-Device
,	O
DLC	B-Device
(	O
1992	O
)	O
AMD	B-Device
Am486	I-Device
(	O
1993	O
)	O
,	O
Am5x86	B-Device
(	O
1995	O
)	O
pipelining	B-General_Concept
,	O
on-die	O
x87	B-Application
FPU	I-Application
(	O
486DX	B-General_Concept
)	O
,	O
on-die	O
cache5th(Superscalar )	O
1993	O
Intel	B-General_Concept
Pentium	I-General_Concept
,	O
Pentium	B-General_Concept
MMX	B-Architecture
(	O
1996	O
)	O
Superscalar	B-General_Concept
,	O
64-bit	B-Device
databus	B-General_Concept
,	O
faster	O
FPU	B-General_Concept
,	O
MMX	B-Architecture
(	O
Pentium	B-General_Concept
MMX	B-Architecture
)	O
,	O
APIC	B-Device
,	O
SMP	B-Operating_System
1994	O
NexGen	O
Nx586AMD	O
5k86/K5	O
(	O
1996	O
)	O
Discrete	O
microarchitecture	B-General_Concept
(µ-	O
op	O
translation	O
)	O
1995	O
Cyrix	O
Cx5x86Cyrix	O
6x86/MX	O
(	O
1997	O
)	O
/MII	O
(	O
1998	O
)	O
dynamic	O
execution6th(PAE, µ-op translation )	O
1995	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
36-bit	O
(	O
PAE	B-General_Concept
)	O
µ-op	B-General_Concept
translation	O
,	O
conditional	O
move	O
instructions	O
,	O
dynamic	B-General_Concept
execution	I-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
3-way	O
x86	B-Operating_System
superscalar	B-General_Concept
,	O
superscalar	B-General_Concept
FPU	B-General_Concept
,	O
PAE	B-General_Concept
,	O
on-chip	O
L2	O
cache	B-General_Concept
1997	O
Intel	B-General_Concept
Pentium	I-General_Concept
II	I-General_Concept
,	O
Pentium	B-General_Concept
III	I-General_Concept
(	O
1999	O
)	O
Celeron	B-Device
(	O
1998	O
)	O
,	O
Xeon	B-Device
(	O
1998	O
)	O
on-package	O
(	O
Pentium	B-General_Concept
II	I-General_Concept
)	O
or	O
on-die	O
(	O
Celeron	B-Device
)	O
L2	O
Cache	B-General_Concept
,	O
SSE	B-General_Concept
(	O
Pentium	B-General_Concept
III	I-General_Concept
)	O
,	O
Slot	B-Device
1	I-Device
,	O
Socket	B-Device
370	I-Device
or	O
Slot	B-Device
2	I-Device
(	O
Xeon	B-Device
)	O
1997	O
AMD	O
K6/K6	O
-2	O
(	O
1998	O
)	O
/K6	O
-III	O
(	O
1999	O
)	O
32-bit	O
3DNow	O
!,	O
3-level	O
cache	B-General_Concept
system	O
(	O
K6-III	B-Architecture
)	O
Enhanced	O
Platform	O
1999	O
AMD	O
AthlonAthlon	O
XP/MP	O
(	O
2001	O
)	O
Duron	O
(	O
2000	O
)	O
Sempron	O
(	O
2004	O
)	O
36-bit	O
MMX+	O
,	O
3DNow	B-General_Concept
!	I-General_Concept
+	O
,	O
double-pumped	O
bus	O
,	O
Slot	O
A	O
or	O
Socket	O
A2000	O
Transmeta	B-General_Concept
Crusoe	I-General_Concept
32-bit	O
CMS	B-Application
powered	O
x86	B-Operating_System
platform	O
processor	O
,	O
VLIW-128	O
core	B-Architecture
,	O
on-die	O
memory	O
controller	O
,	O
on-die	O
PCI	O
bridge	O
logicIntel	O
Pentium	B-General_Concept
4	I-General_Concept
36-bit	O
SSE2	B-General_Concept
,	O
HTT	B-Operating_System
(	O
Northwood	O
)	O
,	O
NetBurst	B-Device
,	O
quad-pumped	O
bus	O
,	O
Trace	O
Cache	B-General_Concept
,	O
Socket	O
4782003	O
Intel	B-General_Concept
Pentium	I-General_Concept
MIntel	O
Core	B-Architecture
(	O
2006	O
)	O
Pentium	B-Device
Dual-Core	I-Device
(	O
2007	O
)	O
µ-op	B-General_Concept
fusion	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
Dothan	O
)	O
(	O
Intel	B-Device
Core	I-Device
"	O
Yonah	O
"	O
)	O
Transmeta	B-General_Concept
Efficeon	I-General_Concept
CMS	B-Application
6.0.4	O
,	O
VLIW-256	O
,	O
NX	B-General_Concept
bit	I-General_Concept
,	O
HTIA-6464-bit	O
Transition1999-2005	O
2001	O
Intel	B-General_Concept
Itanium	I-General_Concept
(	O
2001-2017	O
)	O
52-bit	O
64-bit	B-Device
EPIC	B-General_Concept
architecture	I-General_Concept
,	O
128-bit	O
VLIW	B-General_Concept
instruction	O
bundle	O
,	O
on-die	O
hardware	B-Architecture
IA-32	B-Device
H/W	O
enabling	O
x86	B-Operating_System
OSes	O
&	O
x86	B-Operating_System
applications	O
(	O
early	O
generations	O
)	O
,	O
software	O
IA-32	B-Device
EL	O
enabling	O
x86	B-Operating_System
applications	O
(	O
Itanium	B-General_Concept
2	O
)	O
,	O
Itanium	B-General_Concept
register	O
files	O
are	O
remapped	O
to	O
x86	B-Operating_System
registers	O
x86-64	B-Device
64-bit	B-Device
Extendedsince	O
2001	O
x86-64	B-Device
is	O
the	O
64-bit	B-Device
extended	O
architecture	O
of	O
x86	B-Operating_System
,	O
its	O
Legacy	O
Mode	O
preserves	O
the	O
entire	O
and	O
unaltered	O
x86	B-Operating_System
architecture	I-Operating_System
.	O
</s>
<s>
The	O
native	O
architecture	O
of	O
x86-64	B-Device
processors	B-General_Concept
:	O
residing	O
in	O
the	O
64-bit	B-Device
Mode	O
,	O
lacks	O
of	O
access	O
mode	O
in	O
segmentation	O
,	O
presenting	O
64-bit	B-Device
architectural-permit	O
linear	B-General_Concept
address	I-General_Concept
space	I-General_Concept
;	O
an	O
adapted	O
IA-32	B-Device
architecture	O
residing	O
in	O
the	O
Compatibility	O
Mode	O
alongside	O
64-bit	B-Device
Mode	O
is	O
provided	O
to	O
support	O
most	O
x86	B-Operating_System
applications	O
2003	O
Athlon	B-Architecture
64/FX/X2	O
(	O
2005	O
)	O
,	O
OpteronSempron	O
(	O
2004	O
)	O
/X2	O
(	O
2008	O
)	O
Turion	O
64	O
(	O
2005	O
)	O
/X2	O
(	O
2006	O
)	O
40-bit	O
AMD64	B-Device
(	O
except	O
some	O
Sempron	O
processors	B-General_Concept
presented	O
as	O
purely	O
x86	B-Operating_System
processors	B-General_Concept
)	O
,	O
on-die	O
memory	O
controller	O
,	O
HyperTransport	B-Device
,	O
on-die	O
dual-core	B-Architecture
(	O
X2	O
)	O
,	O
AMD-V	O
(	O
Athlon	B-Architecture
64	O
Orleans	O
)	O
,	O
Socket	O
754/939/940	O
or	O
AM2	O
2004	O
Pentium	B-General_Concept
4	I-General_Concept
(	O
Prescott	O
)	O
Celeron	B-Device
D	O
,	O
Pentium	B-Device
D	I-Device
(	O
2005	O
)	O
36-bit	O
EM64T	B-Device
(	O
enabled	O
on	O
selected	O
models	O
of	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Celeron	B-Device
D	O
)	O
,	O
SSE3	B-General_Concept
,	O
2nd	O
gen	O
.	O
NetBurst	B-Device
pipelining	B-General_Concept
,	O
dual-core	B-Architecture
(	O
on-die	O
:	O
Pentium	B-Device
D	I-Device
8xx	O
,	O
on-chip	O
:	O
Pentium	B-Device
D	I-Device
9xx	O
)	O
,	O
Intel	O
VT(Pentium 4 6x2 )	O
,	O
socket	O
LGA	B-Device
775	I-Device
2006	O
Intel	B-Device
Core	I-Device
2Pentium	O
Dual-Core	B-Architecture
(	O
2007	O
)	O
Celeron	B-Device
Dual-Core	B-Architecture
(	O
2008	O
)	O
Intel	O
64	O
(<<==	O
EM64T	B-Device
)	O
,	O
SSSE3(65 nm )	O
,	O
wide	O
dynamic	B-General_Concept
execution	I-General_Concept
,	O
µ-op	B-General_Concept
fusion	O
,	O
macro-op	O
fusion	O
in	O
16-bit	B-Device
and	O
32-bit	O
mode	O
,	O
on-chip	O
quad-core(Core 2 Quad )	O
,	O
Smart	O
Shared	O
L2	O
Cache	B-General_Concept
(	O
Intel	B-Device
Core	I-Device
2	I-Device
"	O
Merom	B-Device
"	O
)	O
2007	O
AMD	O
Phenom/II	O
(	O
2008	O
)	O
Athlon	B-Architecture
II	O
(	O
2009	O
)	O
Turion	O
II	O
(	O
2009	O
)	O
48-bit	O
Monolithic	O
quad-core	B-Architecture
(	O
X4	O
)	O
/triple	O
-core	O
(	O
X3	O
)	O
,	O
SSE4a	O
,	O
Rapid	O
Virtualization	O
Indexing	O
(	O
RVI	O
)	O
,	O
HyperTransport	B-Device
3	O
,	O
AM2+	O
or	O
AM32008	O
Intel	B-Device
Core	I-Device
2	I-Device
(	O
45	O
nm	O
)	O
40-bit	O
SSE4.1	O
Intel	B-Device
Atom	I-Device
netbook	O
or	O
low	O
power	O
smart	O
device	O
processor	O
,	O
P54C	B-General_Concept
core	B-Architecture
reused	O
Intel	B-Device
Core	I-Device
i7Core	O
i5	O
(	O
2009	O
)	O
Core	B-Device
i3	I-Device
(	O
2010	O
)	O
QuickPath	O
,	O
on-chip	O
GMCH	O
(	O
Clarkdale	B-Device
)	O
,	O
SSE4.2	B-General_Concept
,	O
Extended	O
Page	O
Tables	O
(	O
EPT	O
)	O
for	O
virtualization	O
,	O
macro-op	O
fusion	O
in	O
64-bit	B-Device
mode	O
,	O
(	O
Intel	B-Device
Xeon	I-Device
"	O
Bloomfield	O
"	O
with	O
Nehalem	B-Device
microarchitecture	I-Device
)	O
VIA	B-Device
Nano	I-Device
hardware-based	B-Device
encryption	I-Device
;	O
adaptive	O
power	O
management	O
2010	O
AMD	O
FX	O
48-bit	O
octa-core	B-Architecture
,	O
CMT(Clustered Multi-Thread )	O
,	O
FMA	B-General_Concept
,	O
OpenCL	O
,	O
AM3+2011	O
AMD	B-Architecture
APU	I-Architecture
A	O
and	O
E	O
Series	O
(	O
Llano	B-Architecture
)	O
40-bit	O
on-die	O
GPGPU	O
,	O
PCI	O
Express	O
2.0	O
,	O
Socket	O
FM1	O
AMD	B-Architecture
APU	I-Architecture
C	O
,	O
E	O
and	O
Z	O
Series	O
(	O
Bobcat	O
)	O
36-bit	O
low	O
power	O
smart	O
device	O
APU	O
Intel	B-Device
Core	I-Device
i3	I-Device
,	O
Core	B-Device
i5	I-Device
and	O
Core	B-Architecture
i7( Sandy	O
Bridge/Ivy	O
Bridge	O
)	O
Internal	O
Ring	B-Operating_System
connection	O
,	O
decoded	O
µ-op	B-General_Concept
cache	B-General_Concept
,	O
LGA	B-Device
1155	I-Device
socket2012	O
AMD	B-Architecture
APU	I-Architecture
A	O
Series	O
(	O
Bulldozer	O
,	O
Trinity	O
and	O
later	O
)	O
48-bit	O
AVX	B-General_Concept
,	O
Bulldozer	O
based	O
APU	O
,	O
Socket	O
FM2	O
or	O
Socket	O
FM2+	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
(	O
Knights	O
Corner	O
)	O
PCI-E	O
add-on	O
card	O
coprocessor	B-General_Concept
for	O
XEON	B-Device
based	O
system	O
,	O
Manycore	O
Chip	O
,	O
In-order	O
P54C	B-General_Concept
,	O
very	O
wide	O
VPU	O
(	O
512-bit	O
SSE	B-General_Concept
)	O
,	O
LRBni	O
instructions	O
(	O
8×	O
64-bit	B-Device
)	O
2013	O
AMD	O
Jaguar(Athlon, Sempron )	O
SoC	B-Architecture
,	O
game	O
console	O
and	O
low	O
power	O
smart	O
device	O
processor	O
Intel	O
Silvermont(Atom, Celeron, Pentium )	O
36-bit	O
SoC	B-Architecture
,	O
low/ultra	O
-low	O
power	O
smart	O
device	O
processorIntel	O
Core	B-Device
i3	I-Device
,	O
Core	B-Device
i5	I-Device
and	O
Core	B-Device
i7	I-Device
(	O
Haswell/Broadwell	O
)	O
39-bit	O
AVX2	O
,	O
FMA3	B-General_Concept
,	O
TSX	B-Operating_System
,	O
BMI1	B-Device
,	I-Device
and	I-Device
BMI2	I-Device
instructions	O
,	O
LGA	B-Device
1150	I-Device
socket	O
2015	O
Intel	O
Broadwell-U(Intel Core i3, Core i5, Core i7, Core M, Pentium, Celeron )	O
SoC	B-Architecture
,	O
on-chip	O
Broadwell-U	B-General_Concept
PCH-LP	O
(	O
Multi-chip	O
module	O
)	O
2015−2020	O
Intel	O
Skylake/Kaby	O
Lake/Cannon	O
Lake/Coffee	O
Lake/Rocket	O
Lake( Intel	O
Pentium/Celeron	O
Gold	O
,	O
Core	B-Device
i3	I-Device
,	O
Core	B-Device
i5	I-Device
,	O
Core	B-Device
i7	I-Device
,	O
Core	B-Device
i9	I-Device
)	O
46-bit	O
AVX-512	B-General_Concept
(	O
restricted	O
to	O
Cannon	O
Lake-U	O
and	O
workstation/server	O
variants	O
of	O
Skylake	B-Architecture
)	O
2016	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
(	O
Knights	O
Landing	O
)	O
48-bit	O
Manycore	O
CPU	O
and	O
coprocessor	B-General_Concept
for	O
Xeon	B-Device
systems	O
,	O
Airmont	B-Device
(	O
Atom	B-Device
)	O
based	O
core2016	O
AMD	O
Bristol	O
Ridge( AMD	O
(	O
Pro	O
)	O
A6/A8/A10/A12	O
)	O
Integrated	O
FCH	O
on	O
die	O
,	O
SoC	B-Architecture
,	O
AM4	O
socket2017	O
AMD	O
Ryzen	O
Series/AMD	O
Epyc	O
Series	O
AMD	O
's	O
implementation	O
of	O
SMT	B-Operating_System
,	O
on-chip	O
multiple	O
dies2017	O
Zhaoxin	B-Device
WuDaoKou	O
(	O
KX-5000	O
,	O
KH-20000	O
)	O
Zhaoxin	B-Device
's	O
first	O
brand	O
new	O
x86-64	B-Device
architecture2018−2021	O
Intel	O
Sunny	O
Cove	O
(	O
Ice	O
Lake-U	O
and	O
Y	O
)	O
,	O
Cypress	O
Cove	O
(	O
Rocket	B-Device
Lake	I-Device
)	O
57-bit	O
Intel	O
's	O
first	O
implementation	O
of	O
AVX-512	B-General_Concept
for	O
the	O
consumer	O
segment	O
.	O
</s>
<s>
At	O
various	O
times	O
,	O
companies	O
such	O
as	O
IBM	O
,	O
VIA	O
,	O
NEC	O
,	O
AMD	O
,	O
TI	O
,	O
STM	O
,	O
Fujitsu	O
,	O
OKI	O
,	O
Siemens	O
,	O
Cyrix	O
,	O
Intersil	O
,	O
C&T	O
,	O
NexGen	O
,	O
UMC	O
,	O
and	O
DM&P	B-Device
started	O
to	O
design	O
or	O
manufacture	O
x86	B-Operating_System
processors	B-General_Concept
(	O
CPUs	B-General_Concept
)	O
intended	O
for	O
personal	B-Device
computers	I-Device
and	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
Other	O
companies	O
that	O
designed	O
or	O
manufactured	O
x86	B-Operating_System
or	O
x87	B-Application
processors	B-General_Concept
include	O
ITT	O
Corporation	O
,	O
National	O
Semiconductor	O
,	O
ULSI	O
System	O
Technology	O
,	O
and	O
Weitek	O
.	O
</s>
<s>
Such	O
x86	B-Operating_System
implementations	O
were	O
seldom	O
simple	O
copies	O
but	O
often	O
employed	O
different	O
internal	O
microarchitectures	B-General_Concept
and	O
different	O
solutions	O
at	O
the	O
electronic	O
and	O
physical	B-General_Concept
levels	O
.	O
</s>
<s>
Quite	O
naturally	O
,	O
early	O
compatible	O
microprocessors	B-Architecture
were	O
16-bit	B-Device
,	O
while	O
32-bit	O
designs	O
were	O
developed	O
much	O
later	O
.	O
</s>
<s>
For	O
the	O
personal	B-Device
computer	I-Device
market	O
,	O
real	O
quantities	O
started	O
to	O
appear	O
around	O
1990	O
with	O
i386	B-General_Concept
and	O
i486	B-General_Concept
compatible	O
processors	B-General_Concept
,	O
often	O
named	O
similarly	O
to	O
Intel	O
's	O
original	O
chips	O
.	O
</s>
<s>
After	O
the	O
fully	O
pipelined	B-General_Concept
i486	B-General_Concept
,	O
in	O
1993	O
Intel	O
introduced	O
the	O
Pentium	B-General_Concept
brand	O
name	O
(	O
which	O
,	O
unlike	O
numbers	O
,	O
could	O
be	O
trademarked	O
)	O
for	O
their	O
new	O
set	O
of	O
superscalar	B-General_Concept
x86	B-Operating_System
designs	O
.	O
</s>
<s>
With	O
the	O
x86	B-Operating_System
naming	O
scheme	O
now	O
legally	O
cleared	O
,	O
other	O
x86	B-Operating_System
vendors	O
had	O
to	O
choose	O
different	O
names	O
for	O
their	O
x86-compatible	O
products	O
,	O
and	O
initially	O
some	O
chose	O
to	O
continue	O
with	O
variations	O
of	O
the	O
numbering	O
scheme	O
:	O
IBM	O
partnered	O
with	O
Cyrix	O
to	O
produce	O
the	O
5x86	B-Device
and	O
then	O
the	O
very	O
efficient	O
6x86	B-General_Concept
(	O
M1	O
)	O
and	O
6x86MX	B-General_Concept
(	O
MII	B-General_Concept
)	O
lines	O
of	O
Cyrix	O
designs	O
,	O
which	O
were	O
the	O
first	O
x86	B-Operating_System
microprocessors	I-Operating_System
implementing	O
register	B-Architecture
renaming	I-Architecture
to	O
enable	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
AMD	O
meanwhile	O
designed	O
and	O
manufactured	O
the	O
advanced	O
but	O
delayed	O
5k86	O
(	O
K5	O
)	O
,	O
which	O
,	O
internally	O
,	O
was	O
closely	O
based	O
on	O
AMD	O
's	O
earlier	O
29K	B-General_Concept
RISC	B-Architecture
design	O
;	O
similar	O
to	O
NexGen	O
's	O
Nx586	B-Device
,	O
it	O
used	O
a	O
strategy	O
such	O
that	O
dedicated	O
pipeline	O
stages	O
decode	O
x86	B-Device
instructions	I-Device
into	O
uniform	O
and	O
easily	O
handled	O
micro-operations	B-General_Concept
,	O
a	O
method	O
that	O
has	O
remained	O
the	O
basis	O
for	O
most	O
x86	B-Operating_System
designs	O
to	O
this	O
day	O
.	O
</s>
<s>
Some	O
early	O
versions	O
of	O
these	O
microprocessors	B-Architecture
had	O
heat	O
dissipation	O
problems	O
.	O
</s>
<s>
The	O
6x86	B-General_Concept
was	O
also	O
affected	O
by	O
a	O
few	O
minor	O
compatibility	O
problems	O
,	O
the	O
Nx586	B-Device
lacked	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	B-General_Concept
)	O
and	O
(	O
the	O
then	O
crucial	O
)	O
pin-compatibility	O
,	O
while	O
the	O
K5	O
had	O
somewhat	O
disappointing	O
performance	O
when	O
it	O
was	O
(	O
eventually	O
)	O
introduced	O
.	O
</s>
<s>
Customer	O
ignorance	O
of	O
alternatives	O
to	O
the	O
Pentium	B-General_Concept
series	O
further	O
contributed	O
to	O
these	O
designs	O
being	O
comparatively	O
unsuccessful	O
,	O
despite	O
the	O
fact	O
that	O
the	O
K5	O
had	O
very	O
good	O
Pentium	B-General_Concept
compatibility	O
and	O
the	O
6x86	B-General_Concept
was	O
significantly	O
faster	O
than	O
the	O
Pentium	B-General_Concept
on	O
integer	O
code	O
.	O
</s>
<s>
AMD	O
later	O
managed	O
to	O
grow	O
into	O
a	O
serious	O
contender	O
with	O
the	O
K6	B-Architecture
set	O
of	O
processors	B-General_Concept
,	O
which	O
gave	O
way	O
to	O
the	O
very	O
successful	O
Athlon	B-Architecture
and	O
Opteron	B-General_Concept
.	O
</s>
<s>
VIA	O
Technologies	O
 '	O
energy	O
efficient	O
C3	B-Device
and	O
C7	B-Device
processors	B-General_Concept
,	O
which	O
were	O
designed	O
by	O
the	O
Centaur	O
company	O
,	O
were	O
sold	O
for	O
many	O
years	O
following	O
their	O
release	O
in	O
2005	O
.	O
</s>
<s>
Centaur	O
's	O
2008	O
design	O
,	O
the	O
VIA	B-Device
Nano	I-Device
,	O
was	O
their	O
first	O
processor	O
with	O
superscalar	B-General_Concept
and	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
It	O
was	O
introduced	O
at	O
about	O
the	O
same	O
time	O
(	O
in	O
2008	O
)	O
as	O
Intel	O
introduced	O
the	O
Intel	B-Device
Atom	I-Device
,	O
its	O
first	O
"	O
in-order	O
"	O
processor	O
after	O
the	O
P5	B-General_Concept
Pentium	B-General_Concept
.	O
</s>
<s>
Many	O
additions	O
and	O
extensions	O
have	O
been	O
added	O
to	O
the	O
original	O
x86	B-Device
instruction	I-Device
set	I-Device
over	O
the	O
years	O
,	O
almost	O
consistently	O
with	O
full	O
backward	B-General_Concept
compatibility	I-General_Concept
.	O
</s>
<s>
The	O
architecture	O
family	O
has	O
been	O
implemented	O
in	O
processors	B-General_Concept
from	O
Intel	O
,	O
Cyrix	O
,	O
AMD	O
,	O
VIA	O
Technologies	O
and	O
many	O
other	O
companies	O
;	O
there	O
are	O
also	O
open	O
implementations	O
,	O
such	O
as	O
the	O
Zet	B-Device
SoC	I-Device
platform	O
(	O
currently	O
inactive	O
)	O
.	O
</s>
<s>
Nevertheless	O
,	O
of	O
those	O
,	O
only	O
Intel	O
,	O
AMD	O
,	O
VIA	O
Technologies	O
,	O
and	O
DM&P	B-Device
Electronics	I-Device
hold	O
x86	B-Operating_System
architectural	O
licenses	O
,	O
and	O
from	O
these	O
,	O
only	O
the	O
first	O
two	O
actively	O
produce	O
modern	O
64-bit	B-Device
designs	O
,	O
leading	O
to	O
what	O
has	O
been	O
called	O
a	O
"	O
duopoly	O
"	O
of	O
Intel	O
and	O
AMD	O
in	O
x86	B-Operating_System
processors	B-General_Concept
.	O
</s>
<s>
However	O
,	O
in	O
2014	O
the	O
Shanghai-based	O
Chinese	O
company	O
Zhaoxin	B-Device
,	O
a	O
joint	O
venture	O
between	O
a	O
Chinese	O
company	O
and	O
VIA	O
Technologies	O
,	O
began	O
designing	O
VIA	O
based	O
x86	B-Operating_System
processors	B-General_Concept
for	O
desktops	O
and	O
laptops	B-Device
.	O
</s>
<s>
The	O
release	O
of	O
its	O
newest	O
"	O
7	O
"	O
family	O
of	O
x86	B-Operating_System
processors	B-General_Concept
(	O
e.g.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
has	O
twice	O
been	O
extended	O
to	O
a	O
larger	O
word	O
size	O
.	O
</s>
<s>
In	O
1985	O
,	O
Intel	O
released	O
the	O
32-bit	O
80386	B-General_Concept
(	O
later	O
known	O
as	O
i386	B-General_Concept
)	O
which	O
gradually	O
replaced	O
the	O
earlier	O
16-bit	B-Device
chips	O
in	O
computers	O
(	O
although	O
typically	O
not	O
in	O
embedded	B-Architecture
systems	I-Architecture
)	O
during	O
the	O
following	O
years	O
;	O
this	O
extended	O
programming	O
model	O
was	O
originally	O
referred	O
to	O
as	O
the	O
i386	B-General_Concept
architecture	O
(	O
like	O
its	O
first	O
implementation	O
)	O
but	O
Intel	O
later	O
dubbed	O
it	O
IA-32	B-Device
when	O
introducing	O
its	O
(	O
unrelated	O
)	O
IA-64	B-General_Concept
architecture	O
.	O
</s>
<s>
In	O
1999	O
–	O
2003	O
,	O
AMD	O
extended	O
this	O
32-bit	O
architecture	O
to	O
64bits	B-Device
and	O
referred	O
to	O
it	O
as	O
x86-64	B-Device
in	O
early	O
documents	O
and	O
later	O
as	O
AMD64	B-Device
.	O
</s>
<s>
Intel	O
soon	O
adopted	O
AMD	O
's	O
architectural	O
extensions	O
under	O
the	O
name	O
IA-32e	B-Device
,	O
later	O
using	O
the	O
name	O
EM64T	B-Device
and	O
finally	O
using	O
Intel	O
64	O
.	O
</s>
<s>
Microsoft	O
and	O
Sun	O
Microsystems/Oracle	O
also	O
use	O
term	O
"	O
x64	B-Device
"	O
,	O
while	O
many	O
Linux	B-Application
distributions	I-Application
,	O
and	O
the	O
BSDs	B-Operating_System
also	O
use	O
the	O
"	O
amd64	B-Device
"	O
term	O
.	O
</s>
<s>
Microsoft	O
Windows	O
,	O
for	O
example	O
,	O
designates	O
its	O
32-bit	O
versions	O
as	O
"	O
x86	B-Operating_System
"	O
and	O
64-bit	B-Device
versions	O
as	O
"	O
x64	B-Device
"	O
,	O
while	O
installation	O
files	O
of	O
64-bit	B-Device
Windows	O
versions	O
are	O
required	O
to	O
be	O
placed	O
into	O
a	O
directory	O
called	O
"	O
AMD64	B-Device
"	O
.	O
</s>
<s>
The	O
x86	B-Operating_System
architecture	I-Operating_System
is	O
a	O
variable	O
instruction	O
length	O
,	O
primarily	O
"	O
CISC	B-Architecture
"	O
design	O
with	O
emphasis	O
on	O
backward	B-General_Concept
compatibility	I-General_Concept
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
is	O
not	O
typical	O
CISC	B-Architecture
,	O
however	O
,	O
but	O
basically	O
an	O
extended	O
version	O
of	O
the	O
simple	O
eight-bit	O
8008	B-General_Concept
and	O
8080	B-General_Concept
architectures	B-General_Concept
.	O
</s>
<s>
The	O
largest	O
native	O
size	O
for	O
integer	O
arithmetic	O
and	O
memory	O
addresses	O
(	O
or	O
offsets	B-General_Concept
)	O
is	O
16	O
,	O
32	O
or	O
64bits	B-Device
depending	O
on	O
architecture	O
generation	O
(	O
newer	O
processors	B-General_Concept
include	O
direct	O
support	O
for	O
smaller	O
integers	O
as	O
well	O
)	O
.	O
</s>
<s>
Multiple	O
scalar	O
values	O
can	O
be	O
handled	O
simultaneously	O
via	O
the	O
SIMD	B-Device
unit	O
present	O
in	O
later	O
generations	O
,	O
as	O
described	O
below	O
.	O
</s>
<s>
Immediate	O
addressing	O
offsets	B-General_Concept
and	O
immediate	O
data	O
may	O
be	O
expressed	O
as	O
8-bit	O
quantities	O
for	O
the	O
frequently	O
occurring	O
cases	O
or	O
contexts	O
where	O
a	O
128	O
..	O
127	O
range	O
is	O
enough	O
.	O
</s>
<s>
To	O
further	O
conserve	O
encoding	O
space	O
,	O
most	O
registers	O
are	O
expressed	O
in	O
opcodes	B-Language
using	O
three	O
or	O
four	O
bits	O
,	O
the	O
latter	O
via	O
an	O
opcode	B-Language
prefix	O
in	O
64-bit	B-Device
mode	O
,	O
while	O
at	O
most	O
one	O
operand	O
to	O
an	O
instruction	O
can	O
be	O
a	O
memory	O
location	O
.	O
</s>
<s>
Among	O
other	O
factors	O
,	O
this	O
contributes	O
to	O
a	O
code	O
size	O
that	O
rivals	O
eight-bit	O
machines	O
and	O
enables	O
efficient	O
use	O
of	O
instruction	O
cache	B-General_Concept
memory	O
.	O
</s>
<s>
The	O
relatively	O
small	O
number	O
of	O
general	O
registers	O
(	O
also	O
inherited	O
from	O
its	O
8-bit	O
ancestors	O
)	O
has	O
made	O
register-relative	O
addressing	O
(	O
using	O
small	O
immediate	O
offsets	B-General_Concept
)	O
an	O
important	O
method	O
of	O
accessing	O
operands	O
,	O
especially	O
on	O
the	O
stack	B-Application
.	O
</s>
<s>
Much	O
work	O
has	O
therefore	O
been	O
invested	O
in	O
making	O
such	O
accesses	O
as	O
fast	O
as	O
register	O
accesses	O
—	O
i.e.	O
,	O
a	O
one	O
cycle	O
instruction	O
throughput	O
,	O
in	O
most	O
circumstances	O
where	O
the	O
accessed	O
data	O
is	O
available	O
in	O
the	O
top-level	O
cache	B-General_Concept
.	O
</s>
<s>
A	O
dedicated	O
floating-point	B-General_Concept
processor	I-General_Concept
with	O
80-bit	O
internal	O
registers	O
,	O
the	O
8087	B-Device
,	O
was	O
developed	O
for	O
the	O
original	O
8086	B-General_Concept
.	O
</s>
<s>
This	O
microprocessor	B-Architecture
subsequently	O
developed	O
into	O
the	O
extended	O
80387	O
,	O
and	O
later	O
processors	B-General_Concept
incorporated	O
a	O
backward	B-General_Concept
compatible	I-General_Concept
version	O
of	O
this	O
functionality	O
on	O
the	O
same	O
microprocessor	B-Architecture
as	O
the	O
main	O
processor	O
.	O
</s>
<s>
In	O
addition	O
to	O
this	O
,	O
modern	O
x86	B-Operating_System
designs	O
also	O
contain	O
a	O
SIMD-unit	O
(	O
see	O
SSE	B-General_Concept
below	O
)	O
where	O
instructions	O
can	O
work	O
in	O
parallel	O
on	O
(	O
one	O
or	O
two	O
)	O
128-bit	O
words	O
,	O
each	O
containing	O
two	O
or	O
four	O
floating-point	B-Algorithm
numbers	I-Algorithm
(	O
each	O
64	O
or	O
32bits	O
wide	O
respectively	O
)	O
,	O
or	O
alternatively	O
,	O
2	O
,	O
4	O
,	O
8	O
or	O
16	O
integers	O
(	O
each	O
64	O
,	O
32	O
,	O
16	O
or	O
8bits	O
wide	O
respectively	O
)	O
.	O
</s>
<s>
The	O
presence	O
of	O
wide	O
SIMD	B-Device
registers	O
means	O
that	O
existing	O
x86	B-Operating_System
processors	B-General_Concept
can	O
load	O
or	O
store	O
up	O
to	O
128bits	O
of	O
memory	O
data	O
in	O
a	O
single	O
instruction	O
and	O
also	O
perform	O
bitwise	O
operations	O
(	O
although	O
not	O
integer	O
arithmetic	O
)	O
on	O
full	O
128-bits	O
quantities	O
in	O
parallel	O
.	O
</s>
<s>
Intel	O
's	O
Sandy	B-Device
Bridge	I-Device
processors	B-General_Concept
added	O
the	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
(	O
AVX	B-General_Concept
)	O
instructions	O
,	O
widening	O
the	O
SIMD	B-Device
registers	O
to	O
256	O
bits	O
.	O
</s>
<s>
The	O
Intel	O
Initial	O
Many	O
Core	B-Architecture
Instructions	O
implemented	O
by	O
the	O
Knights	O
Corner	O
Xeon	B-General_Concept
Phi	I-General_Concept
processors	B-General_Concept
,	O
and	O
the	O
AVX-512	B-General_Concept
instructions	O
implemented	O
by	O
the	O
Knights	O
Landing	O
Xeon	B-General_Concept
Phi	I-General_Concept
processors	B-General_Concept
and	O
by	O
Skylake-X	B-Architecture
processors	B-General_Concept
,	O
use	O
512-bit	O
wide	O
SIMD	B-Device
registers	O
.	O
</s>
<s>
During	O
execution	B-General_Concept
,	O
current	O
x86	B-Operating_System
processors	B-General_Concept
employ	O
a	O
few	O
extra	O
decoding	O
steps	O
to	O
split	O
most	O
instructions	O
into	O
smaller	O
pieces	O
called	O
micro-operations	B-General_Concept
.	O
</s>
<s>
These	O
are	O
then	O
handed	O
to	O
a	O
control	B-General_Concept
unit	I-General_Concept
that	O
buffers	O
and	O
schedules	O
them	O
in	O
compliance	O
with	O
x86-semantics	O
so	O
that	O
they	O
can	O
be	O
executed	O
,	O
partly	O
in	O
parallel	O
,	O
by	O
one	O
of	O
several	O
(	O
more	O
or	O
less	O
specialized	O
)	O
execution	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
These	O
modern	O
x86	B-Operating_System
designs	O
are	O
thus	O
pipelined	B-General_Concept
,	O
superscalar	B-General_Concept
,	O
and	O
also	O
capable	O
of	O
out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
and	O
speculative	B-General_Concept
execution	I-General_Concept
(	O
via	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
register	B-Architecture
renaming	I-Architecture
,	O
and	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
)	O
,	O
which	O
means	O
they	O
may	O
execute	O
multiple	O
(	O
partial	O
or	O
complete	O
)	O
x86	B-Device
instructions	I-Device
simultaneously	O
,	O
and	O
not	O
necessarily	O
in	O
the	O
same	O
order	O
as	O
given	O
in	O
the	O
instruction	O
stream	O
.	O
</s>
<s>
Some	O
Intel	B-Device
CPUs	I-Device
(	O
Xeon	B-Device
Foster	O
MP	B-Architecture
,	O
some	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
and	O
some	O
Nehalem	B-Device
and	O
later	O
Intel	B-Device
Core	I-Device
processors	B-General_Concept
)	O
and	O
AMD	B-Device
CPUs	I-Device
(	O
starting	O
from	O
Zen	O
)	O
are	O
also	O
capable	O
of	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
with	O
two	O
threads	B-Operating_System
per	O
core	B-Architecture
(	O
Xeon	B-General_Concept
Phi	I-General_Concept
has	O
four	O
threads	B-Operating_System
per	O
core	B-Architecture
)	O
.	O
</s>
<s>
Some	O
Intel	B-Device
CPUs	I-Device
support	O
transactional	B-Operating_System
memory	I-Operating_System
(	O
TSX	B-Operating_System
)	O
.	O
</s>
<s>
When	O
introduced	O
,	O
in	O
the	O
mid-1990s	O
,	O
this	O
method	O
was	O
sometimes	O
referred	O
to	O
as	O
a	O
"	O
RISC	B-Architecture
core	B-Architecture
"	O
or	O
as	O
"	O
RISC	B-Architecture
translation	O
"	O
,	O
partly	O
for	O
marketing	O
reasons	O
,	O
but	O
also	O
because	O
these	O
micro-operations	B-General_Concept
share	O
some	O
properties	O
with	O
certain	O
types	O
of	O
RISC	B-Architecture
instructions	O
.	O
</s>
<s>
However	O
,	O
traditional	O
microcode	B-Device
(	O
used	O
since	O
the	O
1950s	O
)	O
also	O
inherently	O
shares	O
many	O
of	O
the	O
same	O
properties	O
;	O
the	O
new	O
method	O
differs	O
mainly	O
in	O
that	O
the	O
translation	O
to	O
micro-operations	B-General_Concept
now	O
occurs	O
asynchronously	O
.	O
</s>
<s>
Not	O
having	O
to	O
synchronize	O
the	O
execution	B-General_Concept
units	I-General_Concept
with	O
the	O
decode	O
steps	O
opens	O
up	O
possibilities	O
for	O
more	O
analysis	O
of	O
the	O
(	O
buffered	O
)	O
code	O
stream	O
,	O
and	O
therefore	O
permits	O
detection	O
of	O
operations	O
that	O
can	O
be	O
performed	O
in	O
parallel	O
,	O
simultaneously	O
feeding	O
more	O
than	O
one	O
execution	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
latest	O
processors	B-General_Concept
also	O
do	O
the	O
opposite	O
when	O
appropriate	O
;	O
they	O
combine	O
certain	O
x86	B-Operating_System
sequences	O
(	O
such	O
as	O
a	O
compare	O
followed	O
by	O
a	O
conditional	O
jump	O
)	O
into	O
a	O
more	O
complex	O
micro-op	B-General_Concept
which	O
fits	O
the	O
execution	B-General_Concept
model	O
better	O
and	O
thus	O
can	O
be	O
executed	O
faster	O
or	O
with	O
fewer	O
machine	O
resources	O
involved	O
.	O
</s>
<s>
Another	O
way	O
to	O
try	O
to	O
improve	O
performance	O
is	O
to	O
cache	B-General_Concept
the	O
decoded	O
micro-operations	B-General_Concept
,	O
so	O
the	O
processor	O
can	O
directly	O
access	O
the	O
decoded	O
micro-operations	B-General_Concept
from	O
a	O
special	O
cache	B-General_Concept
,	O
instead	O
of	O
decoding	O
them	O
again	O
.	O
</s>
<s>
Intel	O
followed	O
this	O
approach	O
with	O
the	O
Execution	B-General_Concept
Trace	O
Cache	B-General_Concept
feature	O
in	O
their	O
NetBurst	B-Device
microarchitecture	B-General_Concept
(	O
for	O
Pentium	B-General_Concept
4	I-General_Concept
processors	B-General_Concept
)	O
and	O
later	O
in	O
the	O
Decoded	O
Stream	O
Buffer	O
(	O
for	O
Core-branded	O
processors	B-General_Concept
since	O
Sandy	B-Device
Bridge	I-Device
)	O
.	O
</s>
<s>
Transmeta	O
used	O
a	O
completely	O
different	O
method	O
in	O
their	O
Crusoe	B-General_Concept
x86	B-Operating_System
compatible	I-Operating_System
CPUs	B-General_Concept
.	O
</s>
<s>
They	O
used	O
just-in-time	O
translation	O
to	O
convert	O
x86	B-Device
instructions	I-Device
to	O
the	O
CPU	O
's	O
native	O
VLIW	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Transmeta	O
argued	O
that	O
their	O
approach	O
allows	O
for	O
more	O
power	O
efficient	O
designs	O
since	O
the	O
CPU	O
can	O
forgo	O
the	O
complicated	O
decode	O
step	O
of	O
more	O
traditional	O
x86	B-Operating_System
implementations	O
.	O
</s>
<s>
Addressing	B-Language
modes	I-Language
for	O
16-bit	B-Device
processor	I-Device
modes	O
can	O
be	O
summarized	O
by	O
the	O
formula	O
:	O
</s>
<s>
Addressing	B-Language
modes	I-Language
for	O
32-bit	B-Device
x86	I-Device
processor	O
modes	O
can	O
be	O
summarized	O
by	O
the	O
formula	O
:	O
</s>
<s>
Addressing	B-Language
modes	I-Language
for	O
the	O
64-bit	B-Device
processor	I-Device
mode	O
can	O
be	O
summarized	O
by	O
the	O
formula	O
:	O
</s>
<s>
Instruction	O
relative	B-General_Concept
addressing	I-General_Concept
in	O
64-bit	B-Device
code	O
(	O
RIP	O
+	O
displacement	O
,	O
where	O
RIP	O
is	O
the	O
instruction	B-General_Concept
pointer	I-General_Concept
register	I-General_Concept
)	O
simplifies	O
the	O
implementation	O
of	O
position-independent	B-Operating_System
code	I-Operating_System
(	O
as	O
used	O
in	O
shared	O
libraries	O
in	O
some	O
operating	B-General_Concept
systems	I-General_Concept
)	O
.	O
</s>
<s>
The	O
8086	B-General_Concept
had	O
of	O
eight-bit	O
(	O
or	O
alternatively	O
)	O
I/O	B-General_Concept
space	O
,	O
and	O
a	O
(	O
one	O
segment	O
)	O
stack	B-Application
in	O
memory	O
supported	O
by	O
computer	B-Architecture
hardware	I-Architecture
.	O
</s>
<s>
Only	O
words	O
(	O
two	O
bytes	O
)	O
can	O
be	O
pushed	O
to	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
stack	B-Application
grows	O
toward	O
numerically	B-General_Concept
lower	O
addresses	O
,	O
with	O
pointing	O
to	O
the	O
most	O
recently	O
pushed	O
item	O
.	O
</s>
<s>
There	O
are	O
256	O
interrupts	B-Application
,	O
which	O
can	O
be	O
invoked	O
by	O
both	O
hardware	B-Architecture
and	O
software	O
.	O
</s>
<s>
The	O
interrupts	B-Application
can	O
cascade	O
,	O
using	O
the	O
stack	B-Application
to	O
store	O
the	O
return	B-Language
address	I-Language
.	O
</s>
<s>
The	O
original	O
Intel	B-General_Concept
8086	I-General_Concept
and	O
8088	B-Device
have	O
fourteen	O
16-bit	B-Device
registers	O
.	O
</s>
<s>
Four	O
of	O
them	O
(	O
AX	O
,	O
BX	O
,	O
CX	O
,	O
DX	O
)	O
are	O
general-purpose	O
registers	O
(	O
GPRs	B-General_Concept
)	O
,	O
although	O
each	O
may	O
have	O
an	O
additional	O
purpose	O
;	O
for	O
example	O
,	O
only	O
CX	O
can	O
be	O
used	O
as	O
a	O
counter	O
with	O
the	O
loop	O
instruction	O
.	O
</s>
<s>
Two	O
pointer	B-General_Concept
registers	I-General_Concept
have	O
special	O
roles	O
:	O
SP	O
(	O
stack	B-Application
pointer	O
)	O
points	O
to	O
the	O
"	O
top	O
"	O
of	O
the	O
stack	B-Application
,	O
and	O
BP	O
(	O
base	O
pointer	O
)	O
is	O
often	O
used	O
to	O
point	O
at	O
some	O
other	O
place	O
in	O
the	O
stack	B-Application
,	O
typically	O
above	O
the	O
local	O
variables	O
(	O
see	O
frame	O
pointer	O
)	O
.	O
</s>
<s>
The	O
registers	O
SI	O
,	O
DI	O
,	O
BX	O
and	O
BP	O
are	O
address	B-General_Concept
registers	I-General_Concept
,	O
and	O
may	O
also	O
be	O
used	O
for	O
array	O
indexing	O
.	O
</s>
<s>
Four	O
segment	B-Device
registers	I-Device
(	O
CS	O
,	O
DS	O
,	O
SS	O
and	O
ES	O
)	O
are	O
used	O
to	O
form	O
a	O
memory	O
address	O
.	O
</s>
<s>
The	O
FLAGS	B-General_Concept
register	I-General_Concept
contains	O
flags	B-General_Concept
such	O
as	O
carry	B-Algorithm
flag	I-Algorithm
,	O
overflow	B-Algorithm
flag	I-Algorithm
and	O
zero	B-Algorithm
flag	I-Algorithm
.	O
</s>
<s>
Finally	O
,	O
the	O
instruction	B-General_Concept
pointer	I-General_Concept
(	O
IP	O
)	O
points	O
to	O
the	O
next	B-General_Concept
instruction	I-General_Concept
that	O
will	O
be	O
fetched	O
from	O
memory	O
and	O
then	O
executed	O
;	O
this	O
register	O
cannot	O
be	O
directly	O
accessed	O
(	O
read	O
or	O
written	O
)	O
by	O
a	O
program	O
.	O
</s>
<s>
The	O
Intel	B-Device
80186	I-Device
and	O
80188	B-Device
are	O
essentially	O
an	O
upgraded	O
8086	B-General_Concept
or	O
8088	B-Device
CPU	O
,	O
respectively	O
,	O
with	O
on-chip	O
peripherals	O
added	O
,	O
and	O
they	O
have	O
the	O
same	O
CPU	B-General_Concept
registers	I-General_Concept
as	O
the	O
8086	B-General_Concept
and	O
8088	B-Device
(	O
in	O
addition	O
to	O
interface	O
registers	O
for	O
the	O
peripherals	O
)	O
.	O
</s>
<s>
The	O
8086	B-General_Concept
,	O
8088	B-Device
,	O
80186	B-Device
,	O
and	O
80188	B-Device
can	O
use	O
an	O
optional	O
floating-point	B-Algorithm
coprocessor	B-General_Concept
,	O
the	O
8087	B-Device
.	O
</s>
<s>
The	O
8087	B-Device
appears	O
to	O
the	O
programmer	O
as	O
part	O
of	O
the	O
CPU	O
and	O
adds	O
eight	O
80-bit	O
wide	O
registers	O
,	O
st(0 )	O
to	O
st(7 )	O
,	O
each	O
of	O
which	O
can	O
hold	O
numeric	B-Algorithm
data	O
in	O
one	O
of	O
seven	O
formats	O
:	O
32-	O
,	O
64-	O
,	O
or	O
80-bit	O
floating	B-Algorithm
point	I-Algorithm
,	O
16-	O
,	O
32-	O
,	O
or	O
64-bit	B-Device
(	O
binary	O
)	O
integer	O
,	O
and	O
80-bit	O
packed	O
decimal	O
integer	O
.	O
</s>
<s>
It	O
also	O
has	O
its	O
own	O
16-bit	B-Device
status	B-General_Concept
register	I-General_Concept
accessible	O
through	O
the	O
instruction	O
,	O
and	O
it	O
is	O
common	O
to	O
simply	O
use	O
some	O
of	O
its	O
bits	O
for	O
branching	O
by	O
copying	O
it	O
into	O
the	O
normal	O
FLAGS	B-General_Concept
.	O
</s>
<s>
In	O
the	O
Intel	B-General_Concept
80286	I-General_Concept
,	O
to	O
support	O
protected	B-Application
mode	I-Application
,	O
three	O
special	O
registers	O
hold	O
descriptor	O
table	O
addresses	O
(	O
GDTR	O
,	O
LDTR	O
,	O
IDTR	B-General_Concept
)	O
,	O
and	O
a	O
fourth	O
task	O
register	O
(	O
TR	O
)	O
is	O
used	O
for	O
task	O
switching	O
.	O
</s>
<s>
The	O
80287	O
is	O
the	O
floating-point	B-Algorithm
coprocessor	B-General_Concept
for	O
the	O
80286	B-General_Concept
and	O
has	O
the	O
same	O
registers	O
as	O
the	O
8087	B-Device
with	O
the	O
same	O
data	O
formats	O
.	O
</s>
<s>
With	O
the	O
advent	O
of	O
the	O
32-bit	O
80386	B-General_Concept
processor	O
,	O
the	O
16-bit	B-Device
general-purpose	O
registers	O
,	O
base	O
registers	O
,	O
index	O
registers	O
,	O
instruction	B-General_Concept
pointer	I-General_Concept
,	O
and	O
FLAGS	B-General_Concept
register	I-General_Concept
,	O
but	O
not	O
the	O
segment	B-Device
registers	I-Device
,	O
were	O
expanded	O
to	O
32bits	O
.	O
</s>
<s>
The	O
nomenclature	O
represented	O
this	O
by	O
prefixing	O
an	O
"	O
E	O
"	O
(	O
for	O
"	O
extended	O
"	O
)	O
to	O
the	O
register	O
names	O
in	O
x86	B-Language
assembly	I-Language
language	I-Language
.	O
</s>
<s>
The	O
general-purpose	O
registers	O
,	O
base	O
registers	O
,	O
and	O
index	O
registers	O
can	O
all	O
be	O
used	O
as	O
the	O
base	O
in	O
addressing	B-Language
modes	I-Language
,	O
and	O
all	O
of	O
those	O
registers	O
except	O
for	O
the	O
stack	B-Application
pointer	O
can	O
be	O
used	O
as	O
the	O
index	O
in	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
Two	O
new	O
segment	B-Device
registers	I-Device
(	O
FS	B-Device
and	I-Device
GS	I-Device
)	O
were	O
added	O
.	O
</s>
<s>
With	O
a	O
greater	O
number	O
of	O
registers	O
,	O
instructions	O
and	O
operands	O
,	O
the	O
machine	B-Language
code	I-Language
format	O
was	O
expanded	O
.	O
</s>
<s>
To	O
provide	O
backward	B-General_Concept
compatibility	I-General_Concept
,	O
segments	O
with	O
executable	O
code	O
can	O
be	O
marked	O
as	O
containing	O
either	O
16-bit	B-Device
or	O
32-bit	O
instructions	O
.	O
</s>
<s>
Special	O
prefixes	O
allow	O
inclusion	O
of	O
32-bit	O
instructions	O
in	O
a	O
16-bit	B-Device
segment	O
or	O
vice	O
versa	O
.	O
</s>
<s>
The	O
80386	B-General_Concept
had	O
an	O
optional	O
floating-point	B-Algorithm
coprocessor	B-General_Concept
,	O
the	O
80387	O
;	O
it	O
had	O
eight	O
80-bit	O
wide	O
registers	O
:	O
st(0 )	O
to	O
st(7 )	O
,	O
like	O
the	O
8087	B-Device
and	O
80287	O
.	O
</s>
<s>
The	O
80386	B-General_Concept
could	O
also	O
use	O
an	O
80287	O
coprocessor	B-General_Concept
.	O
</s>
<s>
With	O
the	O
80486	B-General_Concept
and	O
all	O
subsequent	O
x86	B-Operating_System
models	O
,	O
the	O
floating-point	B-Algorithm
processing	O
unit	O
(	O
FPU	B-General_Concept
)	O
is	O
integrated	O
on-chip	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
MMX	B-Architecture
added	O
eight	O
64-bit	B-Device
MMX	B-Architecture
integer	O
vector	O
registers	O
(	O
MM0	O
to	O
MM7	O
,	O
which	O
share	O
lower	O
bits	O
with	O
the	O
80-bit-wide	O
FPU	B-General_Concept
stack	B-Application
)	O
.	O
</s>
<s>
With	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
Intel	O
added	O
a	O
32-bit	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
(	O
SSE	B-General_Concept
)	O
control/status	O
register	O
(	O
MXCSR	O
)	O
and	O
eight	O
128-bit	O
SSE	B-General_Concept
floating-point	B-Algorithm
registers	O
(	O
XMM0	O
to	O
XMM7	O
)	O
.	O
</s>
<s>
Starting	O
with	O
the	O
AMD	B-General_Concept
Opteron	I-General_Concept
processor	O
,	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
extended	O
the	O
32-bit	O
registers	O
into	O
64-bit	B-Device
registers	O
in	O
a	O
way	O
similar	O
to	O
how	O
the	O
16	O
to	O
32-bit	O
extension	O
took	O
place	O
.	O
</s>
<s>
An	O
R-prefix	O
(	O
for	O
"	O
register	O
"	O
)	O
identifies	O
the	O
64-bit	B-Device
registers	O
(	O
RAX	O
,	O
RBX	O
,	O
RCX	O
,	O
RDX	O
,	O
RSI	O
,	O
RDI	O
,	O
RBP	O
,	O
RSP	O
,	O
RFLAGS	B-General_Concept
,	O
RIP	O
)	O
,	O
and	O
eight	O
additional	O
64-bit	B-Device
general	O
registers	O
(	O
R8	O
–	O
R15	O
)	O
were	O
also	O
introduced	O
in	O
the	O
creation	O
of	O
x86-64	B-Device
.	O
</s>
<s>
Also	O
,	O
eight	O
more	O
SSE	B-General_Concept
vector	O
registers	O
(	O
XMM8	O
–	O
XMM15	O
)	O
were	O
added	O
.	O
</s>
<s>
However	O
,	O
these	O
extensions	O
are	O
only	O
usable	O
in	O
64-bit	B-Device
mode	O
,	O
which	O
is	O
one	O
of	O
the	O
two	O
modes	O
only	O
available	O
in	O
long	B-Application
mode	I-Application
.	O
</s>
<s>
The	O
addressing	B-Language
modes	I-Language
were	O
not	O
dramatically	O
changed	O
from	O
32-bit	O
mode	O
,	O
except	O
that	O
addressing	O
was	O
extended	O
to	O
64bits	B-Device
,	O
virtual	B-General_Concept
addresses	O
are	O
now	O
sign	O
extended	O
to	O
64bits	B-Device
(	O
in	O
order	O
to	O
disallow	O
mode	O
bits	O
in	O
virtual	B-General_Concept
addresses	O
)	O
,	O
and	O
other	O
selector	O
details	O
were	O
dramatically	O
reduced	O
.	O
</s>
<s>
In	O
addition	O
,	O
an	O
addressing	B-Language
mode	I-Language
was	O
added	O
to	O
allow	O
memory	O
references	O
relative	O
to	O
RIP	O
(	O
the	O
instruction	B-General_Concept
pointer	I-General_Concept
)	O
,	O
to	O
ease	O
the	O
implementation	O
of	O
position-independent	B-Operating_System
code	I-Operating_System
,	O
used	O
in	O
shared	O
libraries	O
in	O
some	O
operating	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
SIMD	B-Device
registers	O
XMM0	O
–	O
XMM15	O
(	O
XMM0	O
–	O
XMM31	O
when	O
AVX-512	B-General_Concept
is	O
supported	O
)	O
.	O
</s>
<s>
SIMD	B-Device
registers	O
YMM0	O
–	O
YMM15	O
(	O
YMM0	O
–	O
YMM31	O
when	O
AVX-512	B-General_Concept
is	O
supported	O
)	O
.	O
</s>
<s>
SIMD	B-Device
registers	O
ZMM0	O
–	O
ZMM31	O
.	O
</s>
<s>
x86	B-Operating_System
processors	B-General_Concept
that	O
have	O
a	O
protected	B-Application
mode	I-Application
,	O
i.e.	O
</s>
<s>
the	O
80286	B-General_Concept
and	O
later	O
processors	B-General_Concept
,	O
also	O
have	O
three	O
descriptor	O
registers	O
(	O
GDTR	O
,	O
LDTR	O
,	O
IDTR	B-General_Concept
)	O
and	O
a	O
task	O
register	O
(	O
TR	O
)	O
.	O
</s>
<s>
32-bit	B-Device
x86	I-Device
processors	B-General_Concept
(	O
starting	O
with	O
the	O
80386	B-General_Concept
)	O
also	O
include	O
various	O
special/miscellaneous	O
registers	O
such	O
as	O
control	B-Operating_System
registers	I-Operating_System
(	O
CR0	B-Operating_System
through	O
4	O
,	O
CR8	O
for	O
64-bit	B-Device
only	O
)	O
,	O
debug	B-Device
registers	I-Device
(	O
DR0	O
through	O
3	O
,	O
plus	O
6	O
and	O
7	O
)	O
,	O
test	B-General_Concept
registers	I-General_Concept
(	O
TR3	O
through	O
7	O
;	O
80486	B-General_Concept
only	O
)	O
,	O
and	O
model-specific	B-General_Concept
registers	I-General_Concept
(	O
MSRs	O
,	O
appearing	O
with	O
the	O
Pentium	B-General_Concept
)	O
.	O
</s>
<s>
AVX-512	B-General_Concept
has	O
eight	O
extra	O
64-bit	B-Device
mask	O
registers	O
K0	O
–	O
K7	B-Architecture
for	O
selecting	O
elements	O
in	O
a	O
vector	O
register	O
.	O
</s>
<s>
Although	O
the	O
main	O
registers	O
(	O
with	O
the	O
exception	O
of	O
the	O
instruction	B-General_Concept
pointer	I-General_Concept
)	O
are	O
"	O
general-purpose	O
"	O
in	O
the	O
32-bit	O
and	O
64-bit	B-Device
versions	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
and	O
can	O
be	O
used	O
for	O
anything	O
,	O
it	O
was	O
originally	O
envisioned	O
that	O
they	O
be	O
used	O
for	O
the	O
following	O
purposes	O
:	O
</s>
<s>
DL/DH/DX/EDX/RDX	O
:	O
Extend	O
the	O
precision	O
of	O
the	O
accumulator	B-General_Concept
(	O
e.g.	O
</s>
<s>
SP/ESP/RSP	O
:	O
Stack	B-Application
pointer	O
for	O
top	O
address	O
of	O
the	O
stack	B-Application
.	O
</s>
<s>
BP/EBP/RBP	O
:	O
Stack	B-Application
base	O
pointer	O
for	O
holding	O
the	O
address	O
of	O
the	O
current	O
stack	B-Application
frame	O
.	O
</s>
<s>
IP/EIP/RIP	O
:	O
Instruction	B-General_Concept
pointer	I-General_Concept
.	O
</s>
<s>
Holds	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
the	O
address	O
of	O
next	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
Segment	B-Device
registers	I-Device
:	O
</s>
<s>
No	O
particular	O
purposes	O
were	O
envisioned	O
for	O
the	O
other	O
8	O
registers	O
available	O
only	O
in	O
64-bit	B-Device
mode	O
.	O
</s>
<s>
For	O
example	O
,	O
using	O
AL	O
as	O
an	O
accumulator	B-General_Concept
and	O
adding	O
an	O
immediate	O
byte	O
value	O
to	O
it	O
produces	O
the	O
efficient	O
add	O
to	O
AL	O
opcode	B-Language
of	O
04h	O
,	O
whilst	O
using	O
the	O
BL	O
register	O
produces	O
the	O
generic	O
and	O
longer	O
add	O
to	O
register	O
opcode	B-Language
of	O
80C3h	O
.	O
</s>
<s>
Modern	O
compilers	O
benefited	O
from	O
the	O
introduction	O
of	O
the	O
sib	O
byte	O
(	O
scale-index-base	O
byte	O
)	O
that	O
allows	O
registers	O
to	O
be	O
treated	O
uniformly	O
(	O
minicomputer-like	O
)	O
.	O
</s>
<s>
(	O
The	O
main	O
benefit	O
of	O
the	O
sib	O
byte	O
is	O
the	O
orthogonality	O
and	O
more	O
powerful	O
addressing	B-Language
modes	I-Language
it	O
provides	O
,	O
which	O
make	O
it	O
possible	O
to	O
save	O
instructions	O
and	O
the	O
use	O
of	O
registers	O
for	O
address	O
calculations	O
such	O
as	O
scaling	O
an	O
index	O
.	O
)	O
</s>
<s>
Some	O
special	O
instructions	O
lost	O
priority	O
in	O
the	O
hardware	B-Architecture
design	O
and	O
became	O
slower	O
than	O
equivalent	O
small	O
code	O
sequences	O
.	O
</s>
<s>
+	O
64-bit	B-Device
mode-only	O
General	O
Purpose	O
Registers	O
(	O
R8	O
,	O
R9	O
,	O
R10	O
,	O
R11	O
,	O
R12	O
,	O
R13	O
,	O
R14	O
,	O
R15	O
)	O
64	O
56	O
48	O
40	O
32	O
24	O
16	O
8	O
?	O
</s>
<s>
Note	O
:	O
The	O
?	O
PL	O
registers	O
are	O
only	O
available	O
in	O
64-bit	B-Device
mode	O
.	O
</s>
<s>
Note	O
:	O
The	O
?	O
IL	O
registers	O
are	O
only	O
available	O
in	O
64-bit	B-Device
mode	O
.	O
</s>
<s>
Real	B-Application
Address	I-Application
mode	I-Application
,	O
commonly	O
called	O
Real	B-Application
mode	I-Application
,	O
is	O
an	O
operating	O
mode	O
of	O
8086	B-General_Concept
and	O
later	O
x86-compatible	O
CPUs	B-General_Concept
.	O
</s>
<s>
Real	B-Application
mode	I-Application
is	O
characterized	O
by	O
a	O
20-bit	O
segmented	O
memory	O
address	B-General_Concept
space	I-General_Concept
(	O
meaning	O
that	O
only	O
slightly	O
more	O
than	O
1	O
MiB	O
of	O
memory	O
can	O
be	O
addressed	O
)	O
,	O
direct	O
software	O
access	O
to	O
peripheral	O
hardware	B-Architecture
,	O
and	O
no	O
concept	O
of	O
memory	B-General_Concept
protection	I-General_Concept
or	O
multitasking	B-Operating_System
at	O
the	O
hardware	B-Architecture
level	O
.	O
</s>
<s>
All	O
x86	B-Operating_System
CPUs	B-General_Concept
in	O
the	O
80286	B-General_Concept
series	O
and	O
later	O
start	O
up	O
in	O
real	B-Application
mode	I-Application
at	O
power-on	O
;	O
80186	B-Device
CPUs	B-General_Concept
and	O
earlier	O
had	O
only	O
one	O
operational	O
mode	O
,	O
which	O
is	O
equivalent	O
to	O
real	B-Application
mode	I-Application
in	O
later	O
chips	O
.	O
</s>
<s>
(	O
On	O
the	O
IBM	B-Device
PC	I-Device
platform	O
,	O
direct	O
software	O
access	O
to	O
the	O
IBM	B-Operating_System
BIOS	I-Operating_System
routines	O
is	O
available	O
only	O
in	O
real	B-Application
mode	I-Application
,	O
since	O
BIOS	B-Operating_System
is	O
written	O
for	O
real	B-Application
mode	I-Application
.	O
</s>
<s>
However	O
,	O
this	O
is	O
not	O
a	O
property	O
of	O
the	O
x86	B-Operating_System
CPU	O
but	O
of	O
the	O
IBM	B-Operating_System
BIOS	I-Operating_System
design	O
.	O
)	O
</s>
<s>
In	O
order	O
to	O
use	O
more	O
than	O
64KB	O
of	O
memory	O
,	O
the	O
segment	B-Device
registers	I-Device
must	O
be	O
used	O
.	O
</s>
<s>
This	O
created	O
great	O
complications	O
for	O
compiler	O
implementors	O
who	O
introduced	O
odd	O
pointer	O
modes	O
such	O
as	O
"	O
near	O
"	O
,	O
"	O
far	O
"	O
and	O
"	O
huge	O
"	O
to	O
leverage	O
the	O
implicit	O
nature	O
of	O
segmented	O
architecture	O
to	O
different	O
degrees	O
,	O
with	O
some	O
pointers	O
containing	O
16-bit	B-Device
offsets	B-General_Concept
within	O
implied	O
segments	O
and	O
other	O
pointers	O
containing	O
segment	O
addresses	O
and	O
offsets	B-General_Concept
within	O
segments	O
.	O
</s>
<s>
It	O
is	O
technically	O
possible	O
to	O
use	O
up	O
to	O
256KB	O
of	O
memory	O
for	O
code	O
and	O
data	O
,	O
with	O
up	O
to	O
64KB	O
for	O
code	O
,	O
by	O
setting	O
all	O
four	O
segment	B-Device
registers	I-Device
once	O
and	O
then	O
only	O
using	O
16-bit	B-Device
offsets	B-General_Concept
(	O
optionally	O
with	O
default-segment	O
override	O
prefixes	O
)	O
to	O
address	O
memory	O
,	O
but	O
this	O
puts	O
substantial	O
restrictions	O
on	O
the	O
way	O
data	O
can	O
be	O
addressed	O
and	O
memory	O
operands	O
can	O
be	O
combined	O
,	O
and	O
it	O
violates	O
the	O
architectural	O
intent	O
of	O
the	O
Intel	O
designers	O
,	O
which	O
is	O
for	O
separate	O
data	O
items	O
(	O
e.g.	O
</s>
<s>
arrays	O
,	O
structures	O
,	O
code	O
units	O
)	O
to	O
be	O
contained	O
in	O
separate	O
segments	O
and	O
addressed	O
by	O
their	O
own	O
segment	O
addresses	O
,	O
in	O
new	O
programs	O
that	O
are	O
not	O
ported	O
from	O
earlier	O
8-bit	O
processors	B-General_Concept
with	O
16-bit	B-Device
address	B-General_Concept
spaces	I-General_Concept
.	O
</s>
<s>
Unreal	O
mode	O
is	O
used	O
by	O
some	O
16-bit	B-Device
operating	B-General_Concept
systems	I-General_Concept
and	O
some	O
32-bit	O
boot	B-Operating_System
loaders	I-Operating_System
.	O
</s>
<s>
The	O
System	O
Management	O
Mode	O
(	O
SMM	O
)	O
is	O
only	O
used	O
by	O
the	O
system	O
firmware	O
(	O
BIOS/UEFI	O
)	O
,	O
not	O
by	O
operating	B-General_Concept
systems	I-General_Concept
and	O
applications	O
software	O
.	O
</s>
<s>
In	O
addition	O
to	O
real	B-Application
mode	I-Application
,	O
the	O
Intel	B-General_Concept
80286	I-General_Concept
supports	O
protected	B-Application
mode	I-Application
,	O
expanding	O
addressable	O
physical	B-General_Concept
memory	O
to	O
16	O
MB	O
and	O
addressable	O
virtual	B-Architecture
memory	I-Architecture
to	O
1GB	O
,	O
and	O
providing	O
protected	B-General_Concept
memory	I-General_Concept
,	O
which	O
prevents	O
programs	O
from	O
corrupting	O
one	O
another	O
.	O
</s>
<s>
This	O
is	O
done	O
by	O
using	O
the	O
segment	B-Device
registers	I-Device
only	O
for	O
storing	O
an	O
index	O
into	O
a	O
descriptor	O
table	O
that	O
is	O
stored	O
in	O
memory	O
.	O
</s>
<s>
There	O
are	O
two	O
such	O
tables	O
,	O
the	O
Global	B-General_Concept
Descriptor	I-General_Concept
Table	I-General_Concept
(	O
GDT	O
)	O
and	O
the	O
Local	B-General_Concept
Descriptor	I-General_Concept
Table	I-General_Concept
(	O
LDT	O
)	O
,	O
each	O
holding	O
up	O
to	O
8192	O
segment	O
descriptors	O
,	O
each	O
segment	O
giving	O
access	O
to	O
64KB	O
of	O
memory	O
.	O
</s>
<s>
In	O
the	O
80286	B-General_Concept
,	O
a	O
segment	O
descriptor	O
provides	O
a	O
24-bit	O
base	B-General_Concept
address	I-General_Concept
,	O
and	O
this	O
base	B-General_Concept
address	I-General_Concept
is	O
added	O
to	O
a	O
16-bit	B-Device
offset	B-General_Concept
to	O
create	O
an	O
absolute	O
address	O
.	O
</s>
<s>
The	O
base	B-General_Concept
address	I-General_Concept
from	O
the	O
table	O
fulfills	O
the	O
same	O
role	O
that	O
the	O
literal	O
value	O
of	O
the	O
segment	O
register	O
fulfills	O
in	O
real	B-Application
mode	I-Application
;	O
the	O
segment	B-Device
registers	I-Device
have	O
been	O
converted	O
from	O
direct	O
registers	O
to	O
indirect	O
registers	O
.	O
</s>
<s>
Each	O
segment	O
can	O
be	O
assigned	O
one	O
of	O
four	O
ring	B-Operating_System
levels	O
used	O
for	O
hardware-based	O
computer	O
security	O
.	O
</s>
<s>
Each	O
segment	O
descriptor	O
also	O
contains	O
a	O
segment	O
limit	O
field	O
which	O
specifies	O
the	O
maximum	O
offset	B-General_Concept
that	O
may	O
be	O
used	O
with	O
the	O
segment	O
.	O
</s>
<s>
Because	O
offsets	B-General_Concept
are	O
16	B-Device
bits	I-Device
,	O
segments	O
are	O
still	O
limited	O
to	O
64KB	O
each	O
in	O
80286	B-General_Concept
protected	B-Application
mode	I-Application
.	O
</s>
<s>
Each	O
time	O
a	O
segment	O
register	O
is	O
loaded	O
in	O
protected	B-Application
mode	I-Application
,	O
the	O
80286	B-General_Concept
must	O
read	O
a	O
6-byte	O
segment	O
descriptor	O
from	O
memory	O
into	O
a	O
set	O
of	O
hidden	O
internal	O
registers	O
.	O
</s>
<s>
Thus	O
,	O
loading	O
segment	B-Device
registers	I-Device
is	O
much	O
slower	O
in	O
protected	B-Application
mode	I-Application
than	O
in	O
real	B-Application
mode	I-Application
,	O
and	O
changing	O
segments	O
very	O
frequently	O
is	O
to	O
be	O
avoided	O
.	O
</s>
<s>
Actual	O
memory	O
operations	O
using	O
protected	B-Application
mode	I-Application
segments	O
are	O
not	O
slowed	O
much	O
because	O
the	O
80286	B-General_Concept
and	O
later	O
have	O
hardware	B-Architecture
to	O
check	O
the	O
offset	B-General_Concept
against	O
the	O
segment	O
limit	O
in	O
parallel	O
with	O
instruction	O
execution	B-General_Concept
.	O
</s>
<s>
The	O
Intel	B-General_Concept
80386	I-General_Concept
extended	O
offsets	B-General_Concept
and	O
also	O
the	O
segment	O
limit	O
field	O
in	O
each	O
segment	O
descriptor	O
to	O
32	O
bits	O
,	O
enabling	O
a	O
segment	O
to	O
span	O
the	O
entire	O
memory	O
space	O
.	O
</s>
<s>
It	O
also	O
introduced	O
support	O
in	O
protected	B-Application
mode	I-Application
for	O
paging	B-Architecture
,	O
a	O
mechanism	O
making	O
it	O
possible	O
to	O
use	O
paged	O
virtual	B-Architecture
memory	I-Architecture
(	O
with	O
4KB	O
page	O
size	O
)	O
.	O
</s>
<s>
Paging	B-Architecture
allows	O
the	O
CPU	O
to	O
map	O
any	O
page	O
of	O
the	O
virtual	B-Architecture
memory	I-Architecture
space	O
to	O
any	O
page	O
of	O
the	O
physical	B-General_Concept
memory	O
space	O
.	O
</s>
<s>
Protected	B-Application
mode	I-Application
on	O
the	O
80386	B-General_Concept
can	O
operate	O
with	O
paging	B-Architecture
either	O
enabled	O
or	O
disabled	O
;	O
the	O
segmentation	O
mechanism	O
is	O
always	O
active	O
and	O
generates	O
virtual	B-General_Concept
addresses	O
that	O
are	O
then	O
mapped	O
by	O
the	O
paging	B-Architecture
mechanism	O
if	O
it	O
is	O
enabled	O
.	O
</s>
<s>
The	O
segmentation	O
mechanism	O
can	O
also	O
be	O
effectively	O
disabled	O
by	O
setting	O
all	O
segments	O
to	O
have	O
a	O
base	B-General_Concept
address	I-General_Concept
of	O
0	O
and	O
size	O
limit	O
equal	O
to	O
the	O
whole	O
address	B-General_Concept
space	I-General_Concept
;	O
this	O
also	O
requires	O
a	O
minimally-sized	O
segment	O
descriptor	O
table	O
of	O
only	O
four	O
descriptors	O
(	O
since	O
the	O
FS	B-Device
and	I-Device
GS	I-Device
segments	O
need	O
not	O
be	O
used	O
)	O
.	O
</s>
<s>
Paging	B-Architecture
is	O
used	O
extensively	O
by	O
modern	O
multitasking	B-Operating_System
operating	I-Operating_System
systems	I-Operating_System
.	O
</s>
<s>
Linux	B-Application
,	O
386BSD	B-Operating_System
and	O
Windows	B-Device
NT	I-Device
were	O
developed	O
for	O
the	O
386	B-General_Concept
because	O
it	O
was	O
the	O
first	O
Intel	O
architecture	O
CPU	O
to	O
support	O
paging	B-Architecture
and	O
32-bit	O
segment	O
offsets	B-General_Concept
.	O
</s>
<s>
The	O
386	B-General_Concept
architecture	O
became	O
the	O
basis	O
of	O
all	O
further	O
development	O
in	O
the	O
x86	B-Operating_System
series	O
.	O
</s>
<s>
x86	B-Operating_System
processors	B-General_Concept
that	O
support	O
protected	B-Application
mode	I-Application
boot	B-Operating_System
into	O
real	B-Application
mode	I-Application
for	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
the	O
older	O
8086	B-General_Concept
class	O
of	O
processors	B-General_Concept
.	O
</s>
<s>
booting	B-Operating_System
)	O
,	O
the	O
processor	O
initializes	O
in	O
real	B-Application
mode	I-Application
,	O
and	O
then	O
begins	O
executing	O
instructions	O
.	O
</s>
<s>
Operating	B-General_Concept
system	I-General_Concept
boot	B-Operating_System
code	O
,	O
which	O
might	O
be	O
stored	O
in	O
read-only	B-Device
memory	I-Device
,	O
may	O
place	O
the	O
processor	O
into	O
the	O
protected	B-Application
mode	I-Application
to	O
enable	O
paging	B-Architecture
and	O
other	O
features	O
)	O
.	O
</s>
<s>
do	O
not	O
apply	O
in	O
protected	B-Application
mode	I-Application
.	O
</s>
<s>
Conversely	O
,	O
segment	O
arithmetic	O
,	O
a	O
common	O
practice	O
in	O
real	B-Application
mode	I-Application
code	O
,	O
is	O
not	O
allowed	O
in	O
protected	B-Application
mode	I-Application
.	O
</s>
<s>
There	O
is	O
also	O
a	O
sub-mode	O
of	O
operation	O
in	O
32-bit	O
protected	B-Application
mode	I-Application
(	O
a.k.a.	O
</s>
<s>
80386	B-General_Concept
protected	B-Application
mode	I-Application
)	O
called	O
virtual	B-Application
8086	I-Application
mode	I-Application
,	O
also	O
known	O
as	O
V86	B-Application
mode	I-Application
.	O
</s>
<s>
This	O
is	O
basically	O
a	O
special	O
hybrid	O
operating	O
mode	O
that	O
allows	O
real	B-Application
mode	I-Application
programs	O
and	O
operating	B-General_Concept
systems	I-General_Concept
to	O
run	O
while	O
under	O
the	O
control	O
of	O
a	O
protected	B-Application
mode	I-Application
supervisor	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
This	O
allows	O
for	O
a	O
great	O
deal	O
of	O
flexibility	O
in	O
running	O
both	O
protected	B-Application
mode	I-Application
programs	O
and	O
real	B-Application
mode	I-Application
programs	O
simultaneously	O
.	O
</s>
<s>
This	O
mode	O
is	O
exclusively	O
available	O
for	O
the	O
32-bit	O
version	O
of	O
protected	B-Application
mode	I-Application
;	O
it	O
does	O
not	O
exist	O
in	O
the	O
16-bit	B-Device
version	O
of	O
protected	B-Application
mode	I-Application
,	O
or	O
in	O
long	B-Application
mode	I-Application
.	O
</s>
<s>
In	O
the	O
mid	O
1990s	O
,	O
it	O
was	O
obvious	O
that	O
the	O
32-bit	O
address	B-General_Concept
space	I-General_Concept
of	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
was	O
limiting	O
its	O
performance	O
in	O
applications	O
requiring	O
large	O
data	O
sets	O
.	O
</s>
<s>
A	O
32-bit	O
address	B-General_Concept
space	I-General_Concept
would	O
allow	O
the	O
processor	O
to	O
directly	O
address	O
only	O
4GB	O
of	O
data	O
,	O
a	O
size	O
surpassed	O
by	O
applications	O
such	O
as	O
video	O
processing	O
and	O
database	B-General_Concept
engines	I-General_Concept
.	O
</s>
<s>
Using	O
64-bit	B-Device
addresses	O
,	O
it	O
is	O
possible	O
to	O
directly	O
address	O
16EiB	O
of	O
data	O
,	O
although	O
most	O
64-bit	B-Device
architectures	I-Device
do	O
not	O
support	O
access	O
to	O
the	O
full	O
64-bit	B-Device
address	B-General_Concept
space	I-General_Concept
;	O
for	O
example	O
,	O
AMD64	B-Device
supports	O
only	O
48bits	O
from	O
a	O
64-bit	B-Device
address	O
,	O
split	O
into	O
four	O
paging	B-Architecture
levels	O
.	O
</s>
<s>
In	O
1999	O
,	O
AMD	O
published	O
a	O
(	O
nearly	O
)	O
complete	O
specification	O
for	O
a	O
64-bit	B-Device
extension	O
of	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
which	O
they	O
called	O
x86-64	B-Device
with	O
claimed	O
intentions	O
to	O
produce	O
.	O
</s>
<s>
That	O
design	O
is	O
currently	O
used	O
in	O
almost	O
all	O
x86	B-Operating_System
processors	B-General_Concept
,	O
with	O
some	O
exceptions	O
intended	O
for	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
Mass-produced	O
x86-64	B-Device
chips	O
for	O
the	O
general	O
market	O
were	O
available	O
four	O
years	O
later	O
,	O
in	O
2003	O
,	O
after	O
the	O
time	O
was	O
spent	O
for	O
working	O
prototypes	O
to	O
be	O
tested	O
and	O
refined	O
;	O
about	O
the	O
same	O
time	O
,	O
the	O
initial	O
name	O
x86-64	B-Device
was	O
changed	O
to	O
AMD64	B-Device
.	O
</s>
<s>
The	O
success	O
of	O
the	O
AMD64	B-Device
line	O
of	O
processors	B-General_Concept
coupled	O
with	O
lukewarm	O
reception	O
of	O
the	O
IA-64	B-General_Concept
architecture	O
forced	O
Intel	O
to	O
release	O
its	O
own	O
implementation	O
of	O
the	O
AMD64	B-Device
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Intel	O
had	O
previously	O
implemented	O
support	O
for	O
AMD64	B-Device
but	O
opted	O
not	O
to	O
enable	O
it	O
in	O
hopes	O
that	O
AMD	O
would	O
not	O
bring	O
AMD64	B-Device
to	O
market	O
before	O
Itanium	B-General_Concept
's	O
new	O
IA-64	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
was	O
widely	O
adopted	O
.	O
</s>
<s>
It	O
branded	O
its	O
implementation	O
of	O
AMD64	B-Device
as	O
EM64T	B-Device
,	O
and	O
later	O
rebranded	O
it	O
Intel	O
64	O
.	O
</s>
<s>
In	O
its	O
literature	O
and	O
product	O
version	O
names	O
,	O
Microsoft	O
and	O
Sun	O
refer	O
to	O
AMD64/Intel	O
64	O
collectively	O
as	O
x64	B-Device
in	O
the	O
Windows	O
and	O
Solaris	B-Application
operating	I-Application
systems	I-Application
.	O
</s>
<s>
Linux	B-Application
distributions	I-Application
refer	O
to	O
it	O
either	O
as	O
"	O
x86-64	B-Device
"	O
,	O
its	O
variant	O
"	O
x86_64	O
"	O
,	O
or	O
"	O
amd64	B-Device
"	O
.	O
</s>
<s>
BSD	B-Operating_System
systems	O
use	O
"	O
amd64	B-Device
"	O
while	O
macOS	B-Application
uses	O
"	O
x86_64	O
"	O
.	O
</s>
<s>
Long	B-Application
mode	I-Application
is	O
mostly	O
an	O
extension	O
of	O
the	O
32-bit	O
instruction	B-General_Concept
set	I-General_Concept
,	O
but	O
unlike	O
the	O
16	O
–	O
to	O
–	O
32-bit	O
transition	O
,	O
many	O
instructions	O
were	O
dropped	O
in	O
the	O
64-bit	B-Device
mode	O
.	O
</s>
<s>
This	O
does	O
not	O
affect	O
actual	O
binary	O
backward	B-General_Concept
compatibility	I-General_Concept
(	O
which	O
would	O
execute	O
legacy	O
code	O
in	O
other	O
modes	O
that	O
retain	O
support	O
for	O
those	O
instructions	O
)	O
,	O
but	O
it	O
changes	O
the	O
way	O
assembler	O
and	O
compilers	O
for	O
new	O
code	O
have	O
to	O
work	O
.	O
</s>
<s>
This	O
was	O
the	O
first	O
time	O
that	O
a	O
major	O
extension	O
of	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
was	O
initiated	O
and	O
originated	O
by	O
a	O
manufacturer	O
other	O
than	O
Intel	O
.	O
</s>
<s>
Early	O
x86	B-Operating_System
processors	B-General_Concept
could	O
be	O
extended	O
with	O
floating-point	B-Algorithm
hardware	B-Architecture
in	O
the	O
form	O
of	O
a	O
series	O
of	O
floating-point	B-Algorithm
numerical	B-General_Concept
co-processors	B-General_Concept
with	O
names	O
like	O
8087	B-Device
,	O
80287	O
and	O
80387	O
,	O
abbreviated	O
x87	B-Application
.	O
</s>
<s>
This	O
was	O
also	O
known	O
as	O
the	O
NPX	B-Application
(	O
Numeric	B-Application
Processor	I-Application
eXtension	I-Application
)	O
,	O
an	O
apt	O
name	O
since	O
the	O
coprocessors	B-General_Concept
,	O
while	O
used	O
mainly	O
for	O
floating-point	B-Algorithm
calculations	O
,	O
also	O
performed	O
integer	O
operations	O
on	O
both	O
binary	O
and	O
decimal	O
formats	O
.	O
</s>
<s>
With	O
very	O
few	O
exceptions	O
,	O
the	O
80486	B-General_Concept
and	O
subsequent	O
x86	B-Operating_System
processors	B-General_Concept
then	O
integrated	O
this	O
x87	B-Application
functionality	O
on	O
chip	O
which	O
made	O
the	O
x87	B-Application
instructions	O
a	O
de	O
facto	O
integral	O
part	O
of	O
the	O
x86	B-Device
instruction	I-Device
set	I-Device
.	O
</s>
<s>
Each	O
x87	B-Application
register	O
,	O
known	O
as	O
ST(0 )	O
through	O
ST(7 )	O
,	O
is	O
80bits	O
wide	O
and	O
stores	O
numbers	O
in	O
the	O
IEEE	O
floating-point	B-Algorithm
standard	O
double	O
extended	O
precision	O
format	O
.	O
</s>
<s>
These	O
registers	O
are	O
organized	O
as	O
a	O
stack	B-Application
with	O
ST(0 )	O
as	O
the	O
top	O
.	O
</s>
<s>
This	O
was	O
done	O
in	O
order	O
to	O
conserve	O
opcode	B-Language
space	O
,	O
and	O
the	O
registers	O
are	O
therefore	O
randomly	O
accessible	O
only	O
for	O
either	O
operand	O
in	O
a	O
register-to-register	O
instruction	O
;	O
ST0	O
must	O
always	O
be	O
one	O
of	O
the	O
two	O
operands	O
,	O
either	O
the	O
source	O
or	O
the	O
destination	O
,	O
regardless	O
of	O
whether	O
the	O
other	O
operand	O
is	O
ST(x )	O
or	O
a	O
memory	O
operand	O
.	O
</s>
<s>
However	O
,	O
random	O
access	O
to	O
the	O
stack	B-Application
registers	O
can	O
be	O
obtained	O
through	O
an	O
instruction	O
which	O
exchanges	O
any	O
specified	O
ST(x )	O
with	O
ST(0 )	O
.	O
</s>
<s>
The	O
operations	O
include	O
arithmetic	O
and	O
transcendental	O
functions	O
,	O
including	O
trigonometric	O
and	O
exponential	O
functions	O
,	O
and	O
instructions	O
that	O
load	O
common	O
constants	O
(	O
such	O
as	O
0	O
;	O
1	O
;	O
e	O
,	O
the	O
base	O
of	O
the	O
natural	O
logarithm	O
;	O
log2(10 )	O
;	O
and	O
log10(2 )	O
)	O
into	O
one	O
of	O
the	O
stack	B-Application
registers	O
.	O
</s>
<s>
While	O
the	O
integer	O
ability	O
is	O
often	O
overlooked	O
,	O
the	O
x87	B-Application
can	O
operate	O
on	O
larger	O
integers	O
with	O
a	O
single	O
instruction	O
than	O
the	O
8086	B-General_Concept
,	O
80286	B-General_Concept
,	O
80386	B-General_Concept
,	O
or	O
any	O
x86	B-Operating_System
CPU	O
without	O
to	O
64-bit	B-Device
extensions	O
can	O
,	O
and	O
repeated	O
integer	O
calculations	O
even	O
on	O
small	O
values	O
(	O
e.g.	O
,	O
16-bit	B-Device
)	O
can	O
be	O
accelerated	O
by	O
executing	O
integer	O
instructions	O
on	O
the	O
x86	B-Operating_System
CPU	O
and	O
the	O
x87	B-Application
in	O
parallel	O
.	O
</s>
<s>
(	O
The	O
x86	B-Operating_System
CPU	O
keeps	O
running	O
while	O
the	O
x87	B-Application
coprocessor	B-General_Concept
calculates	O
,	O
and	O
the	O
x87	B-Application
sets	O
a	O
signal	O
to	O
the	O
x86	B-Operating_System
when	O
it	O
is	O
finished	O
or	O
interrupts	B-Application
the	O
x86	B-Operating_System
if	O
it	O
needs	O
attention	O
because	O
of	O
an	O
error	O
.	O
)	O
</s>
<s>
MMX	B-Architecture
is	O
a	O
SIMD	B-Device
instruction	B-General_Concept
set	I-General_Concept
designed	O
by	O
Intel	O
and	O
introduced	O
in	O
1997	O
for	O
the	O
Pentium	B-General_Concept
MMX	B-Architecture
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
MMX	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
was	O
developed	O
from	O
a	O
similar	O
concept	O
first	O
used	O
on	O
the	O
Intel	B-General_Concept
i860	I-General_Concept
.	O
</s>
<s>
It	O
is	O
supported	O
on	O
most	O
subsequent	O
IA-32	B-Device
processors	B-General_Concept
by	O
Intel	O
and	O
other	O
vendors	O
.	O
</s>
<s>
MMX	B-Architecture
is	O
typically	O
used	O
for	O
video	O
processing	O
(	O
in	O
multimedia	O
applications	O
,	O
for	O
instance	O
)	O
.	O
</s>
<s>
MMX	B-Architecture
added	O
8	O
new	O
registers	O
to	O
the	O
architecture	O
,	O
known	O
as	O
MM0	O
through	O
MM7	O
(	O
henceforth	O
referred	O
to	O
as	O
MMn	O
)	O
.	O
</s>
<s>
In	O
reality	O
,	O
these	O
new	O
registers	O
were	O
just	O
aliases	O
for	O
the	O
existing	O
x87	B-Application
FPU	I-Application
stack	B-Application
registers	O
.	O
</s>
<s>
Hence	O
,	O
anything	O
that	O
was	O
done	O
to	O
the	O
floating-point	B-Algorithm
stack	B-Application
would	O
also	O
affect	O
the	O
MMX	B-Architecture
registers	O
.	O
</s>
<s>
Unlike	O
the	O
FP	O
stack	B-Application
,	O
these	O
MMn	O
registers	O
were	O
fixed	O
,	O
not	O
relative	O
,	O
and	O
therefore	O
they	O
were	O
randomly	O
accessible	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
did	O
not	O
adopt	O
the	O
stack-like	O
semantics	O
so	O
that	O
existing	O
operating	B-General_Concept
systems	I-General_Concept
could	O
still	O
correctly	O
save	O
and	O
restore	O
the	O
register	O
state	O
when	O
multitasking	B-Operating_System
without	O
modifications	O
.	O
</s>
<s>
Each	O
of	O
the	O
MMn	O
registers	O
are	O
64-bit	B-Device
integers	O
.	O
</s>
<s>
However	O
,	O
one	O
of	O
the	O
main	O
concepts	O
of	O
the	O
MMX	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
is	O
the	O
concept	O
of	O
packed	O
data	O
types	O
,	O
which	O
means	O
instead	O
of	O
using	O
the	O
whole	O
register	O
for	O
a	O
single	O
64-bit	B-Device
integer	O
(	O
quadword	O
)	O
,	O
one	O
may	O
use	O
it	O
to	O
contain	O
two	O
32-bit	O
integers	O
(	O
doubleword	O
)	O
,	O
four	O
16-bit	B-Device
integers	O
(	O
word	O
)	O
or	O
eight	O
8-bit	O
integers	O
(	O
byte	O
)	O
.	O
</s>
<s>
Given	O
that	O
the	O
MMX	B-Architecture
's	O
64-bit	B-Device
MMn	O
registers	O
are	O
aliased	O
to	O
the	O
FPU	B-General_Concept
stack	B-Application
and	O
each	O
of	O
the	O
floating-point	B-Algorithm
registers	O
are	O
80bits	O
wide	O
,	O
the	O
upper	O
16bits	O
of	O
the	O
floating-point	B-Algorithm
registers	O
are	O
unused	O
in	O
MMX	B-Architecture
.	O
</s>
<s>
These	O
bits	O
are	O
set	O
to	O
all	O
ones	O
by	O
any	O
MMX	B-Architecture
instruction	O
,	O
which	O
correspond	O
to	O
the	O
floating-point	B-Algorithm
representation	I-Algorithm
of	O
NaNs	O
or	O
infinities	O
.	O
</s>
<s>
In	O
1997	O
,	O
AMD	O
introduced	O
3DNow	B-General_Concept
!	I-General_Concept
.	O
</s>
<s>
The	O
introduction	O
of	O
this	O
technology	O
coincided	O
with	O
the	O
rise	O
of	O
3D	O
entertainment	O
applications	O
and	O
was	O
designed	O
to	O
improve	O
the	O
CPU	O
's	O
vector	B-Operating_System
processing	I-Operating_System
performance	O
of	O
graphic-intensive	O
applications	O
.	O
</s>
<s>
3D	O
video	O
game	O
developers	O
and	O
3D	O
graphics	O
hardware	B-Architecture
vendors	O
use	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
to	O
enhance	O
their	O
performance	O
on	O
AMD	O
's	O
K6	B-Architecture
and	O
Athlon	B-Architecture
series	O
of	O
processors	B-General_Concept
.	O
</s>
<s>
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
was	O
designed	O
to	O
be	O
the	O
natural	O
evolution	O
of	O
MMX	B-Architecture
from	O
integers	O
to	O
floating	B-Algorithm
point	I-Algorithm
.	O
</s>
<s>
As	O
such	O
,	O
it	O
uses	O
exactly	O
the	O
same	O
register	O
naming	O
convention	O
as	O
MMX	B-Architecture
,	O
that	O
is	O
MM0	O
through	O
MM7	O
.	O
</s>
<s>
The	O
only	O
difference	O
is	O
that	O
instead	O
of	O
packing	O
integers	O
into	O
these	O
registers	O
,	O
two	O
single-precision	O
floating-point	B-Algorithm
numbers	I-Algorithm
are	O
packed	O
into	O
each	O
register	O
.	O
</s>
<s>
The	O
advantage	O
of	O
aliasing	O
the	O
FPU	B-General_Concept
registers	O
is	O
that	O
the	O
same	O
instruction	O
and	O
data	O
structures	O
used	O
to	O
save	O
the	O
state	O
of	O
the	O
FPU	B-General_Concept
registers	O
can	O
also	O
be	O
used	O
to	O
save	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
Thus	O
no	O
special	O
modifications	O
are	O
required	O
to	O
be	O
made	O
to	O
operating	B-General_Concept
systems	I-General_Concept
which	O
would	O
otherwise	O
not	O
know	O
about	O
them	O
.	O
</s>
<s>
In	O
1999	O
,	O
Intel	O
introduced	O
the	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
(	O
SSE	B-General_Concept
)	O
instruction	B-General_Concept
set	I-General_Concept
,	O
following	O
in	O
2000	O
with	O
SSE2	B-General_Concept
.	O
</s>
<s>
The	O
first	O
addition	O
allowed	O
offloading	O
of	O
basic	O
floating-point	B-Algorithm
operations	O
from	O
the	O
x87	B-Application
stack	B-Application
and	O
the	O
second	O
made	O
MMX	B-Architecture
almost	O
obsolete	O
and	O
allowed	O
the	O
instructions	O
to	O
be	O
realistically	O
targeted	O
by	O
conventional	O
compilers	O
.	O
</s>
<s>
Introduced	O
in	O
2004	O
along	O
with	O
the	O
Prescott	O
revision	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
processor	O
,	O
SSE3	B-General_Concept
added	O
specific	O
memory	O
and	O
thread-handling	O
instructions	O
to	O
boost	O
the	O
performance	O
of	O
Intel	O
's	O
HyperThreading	B-Operating_System
technology	O
.	O
</s>
<s>
AMD	O
licensed	O
the	O
SSE3	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
and	O
implemented	O
most	O
of	O
the	O
SSE3	B-General_Concept
instructions	O
for	O
its	O
revision	O
E	O
and	O
later	O
Athlon	B-Architecture
64	O
processors	B-General_Concept
.	O
</s>
<s>
The	O
Athlon	B-Architecture
64	O
does	O
not	O
support	O
HyperThreading	B-Operating_System
and	O
lacks	O
those	O
SSE3	B-General_Concept
instructions	O
used	O
only	O
for	O
HyperThreading	B-Operating_System
.	O
</s>
<s>
SSE	B-General_Concept
discarded	O
all	O
legacy	O
connections	O
to	O
the	O
FPU	B-General_Concept
stack	B-Application
.	O
</s>
<s>
This	O
also	O
meant	O
that	O
this	O
instruction	B-General_Concept
set	I-General_Concept
discarded	O
all	O
legacy	O
connections	O
to	O
previous	O
generations	O
of	O
SIMD	B-Device
instruction	B-General_Concept
sets	I-General_Concept
like	O
MMX	B-Architecture
.	O
</s>
<s>
But	O
it	O
freed	O
the	O
designers	O
up	O
,	O
allowing	O
them	O
to	O
use	O
larger	O
registers	O
,	O
not	O
limited	O
by	O
the	O
size	O
of	O
the	O
FPU	B-General_Concept
registers	O
.	O
</s>
<s>
(	O
In	O
AMD64	B-Device
,	O
the	O
number	O
of	O
SSE	B-General_Concept
XMM	O
registers	O
has	O
been	O
increased	O
from	O
8	O
to	O
16	O
.	O
)	O
</s>
<s>
However	O
,	O
the	O
downside	O
was	O
that	O
operating	B-General_Concept
systems	I-General_Concept
had	O
to	O
have	O
an	O
awareness	O
of	O
this	O
new	O
set	O
of	O
instructions	O
in	O
order	O
to	O
be	O
able	O
to	O
save	O
their	O
register	O
states	O
.	O
</s>
<s>
So	O
Intel	O
created	O
a	O
slightly	O
modified	O
version	O
of	O
Protected	B-Application
mode	I-Application
,	O
called	O
Enhanced	O
mode	O
which	O
enables	O
the	O
usage	O
of	O
SSE	B-General_Concept
instructions	I-General_Concept
,	O
whereas	O
they	O
stay	O
disabled	O
in	O
regular	O
Protected	B-Application
mode	I-Application
.	O
</s>
<s>
An	O
OS	O
that	O
is	O
aware	O
of	O
SSE	B-General_Concept
will	O
activate	O
Enhanced	O
mode	O
,	O
whereas	O
an	O
unaware	O
OS	O
will	O
only	O
enter	O
into	O
traditional	O
Protected	B-Application
mode	I-Application
.	O
</s>
<s>
SSE	B-General_Concept
is	O
a	O
SIMD	B-Device
instruction	B-General_Concept
set	I-General_Concept
that	O
works	O
only	O
on	O
floating-point	B-Algorithm
values	O
,	O
like	O
3DNow	B-General_Concept
!	I-General_Concept
.	O
</s>
<s>
However	O
,	O
unlike	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
it	O
severs	O
all	O
legacy	O
connection	O
to	O
the	O
FPU	B-General_Concept
stack	B-Application
.	O
</s>
<s>
Because	O
it	O
has	O
larger	O
registers	O
than	O
3DNow	O
!,	O
SSE	B-General_Concept
can	O
pack	O
twice	O
the	O
number	O
of	O
single	O
precision	O
floats	B-Algorithm
into	O
its	O
registers	O
.	O
</s>
<s>
The	O
original	O
SSE	B-General_Concept
was	O
limited	O
to	O
only	O
single-precision	O
numbers	O
,	O
like	O
3DNow	B-General_Concept
!	I-General_Concept
.	O
</s>
<s>
The	O
SSE2	B-General_Concept
introduced	O
the	O
capability	O
to	O
pack	O
double	O
precision	O
numbers	O
too	O
,	O
which	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
had	O
no	O
possibility	O
of	O
doing	O
since	O
a	O
double	O
precision	O
number	O
is	O
64-bit	B-Device
in	O
size	O
which	O
would	O
be	O
the	O
full	O
size	O
of	O
a	O
single	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
At	O
128bits	O
,	O
the	O
SSE	B-General_Concept
XMMn	O
registers	O
could	O
pack	O
two	O
double	O
precision	O
floats	B-Algorithm
into	O
one	O
register	O
.	O
</s>
<s>
Thus	O
SSE2	B-General_Concept
is	O
much	O
more	O
suitable	O
for	O
scientific	O
calculations	O
than	O
either	O
SSE1	B-General_Concept
or	O
3DNow	O
!,	O
which	O
were	O
limited	O
to	O
only	O
single	O
precision	O
.	O
</s>
<s>
SSE3	B-General_Concept
does	O
not	O
introduce	O
any	O
additional	O
registers	O
.	O
</s>
<s>
The	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
(	O
AVX	B-General_Concept
)	O
doubled	O
the	O
size	O
of	O
SSE	B-General_Concept
registers	O
to	O
256-bit	O
YMM	O
registers	O
.	O
</s>
<s>
AVX2	O
did	O
not	O
introduce	O
extra	O
registers	O
,	O
but	O
was	O
notable	O
for	O
the	O
addition	O
for	O
masking	O
,	O
gather	B-General_Concept
,	O
and	O
shuffle	O
instructions	O
.	O
</s>
<s>
AVX-512	B-General_Concept
features	O
yet	O
another	O
expansion	O
to	O
32	O
512-bit	O
ZMM	O
registers	O
and	O
a	O
new	O
EVEX	O
scheme	O
.	O
</s>
<s>
Unlike	O
its	O
predecessors	O
featuring	O
a	O
monolithic	O
extension	O
,	O
it	O
is	O
divided	O
into	O
many	O
subsets	O
that	O
specific	O
models	O
of	O
CPUs	B-General_Concept
can	O
choose	O
to	O
implement	O
.	O
</s>
<s>
Physical	B-General_Concept
Address	I-General_Concept
Extension	I-General_Concept
or	O
PAE	B-General_Concept
was	O
first	O
added	O
in	O
the	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
,	O
and	O
later	O
by	O
AMD	O
in	O
the	O
Athlon	B-Architecture
processors	B-General_Concept
,	O
to	O
allow	O
up	O
to	O
64GB	O
of	O
RAM	O
to	O
be	O
addressed	O
.	O
</s>
<s>
Without	O
PAE	B-General_Concept
,	O
physical	B-General_Concept
RAM	O
in	O
32-bit	O
protected	B-Application
mode	I-Application
is	O
usually	O
limited	O
to	O
4GB	O
.	O
</s>
<s>
PAE	B-General_Concept
defines	O
a	O
different	O
page	O
table	O
structure	O
with	O
wider	O
page	O
table	O
entries	O
and	O
a	O
third	O
level	O
of	O
page	O
table	O
,	O
allowing	O
additional	O
bits	O
of	O
physical	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
Although	O
the	O
initial	O
implementations	O
on	O
32-bit	O
processors	B-General_Concept
theoretically	O
supported	O
up	O
to	O
64GB	O
of	O
RAM	O
,	O
chipset	O
and	O
other	O
platform	O
limitations	O
often	O
restricted	O
what	O
could	O
actually	O
be	O
used	O
.	O
</s>
<s>
x86-64	B-Device
processors	B-General_Concept
define	O
page	O
table	O
structures	O
that	O
theoretically	O
allow	O
up	O
to	O
52	O
bits	O
of	O
physical	B-General_Concept
address	I-General_Concept
,	O
although	O
again	O
,	O
chipset	O
and	O
other	O
platform	O
concerns	O
(	O
like	O
the	O
number	O
of	O
DIMM	O
slots	O
available	O
,	O
and	O
the	O
maximum	O
RAM	O
possible	O
per	O
DIMM	O
)	O
prevent	O
such	O
a	O
large	O
physical	B-General_Concept
address	I-General_Concept
space	O
to	O
be	O
realized	O
.	O
</s>
<s>
On	O
x86-64	B-Device
processors	B-General_Concept
PAE	B-General_Concept
mode	O
must	O
be	O
active	O
before	O
the	O
switch	O
to	O
long	B-Application
mode	I-Application
,	O
and	O
must	O
remain	O
active	O
while	O
long	B-Application
mode	I-Application
is	O
active	O
,	O
so	O
while	O
in	O
long	B-Application
mode	I-Application
there	O
is	O
no	O
"	O
non-PAE	O
"	O
mode	O
.	O
</s>
<s>
PAE	B-General_Concept
mode	O
does	O
not	O
affect	O
the	O
width	O
of	O
linear	B-General_Concept
or	O
virtual	B-General_Concept
addresses	O
.	O
</s>
<s>
By	O
the	O
2000s	O
,	O
32-bit	B-Device
x86	I-Device
processors	B-General_Concept
 '	O
limits	O
in	O
memory	O
addressing	O
were	O
an	O
obstacle	O
to	O
their	O
use	O
in	O
high-performance	B-Architecture
computing	I-Architecture
clusters	O
and	O
powerful	O
desktop	B-Device
workstations	B-Device
.	O
</s>
<s>
The	O
aged	O
32-bit	B-Device
x86	I-Device
was	O
competing	O
with	O
much	O
more	O
advanced	O
64-bit	B-Device
RISC	B-Architecture
architectures	I-Architecture
which	O
could	O
address	O
much	O
more	O
memory	O
.	O
</s>
<s>
Intel	O
and	O
the	O
whole	O
x86	B-Operating_System
ecosystem	O
needed	O
64-bit	B-Device
memory	O
addressing	O
if	O
x86	B-Operating_System
was	O
to	O
survive	O
the	O
64-bit	B-Device
computing	I-Device
era	O
,	O
as	O
workstation	B-Device
and	O
desktop	B-Device
software	O
applications	O
were	O
soon	O
to	O
start	O
hitting	O
the	O
limits	O
of	O
32-bit	O
memory	O
addressing	O
.	O
</s>
<s>
However	O
,	O
Intel	O
felt	O
that	O
it	O
was	O
the	O
right	O
time	O
to	O
make	O
a	O
bold	O
step	O
and	O
use	O
the	O
transition	O
to	O
64-bit	B-Device
desktop	B-Device
computers	I-Device
for	O
a	O
transition	O
away	O
from	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
in	O
general	O
,	O
an	O
experiment	O
which	O
ultimately	O
failed	O
.	O
</s>
<s>
In	O
2001	O
,	O
Intel	O
attempted	O
to	O
introduce	O
a	O
non-x86	O
64-bit	O
architecture	O
named	O
IA-64	B-General_Concept
in	O
its	O
Itanium	B-General_Concept
processor	O
,	O
initially	O
aiming	O
for	O
the	O
high-performance	B-Architecture
computing	I-Architecture
market	O
,	O
hoping	O
that	O
it	O
would	O
eventually	O
replace	O
the	O
32-bit	B-Device
x86	I-Device
.	O
</s>
<s>
While	O
IA-64	B-General_Concept
was	O
incompatible	O
with	O
x86	B-Operating_System
,	O
the	O
Itanium	B-General_Concept
processor	O
did	O
provide	O
emulation	B-Application
abilities	O
for	O
translating	O
x86	B-Device
instructions	I-Device
into	O
IA-64	B-General_Concept
,	O
but	O
this	O
affected	O
the	O
performance	O
of	O
x86	B-Operating_System
programs	O
so	O
badly	O
that	O
it	O
was	O
rarely	O
,	O
if	O
ever	O
,	O
actually	O
useful	O
to	O
the	O
users	O
:	O
programmers	O
should	O
rewrite	O
x86	B-Operating_System
programs	O
for	O
the	O
IA-64	B-General_Concept
architecture	O
or	O
their	O
performance	O
on	O
Itanium	B-General_Concept
would	O
be	O
orders	O
of	O
magnitude	O
worse	O
than	O
on	O
a	O
true	O
x86	B-Operating_System
processor	O
.	O
</s>
<s>
The	O
market	O
rejected	O
the	O
Itanium	B-General_Concept
processor	O
since	O
it	O
broke	O
backward	B-General_Concept
compatibility	I-General_Concept
and	O
preferred	O
to	O
continue	O
using	O
x86	B-Operating_System
chips	O
,	O
and	O
very	O
few	O
programs	O
were	O
rewritten	O
for	O
IA-64	B-General_Concept
.	O
</s>
<s>
AMD	O
decided	O
to	O
take	O
another	O
path	O
toward	O
64-bit	B-Device
memory	O
addressing	O
,	O
making	O
sure	O
backward	B-General_Concept
compatibility	I-General_Concept
would	O
not	O
suffer	O
.	O
</s>
<s>
In	O
April	O
2003	O
,	O
AMD	O
released	O
the	O
first	O
x86	B-Operating_System
processor	O
with	O
64-bit	B-Device
general-purpose	O
registers	O
,	O
the	O
Opteron	B-General_Concept
,	O
capable	O
of	O
addressing	O
much	O
more	O
than	O
4GB	O
of	O
virtual	B-Architecture
memory	I-Architecture
using	O
the	O
new	O
x86-64	B-Device
extension	O
(	O
also	O
known	O
as	O
AMD64	B-Device
or	O
x64	B-Device
)	O
.	O
</s>
<s>
The	O
64-bit	B-Device
extensions	O
to	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
were	O
enabled	O
only	O
in	O
the	O
newly	O
introduced	O
long	B-Application
mode	I-Application
,	O
therefore	O
32-bit	O
and	O
16-bit	B-Device
applications	O
and	O
operating	B-General_Concept
systems	I-General_Concept
could	O
simply	O
continue	O
using	O
an	O
AMD64	B-Device
processor	O
in	O
protected	O
or	O
other	O
modes	O
,	O
without	O
even	O
the	O
slightest	O
sacrifice	O
of	O
performance	O
and	O
with	O
full	O
compatibility	O
back	O
to	O
the	O
original	O
instructions	O
of	O
the	O
16-bit	B-Device
Intel	B-General_Concept
8086	I-General_Concept
.	O
</s>
<s>
The	O
market	O
responded	O
positively	O
,	O
adopting	O
the	O
64-bit	B-Device
AMD	B-Device
processors	I-Device
for	O
both	O
high-performance	O
applications	O
and	O
business	O
or	O
home	O
computers	O
.	O
</s>
<s>
Seeing	O
the	O
market	O
rejecting	O
the	O
incompatible	O
Itanium	B-General_Concept
processor	O
and	O
Microsoft	O
supporting	O
AMD64	B-Device
,	O
Intel	O
had	O
to	O
respond	O
and	O
introduced	O
its	O
own	O
x86-64	B-Device
processor	O
,	O
the	O
Prescott	O
Pentium4	B-General_Concept
,	O
in	O
July	O
2004	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
Itanium	B-General_Concept
processor	O
with	O
its	O
IA-64	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
is	O
rarely	O
used	O
and	O
x86	B-Operating_System
,	O
through	O
its	O
x86-64	B-Device
incarnation	O
,	O
is	O
still	O
the	O
dominant	O
CPU	O
architecture	O
in	O
non-embedded	O
computers	O
.	O
</s>
<s>
x86-64	B-Device
also	O
introduced	O
the	O
NX	B-General_Concept
bit	I-General_Concept
,	O
which	O
offers	O
some	O
protection	O
against	O
security	O
bugs	O
caused	O
by	O
buffer	B-General_Concept
overruns	I-General_Concept
.	O
</s>
<s>
As	O
a	O
result	O
of	O
AMD	O
's	O
64-bit	B-Device
contribution	O
to	O
the	O
x86	B-Operating_System
lineage	O
and	O
its	O
subsequent	O
acceptance	O
by	O
Intel	O
,	O
the	O
64-bit	B-Device
RISC	B-Architecture
architectures	I-Architecture
ceased	O
to	O
be	O
a	O
threat	O
to	O
the	O
x86	B-Operating_System
ecosystem	O
and	O
almost	O
disappeared	O
from	O
the	O
workstation	B-Device
market	O
.	O
</s>
<s>
x86-64	B-Device
began	O
to	O
be	O
utilized	O
in	O
powerful	O
supercomputers	B-Architecture
(	O
in	O
its	O
AMD	B-General_Concept
Opteron	I-General_Concept
and	O
Intel	B-Device
Xeon	I-Device
incarnations	O
)	O
,	O
a	O
market	O
which	O
was	O
previously	O
the	O
natural	O
habitat	O
for	O
64-bit	B-Device
RISC	B-Architecture
designs	O
(	O
such	O
as	O
the	O
IBM	B-Device
Power	I-Device
microprocessors	I-Device
or	O
SPARC	B-Architecture
processors	B-General_Concept
)	O
.	O
</s>
<s>
The	O
great	O
leap	O
toward	O
64-bit	B-Device
computing	I-Device
and	O
the	O
maintenance	O
of	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
32-bit	O
and	O
16-bit	B-Device
software	O
enabled	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
to	O
become	O
an	O
extremely	O
flexible	O
platform	O
today	O
,	O
with	O
x86	B-Operating_System
chips	O
being	O
utilized	O
from	O
small	O
low-power	O
systems	O
(	O
for	O
example	O
,	O
Intel	B-Device
Quark	I-Device
and	O
Intel	B-Device
Atom	I-Device
)	O
to	O
fast	O
gaming	O
desktop	B-Device
computers	I-Device
(	O
for	O
example	O
,	O
Intel	B-Device
Core	I-Device
i7	I-Device
and	O
AMD	O
FX/Ryzen	O
)	O
,	O
and	O
even	O
dominate	O
large	O
supercomputing	B-Architecture
clusters	O
,	O
effectively	O
leaving	O
only	O
the	O
ARM	B-Architecture
32-bit	O
and	O
64-bit	B-Device
RISC	B-Architecture
architecture	O
as	O
a	O
competitor	O
in	O
the	O
smartphone	B-Application
and	O
tablet	B-Device
market	O
.	O
</s>
<s>
Prior	O
to	O
2005	O
,	O
x86	B-Operating_System
architecture	I-Operating_System
processors	B-General_Concept
were	O
unable	O
to	O
meet	O
the	O
Popek	B-Architecture
and	I-Architecture
Goldberg	I-Architecture
requirements	I-Architecture
-	O
a	O
specification	O
for	O
virtualization	O
created	O
in	O
1974	O
by	O
Gerald	O
J	O
.	O
Popek	O
and	O
Robert	O
P	O
.	O
Goldberg	O
.	O
</s>
<s>
However	O
,	O
both	O
proprietary	O
and	O
open-source	O
x86	B-General_Concept
virtualization	I-General_Concept
hypervisor	O
products	O
were	O
developed	O
using	O
software-based	O
virtualization	O
.	O
</s>
<s>
Proprietary	O
systems	O
include	O
Hyper-V	O
,	O
Parallels	B-Operating_System
Workstation	I-Operating_System
,	O
VMware	B-Operating_System
ESX	I-Operating_System
,	O
VMware	B-Operating_System
Workstation	I-Operating_System
,	O
VMware	B-Operating_System
Workstation	I-Operating_System
Player	I-Operating_System
and	O
Windows	B-Application
Virtual	I-Application
PC	I-Application
,	O
while	O
free	B-License
and	I-License
open-source	I-License
systems	O
include	O
QEMU	B-Application
,	O
Kernel-based	B-Application
Virtual	I-Application
Machine	I-Application
,	O
VirtualBox	B-Operating_System
,	O
and	O
Xen	B-Operating_System
.	O
</s>
<s>
The	O
introduction	O
of	O
the	O
AMD-V	O
and	O
Intel	O
VT-x	O
instruction	B-General_Concept
sets	I-General_Concept
in	O
2005	O
allowed	O
x86	B-Operating_System
processors	B-General_Concept
to	O
meet	O
the	O
Popek	B-Architecture
and	I-Architecture
Goldberg	I-Architecture
virtualization	I-Architecture
requirements	I-Architecture
.	O
</s>
