<s>
Write	B-Architecture
combining	I-Architecture
(	O
WC	O
)	O
is	O
a	O
computer	B-General_Concept
bus	I-General_Concept
technique	O
for	O
allowing	O
data	O
to	O
be	O
combined	O
and	O
temporarily	O
stored	O
in	O
a	O
buffer	B-General_Concept
the	O
write	B-Architecture
combine	I-Architecture
buffer	I-Architecture
(	O
WCB	O
)	O
to	O
be	O
released	O
together	O
later	O
in	O
burst	B-Architecture
mode	I-Architecture
instead	O
of	O
writing	O
(	O
immediately	O
)	O
as	O
single	O
bits	O
or	O
small	O
chunks	O
.	O
</s>
<s>
Write	B-Architecture
combining	I-Architecture
cannot	O
be	O
used	O
for	O
general	O
memory	O
access	O
(	O
data	O
or	O
code	O
regions	O
)	O
due	O
to	O
the	O
weak	O
ordering	O
.	O
</s>
<s>
Write-combining	B-Architecture
does	O
not	O
guarantee	O
that	O
the	O
combination	O
of	O
writes	O
and	O
reads	O
is	O
done	O
in	O
the	O
expected	O
order	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
write/read/write	O
combination	O
to	O
a	O
specific	O
address	O
would	O
lead	O
to	O
the	O
write	B-Architecture
combining	I-Architecture
order	O
of	O
read/write/write	O
which	O
can	O
lead	O
to	O
obtaining	O
wrong	O
values	O
with	O
the	O
first	O
read	O
(	O
which	O
potentially	O
relies	O
on	O
the	O
write	O
before	O
)	O
.	O
</s>
<s>
In	O
order	O
to	O
avoid	O
the	O
problem	O
of	O
read/write	O
order	O
described	O
above	O
,	O
the	O
write	B-General_Concept
buffer	I-General_Concept
can	O
be	O
treated	O
as	O
a	O
fully	O
associative	O
cache	B-General_Concept
and	O
added	O
into	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
of	O
the	O
device	O
in	O
which	O
it	O
is	O
implemented	O
.	O
</s>
<s>
Adding	O
complexity	O
slows	O
down	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
so	O
this	O
technique	O
is	O
often	O
only	O
used	O
for	O
memory	O
which	O
does	O
not	O
need	O
strong	O
ordering	O
(	O
always	O
correct	O
)	O
like	O
the	O
frame	B-Algorithm
buffers	I-Algorithm
of	O
video	B-Device
cards	I-Device
.	O
</s>
