<s>
The	O
Wright	B-Algorithm
etch	I-Algorithm
(	O
also	O
Wright-Jenkins	B-Algorithm
etch	I-Algorithm
)	O
is	O
a	O
preferential	O
etch	O
for	O
revealing	O
defects	O
in	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
,	O
p	O
-	O
and	O
n-type	O
silicon	B-Architecture
wafers	I-Architecture
used	O
for	O
making	O
transistors	B-Application
,	O
microprocessors	O
,	O
memories	O
,	O
and	O
other	O
components	O
.	O
</s>
<s>
These	O
defects	O
are	O
known	O
causes	O
of	O
shorts	O
and	O
current	O
leakage	O
in	O
finished	O
semiconductor	O
devices	O
(	O
such	O
as	O
transistors	B-Application
)	O
should	O
they	O
fall	O
across	O
isolated	O
junctions	O
.	O
</s>
<s>
The	O
composition	O
of	O
the	O
Wright	B-Algorithm
etch	I-Algorithm
is	O
as	O
follows	O
:	O
</s>
<s>
The	O
Wright	B-Algorithm
etch	I-Algorithm
consistently	O
produces	O
well-defined	O
etch	O
figures	O
of	O
common	O
defects	O
on	O
silicon	O
surfaces	O
.	O
</s>
<s>
All	O
experimental	O
preferential	O
etching	O
to	O
show	O
defects	O
was	O
done	O
on	O
cleaned	O
and	O
oxidized	O
wafers	B-Architecture
.	O
</s>
<s>
Figure	O
1	O
(	O
a	O
)	O
shows	O
oxidation-induced	O
stacking	O
faults	O
in	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
wafers	B-Architecture
respectively	O
after	O
20minutes	O
Wright	B-Algorithm
etch	I-Algorithm
.	O
</s>
<s>
Figure	O
1	O
(	O
a	O
)	O
shows	O
oxidation-induced	O
stacking	O
faults	O
on	O
a	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
,	O
7-10Ω-cm	O
,	O
boron-doped	O
wafer	B-Architecture
after	O
30minutes	O
Wright	B-Algorithm
etch	I-Algorithm
(	O
the	O
A	O
arrow	O
in	O
this	O
figure	O
points	O
to	O
the	O
shape	O
of	O
faults	O
that	O
intersect	O
the	O
surface	O
,	O
while	O
B	O
points	O
to	O
bulk	O
faults	O
)	O
.	O
</s>
<s>
Figure	O
1	O
(	O
b	O
)	O
and	O
(	O
c	O
)	O
show	O
dislocation	O
pits	O
on	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
wafers	B-Architecture
respectively	O
after	O
20minutes	O
Wright	B-Algorithm
etch	I-Algorithm
.	O
</s>
<s>
This	O
etch	O
process	O
is	O
a	O
quick	O
and	O
reliable	O
method	O
of	O
determining	O
the	O
integrity	O
of	O
pre-processed	O
polished	O
silicon	B-Architecture
wafers	I-Architecture
or	O
to	O
reveal	O
defects	O
that	O
may	O
be	O
induced	O
at	O
any	O
point	O
during	O
wafer	B-Architecture
processing	O
.	O
</s>
<s>
It	O
has	O
been	O
demonstrated	O
that	O
Wright	B-Algorithm
etch	I-Algorithm
is	O
superior	O
in	O
revealing	O
stacking	O
faults	O
and	O
dislocation	O
etch	O
figures	O
when	O
compared	O
with	O
those	O
revealed	O
by	O
Sirtl	O
and	O
Secco	O
etchings	O
.	O
</s>
<s>
This	O
etch	O
is	O
widely	O
used	O
in	O
failure	O
analysis	O
of	O
electrical	O
devices	O
at	O
various	O
wafer	B-Architecture
processing	O
stages	O
.	O
</s>
<s>
In	O
comparison	O
,	O
the	O
Wright	B-Algorithm
etch	I-Algorithm
was	O
often	O
the	O
preferred	O
etchant	O
to	O
reveal	O
defects	O
in	O
silicon	O
crystals	O
.	O
</s>
<s>
Figure	O
2	O
shows	O
a	O
comparison	O
of	O
oxidation-induced	O
stacking	O
fault	O
delineation	O
on	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
wafers	B-Architecture
after	O
Wright	B-Algorithm
etch	I-Algorithm
,	O
Secco	O
and	O
Sirtl	O
etch	O
respectively	O
.	O
</s>
<s>
Figure	O
3	O
shows	O
a	O
comparison	O
of	O
dislocation	O
pits	O
delineation	O
on	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
wafers	B-Architecture
after	O
Wright	B-Algorithm
etch	I-Algorithm
,	O
Secco	O
and	O
Sirtl	O
etch	O
.	O
</s>
<s>
The	O
final	O
figure	O
4	O
shows	O
a	O
comparison	O
of	O
dislocation	O
pits	O
revealed	O
on	O
a	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
wafer	B-Architecture
after	O
etching	O
with	O
Wright	B-Algorithm
etch	I-Algorithm
,	O
Secco	O
and	O
Sirtl	O
etch	O
respectively	O
.	O
</s>
<s>
Figure	O
3	O
shows	O
a	O
comparison	O
of	O
dislocation	O
delineation	O
on	O
a	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
,	O
10-20Ω-cm	O
,	O
boron	O
doped	O
wafer	B-Architecture
after	O
oxidation	O
and	O
preferential	O
etching	O
.	O
</s>
<s>
(	O
a	O
)	O
After	O
20minutes	O
Wright	B-Algorithm
etch	I-Algorithm
,	O
(	O
b	O
)	O
10minutes	O
Secco	O
etch	O
and	O
(	O
c	O
)	O
6minutes	O
Sirtl	O
etch	O
.	O
</s>
<s>
Figure	O
4	O
shows	O
a	O
comparison	O
of	O
dislocation	O
delineation	O
on	O
a	O
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1-oriented	O
,	O
10-20Ω-cm	O
,	O
boron-doped	O
wafer	B-Architecture
after	O
oxidation	O
and	O
preferential	O
etching	O
.	O
</s>
<s>
(	O
a	O
)	O
After	O
10minutes	O
Wright	B-Algorithm
etch	I-Algorithm
,	O
(	O
b	O
)	O
10minutes	O
Secco	O
etch	O
and	O
(	O
c	O
)	O
3minutes	O
Sirtl	O
etch	O
.	O
</s>
