<s>
The	O
Wishbone	B-Architecture
Bus	I-Architecture
is	O
an	O
open	B-Application
source	I-Application
hardware	O
computer	B-General_Concept
bus	I-General_Concept
intended	O
to	O
let	O
the	O
parts	O
of	O
an	O
integrated	O
circuit	O
communicate	O
with	O
each	O
other	O
.	O
</s>
<s>
The	O
aim	O
is	O
to	O
allow	O
the	O
connection	O
of	O
differing	O
cores	B-Architecture
to	O
each	O
other	O
inside	O
of	O
a	O
chip	O
.	O
</s>
<s>
The	O
Wishbone	B-Architecture
Bus	I-Architecture
is	O
used	O
by	O
many	O
designs	O
in	O
the	O
OpenCores	O
project	O
.	O
</s>
<s>
Wishbone	B-Architecture
is	O
intended	O
as	O
a	O
"	O
logic	O
bus	O
"	O
.	O
</s>
<s>
Wishbone	B-Architecture
is	O
made	O
to	O
let	O
designers	O
combine	O
several	O
designs	O
written	O
in	O
Verilog	B-Language
,	O
VHDL	B-Language
or	O
some	O
other	O
logic-description	O
language	O
for	O
electronic	O
design	O
automation	O
(	O
EDA	O
)	O
.	O
</s>
<s>
Wishbone	B-Architecture
provides	O
a	O
standard	O
way	O
for	O
designers	O
to	O
combine	O
these	O
hardware	O
logic	O
designs	O
(	O
called	O
"	O
cores	B-Architecture
"	O
)	O
.	O
</s>
<s>
Wishbone	B-Architecture
is	O
defined	O
to	O
have	O
8	O
,	O
16	O
,	O
32	O
,	O
and	O
64-bit	O
buses	O
.	O
</s>
<s>
Wishbone	B-Architecture
permits	O
addition	O
of	O
a	O
"	O
tag	O
bus	O
"	O
to	O
describe	O
the	O
data	O
.	O
</s>
<s>
Wishbone	B-Architecture
is	O
open	B-Application
source	I-Application
.	O
</s>
<s>
To	O
prevent	O
preemption	O
of	O
its	O
technologies	O
by	O
aggressive	O
patenting	O
,	O
the	O
Wishbone	B-Architecture
specification	O
includes	O
examples	O
of	O
prior	O
art	O
,	O
to	O
prove	O
its	O
concepts	O
are	O
in	O
the	O
public	O
domain	O
.	O
</s>
<s>
A	O
device	O
does	O
not	O
conform	O
to	O
the	O
Wishbone	B-Architecture
specification	O
unless	O
it	O
includes	O
a	O
data	O
sheet	O
that	O
describes	O
what	O
it	O
does	O
,	O
bus	O
width	O
,	O
utilization	O
,	O
etc	O
.	O
</s>
<s>
The	O
Simple	B-Architecture
Bus	I-Architecture
Architecture	I-Architecture
is	O
a	O
simplified	O
version	O
of	O
the	O
Wishbone	B-Architecture
specification	O
.	O
</s>
<s>
Wishbone	B-Architecture
adapts	O
well	O
to	O
common	O
topologies	O
such	O
as	O
point-to-point	O
,	O
many-to-many	O
(	O
i.e.	O
</s>
<s>
In	O
the	O
more	O
exotic	O
topologies	O
,	O
Wishbone	B-Architecture
requires	O
a	O
bus	O
controller	O
or	O
arbiter	O
,	O
but	O
devices	O
still	O
maintain	O
the	O
same	O
interface	O
.	O
</s>
<s>
Wishbone	B-Architecture
control	O
signals	O
compared	O
to	O
other	O
system	O
on	O
a	O
chip	O
(	O
SoC	O
)	O
bus	O
standards	O
:	O
</s>
<s>
+Wishbone	O
=>	O
Avalon	O
Wishbone	B-Architecture
Avalon	O
Bus	O
Description	O
cyc	O
=	O
!	O
write_n	O
or	O
!	O
read_n	O
indicates	O
that	O
a	O
valid	O
bus	O
cycle	O
is	O
in	O
progress	O
stb	O
=	O
chipselect	O
indicates	O
a	O
valid	O
data	O
transfer	O
cycle	O
we	O
=	O
!	O
write_n	O
and	O
read_n	O
indicates	O
whether	O
the	O
current	O
local	O
bus	O
cycle	O
is	O
a	O
READ	O
or	O
WRITE	O
cycle	O
.	O
</s>
<s>
+	O
Avalon	O
=>	O
Wishbone	B-Architecture
Avalon	O
Bus	O
Wishbone	B-Architecture
Description	O
chipselect	O
=	O
stb	O
indicates	O
that	O
slave	O
device	O
is	O
selected	O
.	O
</s>
