<s>
The	O
WinChip	B-Device
series	O
was	O
a	O
low-power	B-General_Concept
Socket	O
7-based	O
x86	B-Operating_System
processor	B-General_Concept
designed	O
by	O
Centaur	O
Technology	O
and	O
marketed	O
by	O
its	O
parent	O
company	O
IDT	O
.	O
</s>
<s>
The	O
design	O
of	O
the	O
WinChip	B-Device
was	O
quite	O
different	O
from	O
other	O
processors	O
of	O
the	O
time	O
.	O
</s>
<s>
Instead	O
of	O
a	O
large	O
gate	B-Algorithm
count	I-Algorithm
and	O
die	O
area	O
,	O
IDT	O
,	O
using	O
its	O
experience	O
from	O
the	O
RISC	B-Architecture
processor	I-Architecture
market	O
,	O
created	O
a	O
small	O
and	O
electrically	O
efficient	O
processor	B-General_Concept
similar	O
to	O
the	O
80486	B-General_Concept
,	O
because	O
of	O
its	O
single	O
pipeline	B-General_Concept
and	O
in-order	O
execution	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
It	O
was	O
of	O
much	O
simpler	O
design	O
than	O
its	O
Socket	B-General_Concept
7	I-General_Concept
competitors	O
,	O
such	O
as	O
AMD	O
K5/K6	O
,	O
which	O
were	O
superscalar	B-General_Concept
and	O
based	O
on	O
dynamic	O
translation	O
to	O
buffered	O
micro-operations	B-General_Concept
with	O
advanced	O
instruction	O
reordering	O
(	O
out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
execution	I-General_Concept
)	O
.	O
</s>
<s>
WinChip	B-Device
was	O
,	O
in	O
general	O
,	O
designed	O
to	O
perform	O
well	O
with	O
popular	O
applications	O
that	O
did	O
few	O
(	O
if	O
any	O
)	O
floating	B-Algorithm
point	I-Algorithm
calculations	O
.	O
</s>
<s>
This	O
included	O
operating	B-General_Concept
systems	I-General_Concept
of	O
the	O
time	O
and	O
the	O
majority	O
of	O
software	O
used	O
in	O
businesses	O
.	O
</s>
<s>
This	O
allowed	O
IDT/Centaur	O
to	O
take	O
advantage	O
of	O
an	O
established	O
system	O
platform	O
(	O
Intel	O
's	O
Socket	B-General_Concept
7	I-General_Concept
)	O
.	O
</s>
<s>
WinChip	B-Device
2	I-Device
,	O
an	O
update	O
of	O
C6	O
,	O
retained	O
the	O
simple	O
in-order	O
execution	O
pipeline	B-General_Concept
of	O
its	O
predecessor	O
,	O
but	O
added	O
dual	O
MMX/3DNow	O
!	O
</s>
<s>
processing	O
units	O
that	O
could	O
operate	O
in	O
superscalar	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
This	O
made	O
it	O
the	O
only	O
non-AMD	O
CPU	O
on	O
Socket	B-General_Concept
7	I-General_Concept
to	O
support	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
WinChip	B-Device
2A	I-Device
added	O
fractional	O
multipliers	O
and	O
adopted	O
a	O
100MHz	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
to	O
improve	O
memory	O
access	O
and	O
L2	O
cache	O
performance	O
.	O
</s>
<s>
Another	O
revision	O
,	O
the	O
WinChip	B-Device
2B	O
,	O
was	O
also	O
planned	O
.	O
</s>
<s>
A	O
third	O
model	O
,	O
the	O
WinChip	B-Device
3	O
,	O
was	O
planned	O
as	O
well	O
.	O
</s>
<s>
This	O
was	O
meant	O
to	O
receive	O
a	O
doubled	O
L1	B-General_Concept
cache	I-General_Concept
,	O
but	O
the	O
W3	O
CPU	O
never	O
made	O
it	O
to	O
market	O
.	O
</s>
<s>
Although	O
the	O
small	O
die	O
size	O
and	O
low	O
power-usage	O
made	O
the	O
processor	B-General_Concept
notably	O
inexpensive	O
to	O
manufacture	O
,	O
it	O
never	O
gained	O
much	O
market	O
share	O
.	O
</s>
<s>
WinChip	B-Device
C6	O
was	O
a	O
competitor	O
to	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
and	O
Pentium	B-General_Concept
MMX	B-Architecture
,	O
Cyrix	B-General_Concept
6x86	I-General_Concept
,	O
and	O
AMD	O
K5/K6	O
.	O
</s>
<s>
It	O
performed	O
adequately	O
,	O
but	O
only	O
in	O
applications	O
that	O
used	O
little	O
floating	B-Algorithm
point	I-Algorithm
math	I-Algorithm
.	O
</s>
<s>
Its	O
floating	B-Algorithm
point	I-Algorithm
performance	O
was	O
simply	O
well	O
below	O
that	O
of	O
the	O
Pentium	B-General_Concept
and	O
K6	B-Architecture
,	O
being	O
even	O
slower	O
than	O
the	O
Cyrix	B-General_Concept
6x86	I-General_Concept
.	O
</s>
<s>
The	O
industry	O
's	O
move	O
away	O
from	O
Socket	B-General_Concept
7	I-General_Concept
and	O
the	O
release	O
of	O
the	O
Intel	B-Device
Celeron	I-Device
processor	I-Device
signalled	O
the	O
end	O
of	O
the	O
WinChip	B-Device
.	O
</s>
<s>
Although	O
VIA	O
branded	O
the	O
processors	O
as	O
"	O
Cyrix	O
"	O
,	O
the	O
company	O
initially	O
used	O
technology	O
similar	O
to	O
the	O
WinChip	B-Device
in	O
its	O
Cyrix	B-Device
III	I-Device
line	O
.	O
</s>
<s>
The	O
64	O
Kib	O
L1	B-General_Concept
Cache	I-General_Concept
of	O
the	O
WinChip	B-Device
C6	O
used	O
a	O
32	O
KB	O
2-way	O
set	O
associative	O
code	O
cache	O
and	O
a	O
32	O
KB	O
2-way	O
set	O
associative	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Processormodel	O
Frequency	O
FSB	B-Architecture
Mult	O
.	O
</s>
<s>
L1	B-General_Concept
cache	I-General_Concept
TDP	B-General_Concept
CPU	B-Device
core	I-Device
voltage	I-Device
Socket	B-General_Concept
Release	O
date	O
Part	O
number(s )	O
Introduction	O
price	O
WinChip	B-Device
180	O
180	O
MHz	O
60	O
MT/s	O
3	O
64	O
KiB	O
9.4	O
W	O
3.45	O
—	O
3.6	O
V	O
13	O
October	O
1997	O
DS180GAEM	O
$90	O
WinChip	B-Device
200	O
200	O
MHz	O
66	O
Mt/s	O
3	O
64	O
KiB	O
10.4	O
W	O
3.45	O
—	O
3.6	O
V	O
13	O
October	O
1997	O
DS200GAEM	O
$135	O
WinChip	B-Device
225	O
225	O
MHz	O
75	O
MT/s	O
3	O
64	O
KiB	O
12.3	O
W	O
3.45	O
—	O
3.6	O
V	O
13	O
October	O
1997	O
PSME225GA	O
WinChip	B-Device
240	O
240	O
MHz	O
60	O
MT/s	O
4	O
64	O
KiB	O
13.1	O
W	O
3.45	O
—	O
3.6	O
V	O
November	O
1997	O
?	O
</s>
<s>
All	O
models	O
supported	O
MMX	B-Architecture
and	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
The	O
64	O
Kib	O
L1	B-General_Concept
Cache	I-General_Concept
of	O
the	O
WinChip	B-Device
2	I-Device
used	O
a	O
32	O
KB	O
2-way	O
set	O
associative	O
code	O
cache	O
and	O
a	O
32	O
KB	O
4-way	O
set	O
associative	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Processormodel	O
Frequency	O
FSB	B-Architecture
Mult	O
.	O
</s>
<s>
L1	B-General_Concept
cache	I-General_Concept
TDP	B-General_Concept
CPU	B-Device
core	I-Device
voltage	I-Device
Socket	B-General_Concept
Release	O
date	O
Part	O
number(s )	O
Introduction	O
price	O
WinChip	O
2-200	O
200	O
MHz	O
66	O
MT/s	O
3	O
64	O
KiB	O
8.8	O
W	O
3.45	O
—	O
3.6	O
V	O
3DEE200GSA3DFF200GSA	O
WinChip	O
2-225	O
225	O
MHz	O
75	O
MT/s	O
3	O
64	O
KiB	O
10.0	O
W	O
3.45	O
—	O
3.6	O
V	O
3DEE225GSA	O
WinChip	O
2-240	O
240	O
MHz	O
60	O
MT/s	O
4	O
64	O
KiB	O
10.5	O
W	O
3.45	O
—	O
3.6	O
V	O
3DEE240GSA	O
WinChip	O
2-250	O
250	O
MHz	O
83	O
MT/s	O
3	O
64	O
KiB	O
10.9	O
W	O
3.45	O
—	O
3.6	O
V	O
?	O
</s>
<s>
All	O
models	O
supported	O
MMX	B-Architecture
and	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
The	O
64	O
Kib	O
L1	B-General_Concept
Cache	I-General_Concept
of	O
the	O
WinChip	B-Device
2A	I-Device
used	O
a	O
32	O
KB	O
2-way	O
set	O
associative	O
code	O
cache	O
and	O
a	O
32	O
KB	O
4-way	O
set	O
associative	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Processormodel	O
Frequency	O
FSB	B-Architecture
Mult	O
.	O
</s>
<s>
L1	B-General_Concept
cache	I-General_Concept
TDP	B-General_Concept
CPU	B-Device
core	I-Device
voltage	I-Device
Socket	B-General_Concept
Release	O
date	O
Part	O
number(s )	O
Introduction	O
price	O
WinChip	O
2A-200	O
200	O
MHz	O
66	O
MT/s	O
3	O
64	O
KiB	O
12.0	O
W	O
3.45	O
—	O
3.6	O
V	O
March	O
1999	O
?	O
</s>
<s>
All	O
models	O
supported	O
MMX	B-Architecture
and	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
The	O
64	O
Kib	O
L1	B-General_Concept
Cache	I-General_Concept
of	O
the	O
WinChip	B-Device
2B	O
used	O
a	O
32	O
KB	O
2-way	O
set	O
associative	O
code	O
cache	O
and	O
a	O
32	O
KB	O
4-way	O
set	O
associative	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Dual-voltage	O
CPU	O
:	O
while	O
the	O
processor	B-General_Concept
core	O
operates	O
at	O
2.8	O
Volt	O
,	O
the	O
external	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
voltages	O
remain	O
3.3	O
volts	O
for	O
backwards	O
compatibility	O
.	O
</s>
<s>
Processormodel	O
Frequency	O
FSB	B-Architecture
Mult	O
.	O
</s>
<s>
All	O
models	O
supported	O
MMX	B-Architecture
and	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
The	O
128	O
Kib	O
L1	B-General_Concept
Cache	I-General_Concept
of	O
the	O
WinChip	B-Device
3	O
used	O
a	O
64	O
KB	O
2-way	O
set	O
associative	O
code	O
cache	O
and	O
a	O
64	O
KB	O
4-way	O
set	O
associative	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Dual-voltage	O
CPU	O
:	O
while	O
the	O
processor	B-General_Concept
core	O
operates	O
at	O
2.8	O
volts	O
,	O
the	O
external	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
voltages	O
remain	O
3.3	O
volts	O
for	O
backwards	O
compatibility	O
.	O
</s>
<s>
Processormodel	O
Frequency	O
FSB	B-Architecture
Mult	O
.	O
</s>
<s>
L1	B-General_Concept
cache	I-General_Concept
TDP	B-General_Concept
CPU	B-Device
core	I-Device
voltage	I-Device
Socket	B-General_Concept
Release	O
date	O
Part	O
number(s )	O
Introduction	O
price	O
WinChip	B-Device
3-233	O
200	O
MHz	O
66	O
MT/s	O
3	O
128	O
KiB	O
?	O
</s>
