<s>
A	O
wide-issue	B-Operating_System
architecture	O
is	O
a	O
computer	O
processor	O
that	O
issues	O
more	O
than	O
one	O
instruction	O
per	O
clock	O
cycle	O
.	O
</s>
<s>
Statically-scheduled	O
superscalar	B-General_Concept
architectures	I-General_Concept
execute	O
instructions	O
in	O
the	O
order	O
presented	O
;	O
the	O
hardware	O
logic	O
determines	O
which	O
instructions	O
are	O
ready	O
and	O
safe	O
to	O
dispatch	O
on	O
each	O
clock	O
cycle	O
.	O
</s>
<s>
VLIW	B-General_Concept
architectures	O
rely	O
on	O
the	O
programming	O
software	O
(	O
compiler	O
)	O
to	O
determine	O
which	O
instructions	O
to	O
dispatch	O
on	O
a	O
given	O
clock	O
cycle	O
.	O
</s>
<s>
Dynamically-scheduled	O
superscalar	B-General_Concept
architectures	I-General_Concept
execute	O
instructions	O
in	O
an	O
order	O
that	O
gives	O
the	O
same	O
result	O
as	O
the	O
order	O
presented	O
;	O
the	O
hardware	O
logic	O
determines	O
which	O
instructions	O
are	O
ready	O
and	O
safe	O
to	O
dispatch	O
on	O
each	O
clock	O
cycle	O
.	O
</s>
