<s>
Westmere	B-Device
(	O
formerly	O
Nehalem-C	B-Device
)	O
is	O
the	O
code	O
name	O
given	O
to	O
the	O
32	B-Algorithm
nm	I-Algorithm
die	O
shrink	O
of	O
Nehalem	B-Device
.	O
</s>
<s>
While	O
sharing	O
the	O
same	O
CPU	B-General_Concept
sockets	I-General_Concept
,	O
Westmere	B-Device
included	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
while	O
Nehalem	B-Device
did	O
not	O
.	O
</s>
<s>
The	O
first	O
Westmere-based	O
processors	O
were	O
launched	O
on	O
January	O
7	O
,	O
2010	O
,	O
by	O
Intel	O
Corporation	O
.	O
</s>
<s>
The	O
Westmere	B-Device
architecture	O
has	O
been	O
available	O
under	O
the	O
Intel	O
brands	O
of	O
Core	B-Device
i3	I-Device
,	O
Core	B-Device
i5	I-Device
,	O
Core	B-Device
i7	I-Device
,	O
Pentium	B-Device
,	O
Celeron	B-Device
and	O
Xeon	B-Device
.	O
</s>
<s>
Westmere	B-Device
's	O
feature	O
improvements	O
from	O
Nehalem	B-Device
,	O
as	O
reported	O
:	O
</s>
<s>
Native	O
six-core	O
(	O
Gulftown	B-Device
)	O
and	O
ten-core	O
(	O
Westmere-EX	O
)	O
processors	O
.	O
</s>
<s>
A	O
new	O
set	O
of	O
instructions	O
that	O
gives	O
over	O
3x	O
the	O
encryption	O
and	O
decryption	O
rate	O
of	O
Advanced	B-Algorithm
Encryption	I-Algorithm
Standard	I-Algorithm
(	O
AES	B-Algorithm
)	O
processes	O
compared	O
to	O
before	O
.	O
</s>
<s>
Delivers	O
seven	O
new	O
instructions	O
(	O
AES	B-Algorithm
instruction	I-Algorithm
set	I-Algorithm
or	O
AES-NI	B-Algorithm
)	O
,	O
out	O
of	O
which	O
six	O
implement	O
the	O
AES	B-Algorithm
algorithm	O
,	O
and	O
PCLMULQDQ	B-Device
(	O
see	O
CLMUL	B-Device
instruction	I-Device
set	I-Device
)	O
implements	O
carry-less	O
multiplication	O
for	O
use	O
in	O
cryptography	O
and	O
data	B-General_Concept
compression	I-General_Concept
.	O
</s>
<s>
Integrated	O
graphics	O
,	O
added	O
into	O
the	O
processor	O
package	O
(	O
dual	B-Architecture
core	I-Architecture
Arrandale	O
and	O
Clarkdale	B-Device
only	O
)	O
.	O
</s>
<s>
New	O
virtualization	O
capability	O
:	O
"	O
VMX	O
Unrestricted	O
mode	O
support	O
,	O
"	O
which	O
allows	O
16-bit	O
guests	O
to	O
run	O
(	O
real	O
mode	O
and	O
big	B-Device
real	I-Device
mode	I-Device
)	O
.	O
</s>
<s>
TDP	B-General_Concept
includes	O
the	O
integrated	O
GPU	B-Application
,	O
if	O
present	O
.	O
</s>
<s>
Clarkdale	B-Device
processors	O
feature	O
16	O
PCIe	O
2.0	O
lanes	O
,	O
which	O
can	O
be	O
used	O
in	O
1x16	O
or	O
2x8	O
configuration	O
.	O
</s>
<s>
Clarkdale	B-Device
and	O
Arrandale	O
contain	O
the	O
32nm	B-Algorithm
dual	B-Architecture
core	I-Architecture
processor	I-Architecture
Hillel	O
and	O
the	O
45nm	B-Algorithm
integrated	O
graphics	O
device	O
Ironlake	O
,	O
and	O
support	O
switchable	O
graphics	O
.	O
</s>
<s>
Only	O
certain	O
higher-end	O
CPUs	O
support	O
AES-NI	B-Algorithm
and	O
1GB	O
Huge	O
Pages	O
.	O
</s>
<s>
The	O
successor	O
to	O
Nehalem	B-Device
and	O
Westmere	B-Device
is	O
Sandy	B-Device
Bridge	I-Device
.	O
</s>
