<s>
A	O
wait	B-Device
state	I-Device
is	O
a	O
delay	O
experienced	O
by	O
a	O
computer	O
processor	B-General_Concept
when	O
accessing	O
external	O
memory	B-General_Concept
or	O
another	O
device	O
that	O
is	O
slow	O
to	O
respond	O
.	O
</s>
<s>
Even	O
memory	B-General_Concept
,	O
the	O
fastest	O
of	O
these	O
,	O
cannot	O
supply	O
data	O
as	O
fast	O
as	O
the	O
CPU	O
could	O
process	O
it	O
.	O
</s>
<s>
In	O
an	O
example	O
from	O
2011	O
,	O
typical	O
PC	O
processors	O
like	O
the	O
Intel	B-Device
Core	I-Device
2	I-Device
and	O
the	O
AMD	O
Athlon	O
64	O
X2	O
run	O
with	O
a	O
clock	O
of	O
several	O
GHz	O
,	O
which	O
means	O
that	O
one	O
clock	O
cycle	O
is	O
less	O
than	O
1	O
nanosecond	O
(	O
typically	O
about	O
0.3	O
ns	O
to	O
0.5	O
ns	O
on	O
modern	O
desktop	O
CPUs	O
)	O
,	O
while	O
main	O
memory	B-General_Concept
has	O
a	O
latency	B-General_Concept
of	O
about	O
15	O
–	O
30	O
ns	O
.	O
</s>
<s>
Some	O
second-level	O
CPU	B-General_Concept
caches	I-General_Concept
run	O
slower	O
than	O
the	O
processor	B-General_Concept
core	O
.	O
</s>
<s>
When	O
the	O
processor	B-General_Concept
needs	O
to	O
access	O
external	O
memory	B-General_Concept
,	O
it	O
starts	O
placing	O
the	O
address	O
of	O
the	O
requested	O
information	O
on	O
the	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Each	O
of	O
the	O
cycles	O
spent	O
waiting	O
is	O
called	O
a	O
wait	B-Device
state	I-Device
.	O
</s>
<s>
Wait	B-Device
states	I-Device
are	O
a	O
pure	O
waste	O
of	O
a	O
processor	B-General_Concept
's	O
performance	O
.	O
</s>
<s>
Modern	O
designs	O
try	O
to	O
eliminate	O
or	O
hide	O
them	O
using	O
a	O
variety	O
of	O
techniques	O
:	O
CPU	B-General_Concept
caches	I-General_Concept
,	O
instruction	B-General_Concept
pipelines	I-General_Concept
,	O
instruction	B-General_Concept
prefetch	I-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
and	O
others	O
.	O
</s>
<s>
Wait	B-Device
states	I-Device
can	O
be	O
used	O
to	O
reduce	O
the	O
energy	O
consumption	O
of	O
a	O
processor	B-General_Concept
,	O
by	O
allowing	O
the	O
main	O
processor	B-General_Concept
clock	O
to	O
either	O
slow	O
down	O
or	O
temporarily	O
pause	O
during	O
the	O
wait	B-Device
state	I-Device
if	O
the	O
CPU	O
has	O
no	O
other	O
work	O
to	O
do	O
.	O
</s>
<s>
Rather	O
than	O
spinning	O
uselessly	O
in	O
a	O
tight	O
loop	O
waiting	O
for	O
data	O
,	O
sporadically	O
reducing	O
the	O
clock	O
speed	O
in	O
this	O
manner	O
helps	O
to	O
keep	O
the	O
processor	B-General_Concept
core	O
cool	O
and	O
to	O
extend	O
battery	O
life	O
in	O
portable	O
computing	O
devices	O
.	O
</s>
<s>
On	O
IBM	B-Device
mainframes	I-Device
,	O
the	O
term	O
wait	B-Device
state	I-Device
is	O
used	O
with	O
a	O
different	O
meaning	O
.	O
</s>
<s>
A	O
wait	B-Device
state	I-Device
refers	O
to	O
a	O
CPU	O
being	O
halted	O
,	O
possibly	O
due	O
to	O
some	O
kind	O
of	O
serious	O
error	O
condition	O
(	O
such	O
as	O
an	O
unrecoverable	O
error	O
during	O
operating	O
system	O
to	O
IPL	O
)	O
.	O
</s>
<s>
A	O
wait	B-Device
state	I-Device
is	O
indicated	O
by	O
bit	O
14	O
of	O
the	O
PSW	B-Device
being	O
set	O
to	O
1	O
,	O
with	O
other	O
bits	O
of	O
the	O
PSW	B-Device
providing	O
a	O
wait	B-Device
state	I-Device
code	O
giving	O
a	O
reason	O
for	O
the	O
wait	O
.	O
</s>
<s>
In	O
z/Architecture	B-Device
mode	O
,	O
the	O
wait	B-Device
state	I-Device
code	O
is	O
found	O
in	O
bits	O
116-127	O
.	O
</s>
