<s>
Wafer	B-Algorithm
testing	I-Algorithm
is	O
a	O
step	O
performed	O
during	O
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
after	O
BEOL	B-Algorithm
process	O
is	O
finished	O
.	O
</s>
<s>
The	O
wafer	B-Algorithm
testing	I-Algorithm
is	O
performed	O
by	O
a	O
piece	O
of	O
test	O
equipment	O
called	O
a	O
wafer	O
prober	O
.	O
</s>
<s>
The	O
process	O
of	O
wafer	B-Algorithm
testing	I-Algorithm
can	O
be	O
referred	O
to	O
in	O
several	O
ways	O
:	O
Wafer	O
Final	O
Test	O
(	O
WFT	O
)	O
,	O
Electronic	O
Die	O
Sort	O
(	O
EDS	O
)	O
and	O
Circuit	O
Probe	O
(	O
CP	O
)	O
are	O
probably	O
the	O
most	O
common	O
.	O
</s>
<s>
For	O
electrical	O
testing	O
a	O
set	O
of	O
microscopic	O
contacts	O
or	O
probes	O
called	O
a	O
probe	B-Algorithm
card	I-Algorithm
are	O
held	O
in	O
place	O
whilst	O
the	O
wafer	O
,	O
vacuum-mounted	O
on	O
a	O
wafer	O
chuck	O
,	O
is	O
moved	O
into	O
electrical	O
contact	O
.	O
</s>
<s>
For	O
today	O
's	O
multi-die	O
packages	O
such	O
as	O
stacked	O
chip-scale	B-Algorithm
package	I-Algorithm
(	O
SCSP	O
)	O
or	O
system	O
in	O
package	O
(	O
SiP	O
)	O
–	O
the	O
development	O
of	O
non-contact	O
(	O
RF	O
)	O
probes	O
for	O
identification	O
of	O
known	O
tested	O
die	O
(	O
KTD	O
)	O
and	O
known	O
good	O
die	O
(	O
KGD	O
)	O
are	O
critical	O
to	O
increasing	O
overall	O
system	O
yield	O
.	O
</s>
<s>
When	O
all	O
test	O
patterns	O
pass	O
for	O
a	O
specific	O
die	O
,	O
its	O
position	O
is	O
remembered	O
for	O
later	O
use	O
during	O
IC	B-Algorithm
packaging	I-Algorithm
.	O
</s>
<s>
This	O
wafermap	O
is	O
then	O
sent	O
to	O
the	O
die	B-Algorithm
attachment	I-Algorithm
process	O
which	O
then	O
only	O
picks	O
up	O
the	O
passing	O
circuits	O
by	O
selecting	O
the	O
bin	O
number	O
of	O
good	O
dies	O
.	O
</s>
<s>
The	O
process	O
where	O
no	O
ink	O
dot	O
is	O
used	O
to	O
mark	O
the	O
bad	O
dies	O
is	O
named	O
substrate	B-Algorithm
mapping	I-Algorithm
.	O
</s>
<s>
The	O
most	O
common	O
example	O
of	O
this	O
is	O
a	O
microprocessor	O
for	O
which	O
only	O
one	O
part	O
of	O
the	O
on-die	O
cache	B-General_Concept
memory	O
is	O
functional	O
.	O
</s>
<s>
After	O
IC	B-Algorithm
packaging	I-Algorithm
,	O
a	O
packaged	O
chip	O
will	O
be	O
tested	O
again	O
during	O
the	O
IC	O
testing	O
phase	O
,	O
usually	O
with	O
the	O
same	O
or	O
very	O
similar	O
test	O
patterns	O
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
it	O
may	O
be	O
thought	O
that	O
wafer	B-Algorithm
testing	I-Algorithm
is	O
an	O
unnecessary	O
,	O
redundant	O
step	O
.	O
</s>
<s>
In	O
reality	O
this	O
is	O
not	O
usually	O
the	O
case	O
,	O
since	O
the	O
removal	O
of	O
defective	O
dies	O
saves	O
the	O
considerable	O
cost	O
of	O
packaging	B-Algorithm
faulty	O
devices	O
.	O
</s>
<s>
However	O
,	O
when	O
the	O
production	O
yield	O
is	O
so	O
high	O
that	O
wafer	B-Algorithm
testing	I-Algorithm
is	O
more	O
expensive	O
than	O
the	O
packaging	B-Algorithm
cost	O
of	O
defect	O
devices	O
,	O
the	O
wafer	B-Algorithm
testing	I-Algorithm
step	O
can	O
be	O
skipped	O
altogether	O
and	O
dies	O
will	O
undergo	O
blind	O
assembly	O
.	O
</s>
