<s>
In	O
the	O
context	O
of	O
manufacturing	O
integrated	O
circuits	O
,	O
wafer	B-Algorithm
dicing	I-Algorithm
is	O
the	O
process	O
by	O
which	O
die	O
are	O
separated	O
from	O
a	O
wafer	B-Architecture
of	O
semiconductor	O
following	O
the	O
processing	O
of	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
Following	O
the	O
dicing	O
process	O
the	O
individual	O
silicon	O
chips	O
may	O
be	O
encapsulated	O
into	O
chip	B-Algorithm
carriers	I-Algorithm
which	O
are	O
then	O
suitable	O
for	O
use	O
in	O
building	O
electronic	O
devices	O
such	O
as	O
computers	O
,	O
etc	O
.	O
</s>
<s>
During	O
dicing	O
,	O
wafers	B-Architecture
are	O
typically	O
mounted	O
on	O
dicing	B-Algorithm
tape	I-Algorithm
which	O
has	O
a	O
sticky	O
backing	O
that	O
holds	O
the	O
wafer	B-Architecture
on	O
a	O
thin	O
sheet	O
metal	O
frame	O
.	O
</s>
<s>
Dicing	B-Algorithm
tape	I-Algorithm
has	O
different	O
properties	O
depending	O
on	O
the	O
dicing	O
application	O
.	O
</s>
<s>
UV	O
curable	O
tapes	O
are	O
used	O
for	O
smaller	O
sizes	O
and	O
non-UV	O
dicing	B-Algorithm
tape	I-Algorithm
for	O
larger	O
die	O
sizes	O
.	O
</s>
<s>
Once	O
a	O
wafer	B-Architecture
has	O
been	O
diced	O
,	O
the	O
pieces	O
left	O
on	O
the	O
dicing	B-Algorithm
tape	I-Algorithm
are	O
referred	O
to	O
as	O
die	O
,	O
dice	O
or	O
dies	O
.	O
</s>
<s>
Each	O
will	O
be	O
packaged	O
in	O
a	O
suitable	O
package	O
or	O
placed	O
directly	O
on	O
a	O
printed	O
circuit	O
board	O
substrate	B-Architecture
as	O
a	O
"	O
bare	O
die	O
"	O
.	O
</s>
<s>
Once	O
a	O
wafer	B-Architecture
has	O
been	O
diced	O
,	O
the	O
die	O
will	O
stay	O
on	O
the	O
dicing	B-Algorithm
tape	I-Algorithm
until	O
they	O
are	O
extracted	O
by	O
die-handling	O
equipment	O
,	O
such	O
as	O
a	O
die	O
bonder	O
or	O
die	O
sorter	O
,	O
further	O
in	O
the	O
electronics	O
assembly	O
process	O
.	O
</s>
<s>
Materials	O
diced	O
include	O
glass	O
,	O
alumina	O
,	O
silicon	O
,	O
gallium	O
arsenide	O
(	O
GaAs	O
)	O
,	O
silicon	B-Algorithm
on	I-Algorithm
sapphire	I-Algorithm
(	O
SoS	O
)	O
,	O
ceramics	O
,	O
and	O
delicate	O
compound	O
semiconductors	O
.	O
</s>
<s>
Dicing	O
of	O
silicon	B-Architecture
wafers	I-Architecture
may	O
also	O
be	O
performed	O
by	O
a	O
laser-based	O
technique	O
,	O
the	O
so-called	O
stealth	O
dicing	O
process	O
.	O
</s>
<s>
It	O
works	O
as	O
a	O
two-stage	O
process	O
in	O
which	O
defect	O
regions	O
are	O
firstly	O
introduced	O
into	O
the	O
wafer	B-Architecture
by	O
scanning	O
the	O
beam	O
along	O
intended	O
cutting	O
lines	O
and	O
secondly	O
an	O
underlying	O
carrier	O
membrane	O
is	O
expanded	O
to	O
induce	O
fracture	O
.	O
</s>
<s>
Defect	O
regions	O
of	O
about	O
10µm	O
width	O
are	O
inscribed	O
by	O
multiple	O
scans	O
of	O
the	O
laser	O
along	O
the	O
intended	O
dicing	O
lanes	O
,	O
where	O
the	O
beam	O
is	O
focused	O
at	O
different	O
depths	O
of	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
The	O
laser	O
is	O
typically	O
pulsed	O
by	O
a	O
frequency	O
of	O
about	O
100kHz	O
,	O
while	O
the	O
wafer	B-Architecture
is	O
moved	O
with	O
a	O
velocity	O
of	O
about	O
1m/s	O
.	O
</s>
<s>
A	O
defected	O
region	O
of	O
about	O
10µm	O
width	O
is	O
finally	O
inscribed	O
in	O
the	O
wafer	B-Architecture
,	O
along	O
which	O
preferential	O
fracture	O
occurs	O
under	O
mechanical	O
loading	O
.	O
</s>
<s>
The	O
fracture	O
is	O
performed	O
in	O
the	O
second	O
step	O
and	O
operates	O
by	O
radially	O
expanding	O
the	O
carrier	O
membrane	O
to	O
which	O
the	O
wafer	B-Architecture
is	O
attached	O
.	O
</s>
<s>
Dry	O
dicing	O
methods	O
inevitably	O
have	O
to	O
be	O
applied	O
for	O
the	O
preparation	O
of	O
certain	O
microelectromechanical	O
systems	O
(	O
MEMS	B-General_Concept
)	O
,	O
in	O
particular	O
,	O
when	O
these	O
are	O
intended	O
for	O
bioelectronic	O
applications	O
.	O
</s>
<s>
In	O
addition	O
,	O
stealth	O
dicing	O
hardly	O
generates	O
debris	O
and	O
allows	O
for	O
improved	O
exploitation	O
of	O
the	O
wafer	B-Architecture
surface	O
due	O
to	O
smaller	O
kerf	O
loss	O
compared	O
to	O
wafer	B-Architecture
saw	O
.	O
</s>
<s>
Wafer	B-Architecture
grinding	O
may	O
be	O
performed	O
after	O
this	O
step	O
,	O
to	O
reduce	O
die	O
thickness	O
.	O
</s>
<s>
The	O
separation	O
occurs	O
during	O
the	O
wafer	B-Architecture
thinning	O
step	O
.	O
</s>
<s>
The	O
wafers	B-Architecture
are	O
initially	O
diced	O
using	O
a	O
half-cut	O
dicer	O
to	O
a	O
depth	O
below	O
the	O
final	O
target	O
thickness	O
.	O
</s>
<s>
Next	O
,	O
the	O
wafer	B-Architecture
is	O
thinned	O
to	O
the	O
target	O
thickness	O
while	O
mounted	O
on	O
a	O
special	O
adhesive	O
film	O
and	O
then	O
mounted	O
on	O
to	O
a	O
pick-up	O
tape	O
to	O
hold	O
the	O
dies	O
in	O
place	O
until	O
they	O
are	O
ready	O
for	O
the	O
packaging	O
step	O
.	O
</s>
<s>
Alternatively	O
,	O
plasma	O
dicing	O
may	O
be	O
used	O
,	O
which	O
replaces	O
the	O
dicer	O
's	O
saw	O
with	O
DRIE	B-Algorithm
plasma	O
etching	O
.	O
</s>
