<s>
Wafer	B-Algorithm
backgrinding	I-Algorithm
is	O
a	O
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
step	O
during	O
which	O
wafer	B-Architecture
thickness	O
is	O
reduced	O
to	O
allow	O
stacking	O
and	O
high-density	O
packaging	O
of	O
integrated	O
circuits	O
(	O
IC	O
)	O
.	O
</s>
<s>
ICs	O
are	O
produced	O
on	O
semiconductor	B-Architecture
wafers	I-Architecture
that	O
undergo	O
a	O
multitude	O
of	O
processing	O
steps	O
.	O
</s>
<s>
The	O
silicon	B-Architecture
wafers	I-Architecture
predominantly	O
used	O
today	O
have	O
diameters	O
of	O
200	O
and	O
300mm	O
.	O
</s>
<s>
The	O
backside	O
of	O
the	O
wafers	B-Architecture
are	O
thus	O
ground	O
prior	O
to	O
wafer	B-Algorithm
dicing	I-Algorithm
(	O
separation	O
of	O
the	O
individual	O
microchips	O
)	O
.	O
</s>
<s>
Wafers	B-Architecture
thinned	O
down	O
to	O
75	O
to	O
50	O
μm	O
are	O
common	O
today	O
.	O
</s>
<s>
Prior	O
to	O
grinding	O
,	O
wafers	B-Architecture
are	O
commonly	O
laminated	O
with	O
UV-curable	O
back-grinding	O
tape	O
,	O
which	O
ensures	O
against	O
wafer	B-Architecture
surface	O
damage	O
during	O
back-grinding	O
and	O
prevents	O
wafer	B-Architecture
surface	O
contamination	O
caused	O
by	O
infiltration	O
of	O
grinding	O
fluid	O
and/or	O
debris	O
.	O
</s>
<s>
The	O
wafers	B-Architecture
are	O
also	O
washed	O
with	O
deionized	O
water	O
throughout	O
the	O
process	O
,	O
which	O
helps	O
prevent	O
contamination	O
.	O
</s>
<s>
The	O
process	O
is	O
also	O
known	O
as	O
"	O
backlap	B-Algorithm
"	O
,	O
"	O
backfinish	O
"	O
or	O
"	O
wafer	B-Algorithm
thinning	I-Algorithm
"	O
.	O
</s>
