<s>
In	O
electronics	O
,	O
a	O
wafer	B-Architecture
(	O
also	O
called	O
a	O
slice	B-Architecture
or	O
substrate	B-Architecture
)	O
is	O
a	O
thin	O
slice	B-Architecture
of	O
semiconductor	O
,	O
such	O
as	O
a	O
crystalline	O
silicon	O
(	O
c-Si	O
)	O
,	O
used	O
for	O
the	B-Architecture
fabrication	I-Architecture
of	O
integrated	O
circuits	O
and	O
,	O
in	O
photovoltaics	O
,	O
to	O
manufacture	O
solar	O
cells	O
.	O
</s>
<s>
The	O
wafer	B-Architecture
serves	O
as	O
the	O
substrate	B-Architecture
for	O
microelectronic	O
devices	O
built	O
in	O
and	O
upon	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
It	O
undergoes	O
many	O
microfabrication	O
processes	O
,	O
such	O
as	O
doping	B-Algorithm
,	O
ion	O
implantation	O
,	O
etching	B-Algorithm
,	O
thin-film	O
deposition	O
of	O
various	O
materials	O
,	O
and	O
photolithographic	B-Algorithm
patterning	O
.	O
</s>
<s>
Finally	O
,	O
the	O
individual	O
microcircuits	O
are	O
separated	O
by	O
wafer	B-Algorithm
dicing	I-Algorithm
and	O
packaged	B-Algorithm
as	O
an	O
integrated	O
circuit	O
.	O
</s>
<s>
In	O
the	O
semiconductor	O
or	O
silicon	B-Architecture
wafer	I-Architecture
industry	O
,	O
the	O
term	O
wafer	B-Architecture
appeared	O
in	O
the	O
1950s	O
to	O
describe	O
a	O
thin	O
round	O
slice	B-Architecture
of	O
semiconductor	O
material	O
,	O
typically	O
germanium	O
or	O
silicon	O
.	O
</s>
<s>
Round	O
shape	O
comes	O
from	O
single-crystal	B-Algorithm
ingots	I-Algorithm
usually	O
produced	O
using	O
the	O
Czochralski	O
method	O
.	O
</s>
<s>
Silicon	B-Architecture
wafers	I-Architecture
were	O
first	O
introduced	O
in	O
the	O
1940s	O
.	O
</s>
<s>
By	O
1960	O
,	O
silicon	B-Architecture
wafers	I-Architecture
were	O
being	O
manufactured	O
in	O
the	O
U.S.	O
by	O
companies	O
such	O
as	O
MEMC/SunEdison	O
.	O
</s>
<s>
Silicon	B-Architecture
wafers	I-Architecture
are	O
made	O
by	O
companies	O
such	O
as	O
Sumco	O
,	O
Shin-Etsu	O
Chemical	O
,	O
Hemlock	O
Semiconductor	O
Corporation	O
and	O
Siltronic	O
.	O
</s>
<s>
Wafers	B-Architecture
are	O
formed	O
of	O
highly	O
pure	O
,	O
</s>
<s>
One	O
process	O
for	O
forming	O
crystalline	O
wafers	B-Architecture
is	O
known	O
as	O
the	O
Czochralski	O
method	O
,	O
invented	O
by	O
Polish	O
chemist	O
Jan	O
Czochralski	O
.	O
</s>
<s>
In	O
this	O
process	O
,	O
a	O
cylindrical	O
ingot	O
of	O
high	O
purity	O
monocrystalline	O
semiconductor	O
,	O
such	O
as	O
silicon	O
or	O
germanium	O
,	O
called	O
a	O
boule	B-Algorithm
,	O
is	O
formed	O
by	O
pulling	O
a	O
seed	O
crystal	O
from	O
a	O
melt	O
.	O
</s>
<s>
Donor	O
impurity	O
atoms	O
,	O
such	O
as	O
boron	O
or	O
phosphorus	O
in	O
the	O
case	O
of	O
silicon	O
,	O
can	O
be	O
added	O
to	O
the	O
molten	O
intrinsic	O
material	O
in	O
precise	O
amounts	O
in	O
order	O
to	O
dope	B-Algorithm
the	O
crystal	O
,	O
thus	O
changing	O
it	O
into	O
an	O
extrinsic	O
semiconductor	O
of	O
n-type	O
or	O
p-type	O
.	O
</s>
<s>
The	O
boule	B-Algorithm
is	O
then	O
sliced	O
with	O
a	O
wafer	B-Architecture
saw	O
(	O
a	O
type	O
of	O
wire	O
saw	O
)	O
,	O
machined	O
to	O
improve	O
flatness	O
,	O
chemically	O
etched	O
to	O
remove	O
crystal	O
damage	O
from	O
machining	O
steps	O
and	O
finally	O
polished	O
to	O
form	O
wafers	B-Architecture
.	O
</s>
<s>
The	O
size	O
of	O
wafers	B-Architecture
for	O
photovoltaics	O
is	O
100	O
–	O
200mm	O
square	O
and	O
the	O
thickness	O
is	O
100	O
–	O
500μm	O
.	O
</s>
<s>
Electronics	O
use	O
wafer	B-Architecture
sizes	O
from	O
100	O
to	O
450mm	O
diameter	O
.	O
</s>
<s>
The	O
largest	O
wafers	B-Architecture
made	O
have	O
a	O
diameter	O
of	O
450mm	O
,	O
but	O
are	O
not	O
yet	O
in	O
general	O
use	O
.	O
</s>
<s>
Wafers	B-Architecture
are	O
cleaned	O
with	O
weak	O
acids	O
to	O
remove	O
unwanted	O
particles	O
.	O
</s>
<s>
There	O
are	O
several	O
standard	O
cleaning	O
procedures	O
to	O
make	O
sure	O
the	O
surface	O
of	O
a	O
silicon	B-Architecture
wafer	I-Architecture
contains	O
no	O
contamination	O
.	O
</s>
<s>
One	O
of	O
the	O
most	O
effective	O
methods	O
is	O
RCA	B-Algorithm
clean	I-Algorithm
.	O
</s>
<s>
When	O
used	O
for	O
solar	O
cells	O
,	O
the	O
wafers	B-Architecture
are	O
textured	O
to	O
create	O
a	O
rough	O
surface	O
to	O
increase	O
surface	O
area	O
and	O
so	O
their	O
efficiency	O
.	O
</s>
<s>
The	O
generated	O
PSG	O
(	O
phosphosilicate	O
glass	O
)	O
is	O
removed	O
from	O
the	O
edge	O
of	O
the	O
wafer	B-Architecture
in	O
the	O
etching	B-Algorithm
.	O
</s>
<s>
Silicon	B-Architecture
wafers	I-Architecture
are	O
available	O
in	O
a	O
variety	O
of	O
diameters	O
from	O
25.4mm	O
(	O
1inch	O
)	O
to	O
300mm	O
(	O
11.8inches	O
)	O
.	O
</s>
<s>
Semiconductor	B-Algorithm
fabrication	I-Algorithm
plants	I-Algorithm
,	O
colloquially	O
known	O
as	O
fabs	B-Algorithm
,	O
are	O
defined	O
by	O
the	O
diameter	O
of	O
wafers	B-Architecture
that	O
they	O
are	O
tooled	O
to	O
produce	O
.	O
</s>
<s>
The	O
diameter	O
has	O
gradually	O
increased	O
to	O
improve	O
throughput	O
and	O
reduce	O
cost	O
with	O
the	O
current	O
state-of-the-art	O
fab	B-Algorithm
using	O
,	O
with	O
a	O
proposal	O
to	O
adopt	O
.	O
</s>
<s>
Intel	O
,	O
TSMC	O
,	O
and	O
Samsung	B-Application
were	O
separately	O
conducting	O
research	O
to	O
the	O
advent	O
of	O
"	O
prototype	B-Application
"	O
(	O
research	O
)	O
fabs	B-Algorithm
,	O
though	O
serious	O
hurdles	O
remain	O
.	O
</s>
<s>
Wafer	B-Architecture
size	O
Typical	O
thickness	O
Year	O
introduced	O
Weight	O
per	O
wafer	B-Architecture
100	O
mm2	O
(	O
10	O
mm	O
)	O
Die	O
per	O
wafer	B-Architecture
1960	O
275	O
μm	O
19699	O
375	O
μm	O
197229	O
525	O
μm	O
1976	O
10	O
grams	O
56	O
4.9	O
inch	O
(	O
125	O
mm	O
)	O
625	O
μm	O
198195	O
150	O
mm	O
(	O
5.9	O
inch	O
,	O
usually	O
referred	O
to	O
as	O
"	O
6	O
inch	O
"	O
)	O
675	O
μm	O
1983144	O
200	O
mm	O
(	O
7.9	O
inch	O
,	O
usually	O
referred	O
to	O
as	O
"	O
8	O
inch	O
"	O
)	O
725	O
μm	O
.	O
</s>
<s>
Wafers	B-Architecture
grown	O
using	O
materials	O
other	O
than	O
silicon	O
will	O
have	O
different	O
thicknesses	O
than	O
a	O
silicon	B-Architecture
wafer	I-Architecture
of	O
the	O
same	O
diameter	O
.	O
</s>
<s>
Wafer	B-Architecture
thickness	O
is	O
determined	O
by	O
the	O
mechanical	O
strength	O
of	O
the	O
material	O
used	O
;	O
the	O
wafer	B-Architecture
must	O
be	O
thick	O
enough	O
to	O
support	O
its	O
own	O
weight	O
without	O
cracking	O
during	O
handling	O
.	O
</s>
<s>
The	O
tabulated	O
thicknesses	O
relate	O
to	O
when	O
that	O
process	O
was	O
introduced	O
,	O
and	O
are	O
not	O
necessarily	O
correct	O
currently	O
,	O
for	O
example	O
the	O
IBM	O
BiCMOS7WL	O
process	O
is	O
on	O
8-inch	O
wafers	B-Architecture
,	O
but	O
these	O
are	O
only	O
200μm	O
thick	O
.	O
</s>
<s>
The	O
weight	O
of	O
the	O
wafer	B-Architecture
goes	O
up	O
along	O
with	O
its	O
thickness	O
and	O
diameter	O
.	O
</s>
<s>
A	O
unit	O
of	O
wafer	B-Algorithm
fabrication	I-Algorithm
step	O
,	O
such	O
as	O
an	O
etch	O
step	O
,	O
can	O
produce	O
more	O
chips	O
proportional	O
to	O
the	O
increase	O
in	O
wafer	B-Architecture
area	O
,	O
while	O
the	O
cost	O
of	O
the	O
unit	O
fabrication	B-Architecture
step	O
goes	O
up	O
more	O
slowly	O
than	O
the	O
wafer	B-Architecture
area	O
.	O
</s>
<s>
This	O
was	O
the	O
cost	O
basis	O
for	O
increasing	O
wafer	B-Architecture
size	O
.	O
</s>
<s>
Conversion	O
to	O
300mm	O
wafers	B-Architecture
from	O
200mm	O
wafers	B-Architecture
began	O
in	O
early	O
2000	O
,	O
and	O
reduced	O
the	O
price	O
per	O
die	O
for	O
about	O
30	O
–	O
40%	O
.	O
</s>
<s>
Larger	O
diameter	O
wafers	B-Architecture
allow	O
for	O
more	O
die	O
per	O
wafer	B-Architecture
.	O
</s>
<s>
M1	O
wafer	B-Architecture
size	O
(	O
156.75mm	O
)	O
is	O
in	O
the	O
process	O
of	O
being	O
phased	O
out	O
in	O
China	O
as	O
of	O
2020	O
.	O
</s>
<s>
Various	O
nonstandard	O
wafer	B-Architecture
sizes	O
have	O
arisen	O
,	O
so	O
efforts	O
to	O
fully	O
adopt	O
the	O
M10	O
standard	O
(	O
182mm	O
)	O
are	O
ongoing	O
.	O
</s>
<s>
Like	O
other	O
semiconductor	B-Architecture
fabrication	I-Architecture
processes	O
,	O
driving	O
down	O
costs	O
has	O
been	O
the	O
main	O
driving	O
factor	O
for	O
this	O
attempted	O
size	O
increase	O
,	O
in	O
spite	O
of	O
the	O
differences	O
in	O
the	O
manufacturing	O
processes	O
of	O
different	O
types	O
of	O
devices	O
.	O
</s>
<s>
Wafers	B-Architecture
are	O
grown	O
from	O
crystal	O
having	O
a	O
regular	O
crystal	O
structure	O
,	O
with	O
silicon	O
having	O
a	O
diamond	O
cubic	O
structure	O
with	O
a	O
lattice	O
spacing	O
of	O
5.430710	O
Å	O
(	O
0.5430710nm	O
)	O
.	O
</s>
<s>
When	O
cut	O
into	O
wafers	B-Architecture
,	O
the	O
surface	O
is	O
aligned	O
in	O
one	O
of	O
several	O
relative	O
directions	O
known	O
as	O
crystal	O
orientations	O
.	O
</s>
<s>
Ion	O
implantation	O
depths	O
depend	O
on	O
the	O
wafer	B-Architecture
's	O
crystal	O
orientation	O
,	O
since	O
each	O
direction	O
offers	O
distinct	O
paths	O
for	O
transport	O
.	O
</s>
<s>
Wafer	B-Architecture
cleavage	O
typically	O
occurs	O
only	O
in	O
a	O
few	O
well-defined	O
directions	O
.	O
</s>
<s>
Scoring	O
the	O
wafer	B-Architecture
along	O
cleavage	O
planes	O
allows	O
it	O
to	O
be	O
easily	O
diced	O
into	O
individual	O
chips	O
(	O
"	O
dies	O
"	O
)	O
so	O
that	O
the	O
billions	O
of	O
individual	O
circuit	O
elements	O
on	O
an	O
average	O
wafer	B-Architecture
can	O
be	O
separated	O
into	O
many	O
individual	O
circuits	O
.	O
</s>
<s>
Wafers	B-Architecture
under	O
200mm	O
diameter	O
have	O
flats	O
cut	O
into	O
one	O
or	O
more	O
sides	O
indicating	O
the	O
crystallographic	O
planes	O
of	O
the	O
wafer	B-Architecture
(	O
usually	O
a	O
 { 110 } 	O
face	O
)	O
.	O
</s>
<s>
In	O
earlier-generation	O
wafers	B-Architecture
a	O
pair	O
of	O
flats	O
at	O
different	O
angles	O
additionally	O
conveyed	O
the	O
doping	B-Algorithm
type	O
(	O
see	O
illustration	O
for	O
conventions	O
)	O
.	O
</s>
<s>
Wafers	B-Architecture
of	O
200mm	O
diameter	O
and	O
above	O
use	O
a	O
single	O
small	O
notch	O
to	O
convey	O
wafer	B-Architecture
orientation	O
,	O
with	O
no	O
visual	O
indication	O
of	O
doping	B-Algorithm
type	O
.	O
</s>
<s>
450	O
mm	O
wafers	B-Architecture
are	O
notchless	O
,	O
relying	O
on	O
a	O
laser	O
scribed	O
structure	O
on	O
the	O
wafer	B-Architecture
surface	O
for	O
orientation	O
.	O
</s>
<s>
Silicon	B-Architecture
wafers	I-Architecture
are	O
generally	O
not	O
100%	O
pure	O
silicon	O
,	O
but	O
are	O
instead	O
formed	O
with	O
an	O
initial	O
impurity	O
doping	B-Algorithm
concentration	O
between	O
1013	O
and	O
1016	O
atoms	O
per	O
cm3	O
of	O
boron	O
,	O
phosphorus	O
,	O
arsenic	O
,	O
or	O
antimony	O
which	O
is	O
added	O
to	O
the	O
melt	O
and	O
defines	O
the	O
wafer	B-Architecture
as	O
either	O
bulk	O
n-type	O
or	O
p-type	O
.	O
</s>
<s>
The	O
wafers	B-Architecture
can	O
also	O
be	O
initially	O
provided	O
with	O
some	O
interstitial	O
oxygen	O
concentration	O
.	O
</s>
<s>
There	O
are	O
also	O
issues	O
related	O
to	O
increased	O
inter-die	O
/	O
edge-to-edge	O
wafer	B-Architecture
variation	O
and	O
additional	O
edge	O
defects	O
.	O
</s>
<s>
450mm	O
wafers	B-Architecture
are	O
expected	O
to	O
cost	O
4	O
times	O
as	O
much	O
as	O
300mm	O
wafers	B-Architecture
,	O
and	O
equipment	O
costs	O
are	O
expected	O
to	O
rise	O
by	O
20	O
to	O
50%	O
.	O
</s>
<s>
Higher	O
cost	O
semiconductor	B-Architecture
fabrication	I-Architecture
equipment	O
for	O
larger	O
wafers	B-Architecture
increases	O
the	O
cost	O
of	O
450mm	O
fabs	B-Algorithm
(	O
semiconductor	B-Architecture
fabrication	I-Architecture
facilities	O
or	O
factories	O
)	O
.	O
</s>
<s>
Lithographer	O
Chris	O
Mack	O
claimed	O
in	O
2012	O
that	O
the	O
overall	O
price	O
per	O
die	O
for	O
450mm	O
wafers	B-Architecture
would	O
be	O
reduced	O
by	O
only	O
10	O
–	O
20%	O
compared	O
to	O
300mm	O
wafers	B-Architecture
,	O
because	O
over	O
50%	O
of	O
total	O
wafer	B-Architecture
processing	O
costs	O
are	O
lithography-related	O
.	O
</s>
<s>
Converting	O
to	O
larger	O
450mm	O
wafers	B-Architecture
would	O
reduce	O
price	O
per	O
die	O
only	O
for	O
process	O
operations	O
such	O
as	O
etch	O
where	O
cost	O
is	O
related	O
to	O
wafer	B-Architecture
count	O
,	O
not	O
wafer	B-Architecture
area	O
.	O
</s>
<s>
Cost	O
for	O
processes	O
such	O
as	O
lithography	O
is	O
proportional	O
to	O
wafer	B-Architecture
area	O
,	O
and	O
larger	O
wafers	B-Architecture
would	O
not	O
reduce	O
the	O
lithography	O
contribution	O
to	O
die	O
cost	O
.	O
</s>
<s>
In	O
November	O
2013	O
ASML	O
paused	O
development	O
of	O
450-mm	O
lithography	O
equipment	O
,	O
citing	O
uncertain	O
timing	O
of	O
chipmaker	B-Algorithm
demand	O
.	O
</s>
<s>
In	O
2012	O
,	O
a	O
group	O
consisting	O
of	O
New	O
York	O
State	O
(	O
SUNY	O
Poly/College	O
of	O
Nanoscale	O
Science	O
and	O
Engineering	O
(	O
CNSE	O
)	O
)	O
,	O
Intel	O
,	O
TSMC	O
,	O
Samsung	B-Application
,	O
IBM	O
,	O
Globalfoundries	O
and	O
Nikon	O
companies	O
has	O
formed	O
a	O
public-private	O
partnership	O
called	O
Global	O
450mm	O
Consortium	O
(	O
G450C	O
,	O
similar	O
to	O
SEMATECH	O
)	O
who	O
made	O
a	O
5-year	O
plan	O
(	O
expiring	O
in	O
2016	O
)	O
to	O
develop	O
a	O
"	O
cost	O
effective	O
wafer	B-Algorithm
fabrication	I-Algorithm
infrastructure	O
,	O
equipment	O
prototypes	B-Application
and	O
tools	O
to	O
enable	O
coordinated	O
industry	O
transition	O
to	O
450mm	O
wafer	B-Architecture
level	O
"	O
.	O
</s>
<s>
In	O
the	O
mid	O
of	O
2014	O
CNSE	O
has	O
announced	O
that	O
it	O
will	O
reveal	O
first	O
fully	O
patterned	O
450mm	O
wafers	B-Architecture
at	O
SEMICON	O
West	O
.	O
</s>
<s>
In	O
early	O
2017	O
,	O
the	O
G450C	O
began	O
to	O
dismantle	O
its	O
activities	O
over	O
450mm	O
wafer	B-Architecture
research	O
due	O
to	O
undisclosed	O
reasons	O
.	O
</s>
<s>
Mark	O
LaPedus	O
of	O
semiengineering.com	O
reported	O
in	O
mid-2014	O
that	O
chipmakers	B-Algorithm
had	O
delayed	O
adoption	O
of	O
450mm	O
"	O
for	O
the	O
foreseeable	O
future.	O
"	O
</s>
<s>
According	O
to	O
this	O
report	O
some	O
observers	O
expected	O
2018	O
to	O
2020	O
,	O
while	O
G	O
.	O
Dan	O
Hutcheson	O
,	O
chief	O
executive	O
of	O
VLSI	O
Research	O
,	O
did	O
n't	O
see	O
450mm	O
fabs	B-Algorithm
moving	O
into	O
production	O
until	O
2020	O
to	O
2025	O
.	O
</s>
<s>
The	O
step	O
up	O
to	O
300mm	O
required	O
major	O
changes	O
,	O
with	O
fully	O
automated	O
factories	O
using	O
300mm	O
wafers	B-Architecture
versus	O
barely	O
automated	O
factories	O
for	O
the	O
200mm	O
wafers	B-Architecture
,	O
partly	O
because	O
a	O
FOUP	B-Algorithm
for	O
300mm	O
wafers	B-Architecture
weighs	O
about	O
7.5	O
kilograms	O
when	O
loaded	O
with	O
25	O
300mm	O
wafers	B-Architecture
where	O
a	O
SMIF	B-Algorithm
weighs	O
about	O
4.8	O
kilograms	O
when	O
loaded	O
with	O
25	O
200mm	O
wafers	B-Architecture
,	O
thus	O
requiring	O
twice	O
the	O
amount	O
of	O
physical	O
strength	O
from	O
factory	O
workers	O
,	O
and	O
increasing	O
fatigue	O
.	O
</s>
<s>
300mm	O
FOUPs	B-Algorithm
have	O
handles	O
so	O
that	O
they	O
can	O
be	O
still	O
be	O
moved	O
by	O
hand	O
.	O
</s>
<s>
450mm	O
FOUPs	B-Algorithm
weigh	O
45	O
kilograms	O
when	O
loaded	O
with	O
25	O
450mm	O
wafers	B-Architecture
,	O
thus	O
cranes	O
are	O
necessary	O
to	O
manually	O
handle	O
the	O
FOUPs	B-Algorithm
and	O
handles	O
are	O
no	O
longer	O
present	O
in	O
the	O
FOUP	B-Algorithm
.	O
</s>
<s>
FOUPs	B-Algorithm
are	O
moved	O
around	O
using	O
material	O
handling	O
systems	O
from	O
Muratec	O
or	O
Daifuku	O
.	O
</s>
<s>
All	O
told	O
,	O
the	O
development	O
of	O
450mm	O
wafers	B-Architecture
requires	O
significant	O
engineering	O
,	O
time	O
,	O
and	O
cost	O
to	O
overcome	O
.	O
</s>
<s>
In	O
order	O
to	O
minimize	O
the	O
cost	O
per	O
die	O
,	O
manufacturers	O
wish	O
to	O
maximize	O
the	O
number	O
of	O
dies	O
that	O
can	O
be	O
made	O
from	O
a	O
single	O
wafer	B-Architecture
;	O
dies	O
always	O
have	O
a	O
square	O
or	O
rectangular	O
shape	O
due	O
to	O
the	O
constraint	O
of	O
wafer	B-Algorithm
dicing	I-Algorithm
.	O
</s>
<s>
In	O
general	O
,	O
this	O
is	O
a	O
computationally	O
complex	O
problem	O
with	O
no	O
analytical	O
solution	O
,	O
dependent	O
on	O
both	O
the	O
area	O
of	O
the	O
dies	O
as	O
well	O
as	O
their	O
aspect	B-Device
ratio	I-Device
(	O
square	O
or	O
rectangular	O
)	O
and	O
other	O
considerations	O
such	O
as	O
the	O
width	O
of	O
the	O
scribeline	O
or	O
saw	O
lane	O
,	O
and	O
additional	O
space	O
occupied	O
by	O
alignment	O
and	O
test	B-Algorithm
structures	I-Algorithm
.	O
</s>
<s>
Note	O
that	O
gross	O
DPW	O
formulas	O
account	O
only	O
for	O
wafer	B-Architecture
area	O
that	O
is	O
lost	O
because	O
it	O
cannot	O
be	O
used	O
to	O
make	O
physically	O
complete	O
dies	O
;	O
gross	O
DPW	O
calculations	O
do	O
not	O
account	O
for	O
yield	O
loss	O
due	O
to	O
defects	O
or	O
parametric	O
issues	O
.	O
</s>
<s>
Nevertheless	O
,	O
the	O
number	O
of	O
gross	O
die	O
per	O
wafer	B-Architecture
(	O
DPW	O
)	O
can	O
be	O
estimated	O
starting	O
with	O
the	O
first-order	B-Algorithm
approximation	I-Algorithm
or	O
floor	O
function	O
of	O
wafer-to-die	O
area	O
ratio	O
,	O
</s>
<s>
This	O
formula	O
simply	O
states	O
that	O
the	O
number	O
of	O
dies	O
which	O
can	O
fit	O
on	O
the	O
wafer	B-Architecture
cannot	O
exceed	O
the	O
area	O
of	O
the	O
wafer	B-Architecture
divided	O
by	O
the	O
area	O
of	O
each	O
individual	O
die	O
.	O
</s>
<s>
It	O
will	O
always	O
overestimate	O
the	O
true	O
best-case	O
gross	O
DPW	O
,	O
since	O
it	O
includes	O
the	O
area	O
of	O
partially	O
patterned	O
dies	O
which	O
do	O
not	O
fully	O
lie	O
on	O
the	O
wafer	B-Architecture
surface	O
(	O
see	O
figure	O
)	O
.	O
</s>
<s>
Refinements	O
of	O
this	O
simple	O
formula	O
typically	O
add	O
an	O
edge	O
correction	O
,	O
to	O
account	O
for	O
partial	O
dies	O
on	O
the	O
edge	O
,	O
which	O
in	O
general	O
will	O
be	O
more	O
significant	O
when	O
the	O
area	O
of	O
the	O
die	O
is	O
large	O
compared	O
to	O
the	O
total	O
area	O
of	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
In	O
the	O
other	O
limiting	O
case	O
(	O
infinitesimally	O
small	O
dies	O
or	O
infinitely	O
large	O
wafers	B-Architecture
)	O
,	O
the	O
edge	O
correction	O
is	O
negligible	O
.	O
</s>
<s>
Studies	O
comparing	O
these	O
analytical	O
formulas	O
to	O
brute-force	B-Algorithm
computational	O
results	O
show	O
that	O
the	O
formulas	O
can	O
be	O
made	O
more	O
accurate	O
,	O
over	O
practical	O
ranges	O
of	O
die	O
sizes	O
and	O
aspect	B-Device
ratios	I-Device
,	O
by	O
adjusting	O
the	O
coefficients	O
of	O
the	O
corrections	O
to	O
values	O
above	O
or	O
below	O
unity	O
,	O
and	O
by	O
replacing	O
the	O
linear	O
die	O
dimension	O
with	O
(	O
average	O
side	O
length	O
)	O
in	O
the	O
case	O
of	O
dies	O
with	O
large	O
aspect	B-Device
ratio	I-Device
:	O
</s>
<s>
While	O
silicon	O
is	O
the	O
prevalent	O
material	O
for	O
wafers	B-Architecture
used	O
in	O
the	O
electronics	O
industry	O
,	O
other	O
compound	O
III-V	O
or	O
II-VI	O
materials	O
have	O
also	O
been	O
employed	O
.	O
</s>
<s>
Gallium	O
arsenide	O
(	O
GaAs	O
)	O
,	O
a	O
III-V	O
semiconductor	O
produced	O
via	O
the	O
Czochralski	O
method	O
,	O
gallium	O
nitride	O
(	O
GaN	O
)	O
and	O
silicon	O
carbide	O
(	O
SiC	O
)	O
are	O
also	O
common	O
wafer	B-Architecture
materials	O
,	O
with	O
GaN	O
and	O
sapphire	B-Application
being	O
extensively	O
used	O
in	O
LED	O
manufacturing	O
.	O
</s>
