<s>
Wafer-scale	B-Algorithm
integration	I-Algorithm
(	O
WSI	O
)	O
is	O
a	O
rarely	O
used	O
system	O
of	O
building	O
very-large	O
integrated	O
circuit	O
(	O
commonly	O
called	O
a	O
"	O
chip	O
"	O
)	O
networks	O
from	O
an	O
entire	O
silicon	B-Architecture
wafer	I-Architecture
to	O
produce	O
a	O
single	O
"	O
super-chip	O
"	O
.	O
</s>
<s>
Combining	O
large	O
size	O
and	O
reduced	O
packaging	O
,	O
WSI	O
was	O
expected	O
to	O
lead	O
to	O
dramatically	O
reduced	O
costs	O
for	O
some	O
systems	O
,	O
notably	O
massively	B-Operating_System
parallel	I-Operating_System
supercomputers	B-Architecture
.	O
</s>
<s>
In	O
the	O
normal	O
integrated	O
circuit	O
manufacturing	O
process	O
,	O
a	O
single	O
large	O
cylindrical	O
crystal	O
(	O
boule	B-Algorithm
)	O
of	O
silicon	O
is	O
produced	O
and	O
then	O
cut	O
into	O
disks	O
known	O
as	O
wafers	B-Architecture
.	O
</s>
<s>
The	O
wafers	B-Architecture
are	O
then	O
cleaned	O
and	O
polished	O
in	O
preparation	O
for	O
the	O
fabrication	O
process	O
.	O
</s>
<s>
A	O
photographic	O
process	O
is	O
used	O
to	O
pattern	O
the	O
surface	O
where	O
material	O
ought	O
to	O
be	O
deposited	O
on	O
top	O
of	O
the	O
wafer	B-Architecture
and	O
where	O
not	O
to	O
.	O
</s>
<s>
From	O
then	O
on	O
the	O
wafer	B-Architecture
is	O
repeatedly	O
processed	O
in	O
this	O
fashion	O
,	O
putting	O
on	O
layer	O
after	O
layer	O
of	O
circuitry	O
on	O
the	O
surface	O
.	O
</s>
<s>
Multiple	O
copies	O
of	O
these	O
patterns	O
are	O
deposited	O
on	O
the	O
wafer	B-Architecture
in	O
a	O
grid	O
fashion	O
across	O
the	O
surface	O
of	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
After	O
all	O
the	O
possible	O
locations	O
are	O
patterned	O
,	O
the	O
wafer	B-Architecture
surface	O
appears	O
like	O
a	O
sheet	O
of	O
graph	O
paper	O
,	O
with	O
grid	O
lines	O
delineating	O
the	O
individual	O
chips	O
.	O
</s>
<s>
Those	O
locations	O
that	O
are	O
found	O
to	O
be	O
defective	O
are	O
recorded	O
and	O
marked	O
with	O
a	O
dot	O
of	O
paint	O
(	O
this	O
process	O
is	O
referred	O
to	O
as	O
"	O
inking	O
a	O
die	O
"	O
and	O
more	O
modern	O
wafer	B-Architecture
fabrication	O
techniques	O
no	O
longer	O
require	O
physical	O
markings	O
to	O
identify	O
defective	O
die	O
)	O
.	O
</s>
<s>
The	O
wafer	B-Architecture
is	O
then	O
sawed	O
apart	O
to	O
cut	O
out	O
the	O
individual	O
chips	O
.	O
</s>
<s>
Flaws	O
on	O
the	O
surface	O
of	O
the	O
wafers	B-Architecture
and	O
problems	O
during	O
the	O
layering/depositing	O
process	O
are	O
impossible	O
to	O
avoid	O
,	O
and	O
cause	O
some	O
of	O
the	O
individual	O
chips	O
to	O
be	O
defective	O
.	O
</s>
<s>
The	O
revenue	O
from	O
the	O
remaining	O
working	O
chips	O
has	O
to	O
pay	O
for	O
the	O
entire	O
cost	O
of	O
the	O
wafer	B-Architecture
and	O
its	O
processing	O
,	O
including	O
those	O
discarded	O
defective	O
chips	O
.	O
</s>
<s>
In	O
order	O
to	O
maximize	O
yield	O
one	O
wants	O
to	O
make	O
the	O
chips	O
as	O
small	O
as	O
possible	O
,	O
so	O
that	O
a	O
higher	O
number	O
of	O
working	O
chips	O
can	O
be	O
obtained	O
per	O
wafer	B-Architecture
.	O
</s>
<s>
Wafer-scale	B-Algorithm
integration	I-Algorithm
seeks	O
to	O
reduce	O
this	O
cost	O
,	O
as	O
well	O
as	O
improve	O
performance	O
,	O
by	O
building	O
larger	O
chips	O
in	O
a	O
single	O
package	O
in	O
principle	O
,	O
chips	O
as	O
large	O
as	O
a	O
full	O
wafer	B-Architecture
.	O
</s>
<s>
Of	O
course	O
this	O
is	O
not	O
easy	O
,	O
since	O
given	O
the	O
flaws	O
on	O
the	O
wafers	B-Architecture
a	O
single	O
large	O
design	O
printed	O
onto	O
a	O
wafer	B-Architecture
would	O
almost	O
always	O
not	O
work	O
.	O
</s>
<s>
It	O
has	O
been	O
an	O
ongoing	O
goal	O
to	O
develop	O
methods	O
to	O
handle	O
faulty	O
areas	O
of	O
the	O
wafers	B-Architecture
through	O
logic	O
,	O
as	O
opposed	O
to	O
sawing	O
them	O
out	O
of	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
If	O
the	O
resulting	O
wafer	B-Architecture
has	O
enough	O
working	O
sub-circuits	O
,	O
it	O
can	O
be	O
used	O
despite	O
faults	O
.	O
</s>
<s>
Another	O
approach	O
–	O
silicon-interconnect	O
fabric	O
(	O
Si-IF	O
)	O
–	O
has	O
neither	O
on	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
Si-IF	O
puts	O
only	O
relatively	O
low-density	O
metal	O
layers	O
on	O
the	O
wafer	B-Architecture
,	O
roughly	O
the	O
same	O
density	O
as	O
the	O
upper	O
layers	O
of	O
a	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
,	O
using	O
the	O
wafer	B-Architecture
only	O
for	O
interconnects	O
between	O
tightly-packed	O
small	O
bare	O
chiplets	O
.	O
</s>
<s>
Texas	O
Instruments	O
and	O
ITT	O
Corporation	O
both	O
saw	O
it	O
as	O
a	O
way	O
to	O
develop	O
complex	O
pipelined	B-General_Concept
microprocessors	B-Architecture
and	O
re-enter	O
a	O
market	O
where	O
they	O
were	O
losing	O
ground	O
,	O
but	O
neither	O
released	O
any	O
products	O
.	O
</s>
<s>
Gene	O
Amdahl	O
also	O
attempted	O
to	O
develop	O
WSI	O
as	O
a	O
method	O
of	O
making	O
a	O
supercomputer	B-Architecture
,	O
starting	O
Trilogy	O
Systems	O
in	O
1980	O
and	O
garnering	O
investments	O
from	O
Groupe	O
Bull	O
,	O
Sperry	O
Rand	O
and	O
Digital	O
Equipment	O
Corporation	O
,	O
who	O
(	O
along	O
with	O
others	O
)	O
provided	O
an	O
estimated	O
$230	O
million	O
in	O
financing	O
.	O
</s>
<s>
He	O
used	O
Trilogy	O
's	O
remaining	O
seed	O
capital	O
to	O
buy	O
Elxsi	O
,	O
a	O
maker	O
of	O
VAX-compatible	O
computers	O
,	O
in	O
1985	O
.	O
</s>
<s>
In	O
1989	O
Anamartic	O
developed	O
a	O
wafer	B-Architecture
stack	O
memory	O
based	O
on	O
the	O
technology	O
of	O
Ivor	O
Catt	O
,	O
but	O
the	O
company	O
was	O
unable	O
to	O
ensure	O
a	O
large	O
enough	O
supply	O
of	O
silicon	B-Architecture
wafers	I-Architecture
and	O
folded	O
in	O
1992	O
.	O
</s>
<s>
On	O
August	O
19	O
,	O
2019	O
,	O
American	O
computer	O
systems	O
company	O
Cerebras	O
Systems	O
presented	O
their	O
development	O
progress	O
of	O
WSI	O
for	O
deep	B-General_Concept
learning	I-General_Concept
acceleration	I-General_Concept
.	O
</s>
<s>
Cerebras	O
 '	O
Wafer-Scale	O
Engine	O
(	O
WSE-1	O
)	O
chip	O
is	O
46,225	O
mm2	O
(	O
215mm	O
×	O
215mm	O
)	O
,	O
around	O
56×	O
larger	O
than	O
the	O
largest	O
GPU	O
die	O
.	O
</s>
<s>
The	O
WSE-1	O
features	O
1.2	O
trillion	O
transistors	O
,	O
400,000	O
AI	O
cores	O
,	O
18GB	O
of	O
on-chip	O
SRAM	O
,	O
100Pbit/s	O
on-wafer	O
fabric	O
bandwidth	O
,	O
and	O
1.2Pbit/s	O
I/O	O
off-wafer	O
bandwidth	O
.	O
</s>
<s>
Compared	O
to	O
the	O
Joule	O
Supercomputer	B-Architecture
at	O
NETL	O
,	O
the	O
CS-1	O
was	O
200	O
times	O
faster	O
,	O
while	O
using	O
much	O
less	O
power	O
.	O
</s>
