<s>
The	O
Western	O
Design	O
Center	O
(	O
WDC	O
)	O
W65C265S	O
is	O
a	O
16-bit	O
CMOS	O
microcontroller	B-Architecture
based	O
on	O
a	O
W65C816S	B-General_Concept
processor	O
core	O
,	O
which	O
is	O
a	O
superset	O
of	O
the	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
processor	O
.	O
</s>
<s>
The	O
W65C265S	O
consists	O
of	O
a	O
fully	O
static	O
W65C816S	B-General_Concept
CPU	B-General_Concept
core	O
,	O
8KB	O
of	O
ROM	B-Device
containing	O
a	O
machine	B-General_Concept
language	I-General_Concept
monitor	I-General_Concept
,	O
576	O
bytes	B-Application
of	O
SRAM	B-Architecture
,	O
a	O
processor	B-General_Concept
cache	I-General_Concept
under	O
software	O
control	O
,	O
eight	O
16-bit	O
timers	O
with	O
maskable	O
interrupts	O
,	O
an	O
interrupt-driven	O
parallel	O
bus	O
(	O
PIB	O
)	O
,	O
four	O
universal	O
asynchronous	O
receiver-transmitters	O
(	O
UARTs	O
)	O
,	O
a	O
watchdog	B-Application
timer	I-Application
that	O
fires	O
a	O
restart	O
interrupt	O
,	O
twenty-nine	O
priority	O
encoded	O
interrupts	O
,	O
a	O
time-of-day	O
clock	O
,	O
two	O
sound	O
generators	O
,	O
a	O
bus	O
control	O
register	O
(	O
BCR	O
)	O
for	O
external	O
memory	O
bus	O
control	O
,	O
interface	O
circuitry	O
for	O
peripheral	O
devices	O
,	O
ABORT	O
input	O
for	O
low	O
cost	O
virtual	O
memory	O
interface	O
,	O
and	O
many	O
low	O
power	O
features	O
.	O
</s>
