<s>
The	O
W65C22	O
versatile	B-Device
interface	I-Device
adapter	I-Device
(	O
VIA	O
)	O
is	O
an	O
input/output	B-General_Concept
device	I-General_Concept
for	O
use	O
with	O
the	O
65xx	B-General_Concept
series	I-General_Concept
microprocessor	O
family	O
.	O
</s>
<s>
Designed	O
by	O
the	O
Western	O
Design	O
Center	O
,	O
the	O
W65C22	O
is	O
made	O
in	O
two	O
versions	O
,	O
both	O
of	O
which	O
are	O
rated	O
for	O
14	O
megahertz	O
operation	O
,	O
and	O
available	O
in	O
DIP-40	B-Algorithm
or	O
PLCC-44	B-Algorithm
packages	O
.	O
</s>
<s>
W65C22N	O
:	O
This	O
device	O
is	O
fully	O
compatible	O
with	O
the	O
NMOS	B-Device
6522	I-Device
produced	O
by	O
MOS	B-Architecture
Technology	I-Architecture
and	O
others	O
,	O
and	O
includes	O
current-limiting	O
resistors	O
on	O
its	O
output	O
lines	O
.	O
</s>
<s>
The	O
W65C22N	O
has	O
an	O
open-drain	O
interrupt	B-Application
output	I-Application
(	O
the	O
pin	O
)	O
that	O
is	O
compatible	O
with	O
a	O
wired-OR	O
interrupt	B-Application
circuit	O
.	O
</s>
<s>
Hence	O
the	O
DIP-40	B-Algorithm
version	O
is	O
a	O
"	O
drop-in	O
"	O
replacement	O
for	O
the	O
NMOS	O
part	O
.	O
</s>
<s>
The	O
W65C22S	O
 '	O
output	O
is	O
a	O
totem	O
pole	O
configuration	O
,	O
and	O
thus	O
cannot	O
be	O
directly	O
connected	O
to	O
a	O
wired-OR	O
interrupt	B-Application
circuit	O
.	O
</s>
<s>
As	O
with	O
the	O
NMOS	B-Device
6522	I-Device
,	O
the	O
W65C22	O
includes	O
functions	O
for	O
programmed	O
control	O
of	O
two	O
peripheral	O
ports	O
(	O
ports	O
A	O
and	O
B	O
)	O
.	O
</s>
<s>
Two	O
programcontrolled	O
8-bit	O
bi-directional	O
peripheral	O
I/O	B-Architecture
ports	I-Architecture
allow	O
direct	O
interfacing	O
between	O
the	O
microprocessor	O
and	O
selected	O
peripheral	O
units	O
.	O
</s>
<s>
Each	O
port	O
has	O
input	B-General_Concept
data	I-General_Concept
latching	O
capability	O
.	O
</s>
<s>
Two	O
programmable	O
data	O
direction	O
registers	O
(	O
A	O
and	O
B	O
)	O
allow	O
selection	O
of	O
data	O
direction	O
(	O
input	O
or	O
output	O
)	O
on	O
an	O
individual	O
I/O	B-General_Concept
line	O
basis	O
.	O
</s>
<s>
In	O
either	O
mode	O
,	O
a	O
timer	O
can	O
generate	O
an	O
interrupt	B-Application
when	O
it	O
has	O
counted	O
down	O
to	O
zero	O
.	O
</s>
<s>
Timer	O
2	O
functions	O
as	O
an	O
interval	B-Device
counter	I-Device
or	O
a	O
pulse	B-Algorithm
counter	I-Algorithm
.	O
</s>
<s>
If	O
operating	O
as	O
an	O
interval	B-Device
counter	I-Device
,	O
timer	O
2	O
is	O
driven	O
by	O
the	O
microprocessor	O
's	O
PHI2	O
clock	O
source	O
.	O
</s>
<s>
As	O
a	O
pulse	B-Algorithm
counter	I-Algorithm
,	O
timer	O
2	O
is	O
triggered	O
by	O
an	O
external	O
pulse	O
source	O
on	O
the	O
chip	O
's	O
line	O
.	O
</s>
<s>
Application	O
versatility	O
is	O
further	O
increased	O
by	O
various	O
control	O
registers	O
,	O
including	O
an	O
interrupt	B-Application
flag	O
register	O
,	O
an	O
interrupt	B-Application
enable	O
register	O
and	O
two	O
Function	O
Control	O
Registers	O
.	O
</s>
