<s>
The	O
W65C21S	O
is	O
a	O
very	O
flexible	O
Peripheral	B-General_Concept
Interface	I-General_Concept
Adapter	I-General_Concept
(	O
PIA	O
)	O
for	O
use	O
with	O
WDC	O
’s	O
65xx	O
and	O
other	O
8-bit	O
microprocessor	O
families	O
.	O
</s>
<s>
Peripheral	O
device	O
control	O
is	O
accomplished	O
through	O
two	O
8-bit	O
bidirectional	O
I/O	B-General_Concept
Ports	O
,	O
with	O
individually	O
designed	O
Data	O
Direction	O
Registers	O
.	O
</s>
<s>
The	O
Data	O
Direction	O
Registers	O
provide	O
selection	O
of	O
data	O
flow	O
direction	O
(	O
input	O
or	O
output	O
)	O
at	O
each	O
respective	O
I/O	B-General_Concept
Port	O
.	O
</s>
<s>
Data	O
flow	O
direction	O
may	O
be	O
selected	O
on	O
a	O
line-by-line	O
basis	O
with	O
intermixed	O
input	B-General_Concept
and	I-General_Concept
output	I-General_Concept
lines	O
within	O
the	O
same	O
port	O
.	O
</s>
<s>
This	O
capability	O
provides	O
enhanced	O
control	O
over	O
data	O
transfer	O
functions	O
between	O
the	O
microprocessor	O
and	O
peripheral	O
devices	O
,	O
as	O
well	O
as	O
bidirectional	O
data	O
transfer	O
between	O
W65C21S	O
Peripheral	B-General_Concept
Interface	I-General_Concept
Adapters	I-General_Concept
in	O
multiprocessor	O
systems	O
.	O
</s>
<s>
Two	O
8-bit	O
bidirectional	O
I/O	B-General_Concept
ports	O
with	O
individual	O
data	O
direction	O
control	O
.	O
</s>
