<s>
The	O
Western	O
Design	O
Center	O
(	O
WDC	O
)	O
W65C134S	O
is	O
an	O
8-bit	O
CMOS	O
microcontroller	B-Architecture
based	O
on	O
a	O
W65C02S	B-General_Concept
processor	O
core	O
,	O
which	O
is	O
a	O
superset	O
of	O
the	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
processor	O
.	O
</s>
<s>
The	O
W65C134S	O
consists	O
of	O
a	O
fully	O
static	O
8-bit	O
W65C02S	B-General_Concept
CPU	B-General_Concept
core	O
,	O
4KB	O
of	O
ROM	B-Device
containing	O
a	O
machine	B-General_Concept
language	I-General_Concept
monitor	I-General_Concept
,	O
192	O
bytes	O
of	O
SRAM	B-Architecture
,	O
two	O
16	O
bit	O
timers	O
,	O
one	O
16-bit	O
Watch-Dog	B-Application
Timer	I-Application
(	O
WDT	O
)	O
with	O
"	O
restart	O
"	O
interrupt	O
,	O
one	O
UART	O
with	O
baud	O
rate	O
timer	O
,	O
a	O
low	O
power	O
Serial	O
Interface	O
Bus	O
(	O
SIB	O
)	O
configured	O
as	O
a	O
token	O
passing	O
Local	B-General_Concept
Area	I-General_Concept
Network	I-General_Concept
,	O
twenty-two	O
priority	O
encoded	O
interrupts	O
,	O
two	O
crystal	O
inputs	O
(	O
slow	O
32.768KHz	O
and	O
fast	O
up	O
to	O
8-MHz	O
)	O
,	O
Bus	O
Control	O
Register	O
(	O
BCR	O
)	O
for	O
external	O
memory	O
bus	O
control	O
,	O
interface	O
circuitry	O
for	O
peripheral	O
devices	O
,	O
and	O
many	O
low	O
power	O
features	O
.	O
</s>
