<s>
The	O
Western	O
Design	O
Center	O
(	O
WDC	O
)	O
65C02	B-General_Concept
microprocessor	I-General_Concept
is	O
an	O
enhanced	O
CMOS	B-Device
version	O
of	O
the	O
popular	O
nMOS-based	O
8-bit	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
.	O
</s>
<s>
The	O
65C02	B-General_Concept
fixed	O
several	O
problems	O
in	O
the	O
original	O
6502	B-General_Concept
and	O
added	O
some	O
new	O
instructions	O
,	O
but	O
its	O
main	O
feature	O
was	O
greatly	O
lowered	O
power	O
usage	O
,	O
on	O
the	O
order	O
of	O
10	O
to	O
20	O
times	O
less	O
than	O
the	O
original	O
6502	B-General_Concept
running	O
at	O
the	O
same	O
speed	O
.	O
</s>
<s>
The	O
reduced	O
power	O
consumption	O
made	O
the	O
65C02	B-General_Concept
useful	O
in	O
portable	B-Device
computer	I-Device
roles	O
and	O
microcontroller	B-Architecture
systems	O
in	O
industrial	O
settings	O
.	O
</s>
<s>
It	O
has	O
been	O
used	O
in	O
some	O
home	O
computers	O
,	O
as	O
well	O
as	O
in	O
embedded	B-Architecture
applications	O
,	O
including	O
medical-grade	O
implanted	O
devices	O
.	O
</s>
<s>
Development	O
of	O
the	O
WDC	B-General_Concept
65C02	I-General_Concept
began	O
in	O
1981	O
with	O
samples	O
released	O
in	O
early	O
1983	O
.	O
</s>
<s>
Rockwell	O
's	O
primary	O
interest	O
was	O
in	O
the	O
embedded	B-Architecture
market	O
and	O
asked	O
for	O
several	O
new	O
commands	O
to	O
be	O
added	O
to	O
aid	O
in	O
this	O
role	O
.	O
</s>
<s>
Sanyo	O
later	O
licensed	O
the	O
design	O
as	O
well	O
,	O
and	O
Seiko	O
Epson	O
produced	O
a	O
further	O
modified	O
version	O
as	O
the	O
HuC6280	B-General_Concept
.	O
</s>
<s>
Early	O
versions	O
used	O
40-pin	O
DIP	B-Algorithm
packaging	O
,	O
and	O
were	O
available	O
in	O
1	O
,	O
2	O
and	O
4MHz	O
versions	O
,	O
matching	O
the	O
speeds	O
of	O
the	O
original	O
nMOS	B-Algorithm
versions	O
.	O
</s>
<s>
Later	O
versions	O
were	O
produced	O
in	O
PLCC	O
and	O
QFP	B-Algorithm
packages	O
,	O
as	O
well	O
as	O
PDIP	B-Algorithm
,	O
and	O
with	O
much	O
higher	O
clock	O
speed	O
ratings	O
.	O
</s>
<s>
The	O
current	O
version	O
from	O
WDC	O
,	O
the	O
W65C02S-14	O
has	O
a	O
fully	O
static	O
core	O
and	O
officially	O
runs	O
at	O
speeds	O
up	O
to	O
14MHz	O
when	O
powered	O
at	O
5	O
volts	O
.	O
</s>
<s>
The	O
65C02	B-General_Concept
is	O
a	O
low	O
cost	O
,	O
general-purpose	O
8-bit	O
microprocessor	B-Architecture
(	O
8-bit	O
registers	O
and	O
data	B-General_Concept
bus	I-General_Concept
)	O
with	O
a	O
16-bit	B-Device
program	B-General_Concept
counter	I-General_Concept
and	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
register	B-General_Concept
set	O
is	O
small	O
,	O
with	O
a	O
single	O
8-bit	O
accumulator	B-General_Concept
(	O
A	O
)	O
,	O
two	O
8-bit	O
index	B-General_Concept
registers	I-General_Concept
(	O
X	O
and	O
Y	O
)	O
,	O
an	O
8-bit	O
status	B-General_Concept
register	I-General_Concept
(	O
P	O
)	O
,	O
and	O
a	O
16-bit	B-Device
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
single	O
accumulator	B-General_Concept
,	O
the	O
first	O
256	O
bytes	O
of	O
RAM	O
,	O
the	O
"	O
zero	B-General_Concept
page	I-General_Concept
"	O
( $0000	O
to	O
$00FF	O
)	O
,	O
allow	O
faster	O
access	O
through	O
addressing	B-Language
modes	I-Language
that	O
use	O
an	O
8-bit	O
memory	O
address	O
instead	O
of	O
a	O
16-bit	B-Device
address	O
.	O
</s>
<s>
The	O
stack	B-Application
lies	O
in	O
the	O
next	O
256	O
bytes	O
,	O
page	O
one	O
( $0100	O
to	O
$01FF	O
)	O
,	O
and	O
cannot	O
be	O
moved	O
or	O
extended	O
.	O
</s>
<s>
The	O
stack	B-Application
grows	O
backwards	O
with	O
the	O
stack	B-Application
pointer	O
(	O
S	O
)	O
starting	O
at	O
$01FF	O
and	O
decrementing	O
as	O
the	O
stack	B-Application
grows	O
.	O
</s>
<s>
It	O
has	O
a	O
variable-length	O
instruction	B-General_Concept
set	I-General_Concept
,	O
varying	O
between	O
one	O
and	O
three	O
bytes	O
per	O
instruction	B-General_Concept
.	O
</s>
<s>
The	O
basic	O
architecture	O
of	O
the	O
65C02	B-General_Concept
is	O
identical	O
to	O
the	O
original	O
6502	B-General_Concept
,	O
and	O
can	O
be	O
considered	O
a	O
low-power	O
implementation	O
of	O
that	O
design	O
.	O
</s>
<s>
At	O
1MHz	O
,	O
the	O
most	O
popular	O
speed	O
for	O
the	O
original	O
6502	B-General_Concept
,	O
the	O
65C02	B-General_Concept
requires	O
only	O
20mW	O
,	O
while	O
the	O
original	O
uses	O
450mW	O
,	O
a	O
reduction	O
of	O
over	O
twenty	O
times	O
.	O
</s>
<s>
The	O
manually	O
optimized	O
core	O
and	O
low	O
power	O
use	O
is	O
intended	O
to	O
make	O
the	O
65C02	B-General_Concept
well	O
suited	O
for	O
low	O
power	O
system-on-chip	B-Architecture
(	O
SoC	O
)	O
designs	O
.	O
</s>
<s>
A	O
Verilog	B-Language
hardware	O
description	O
model	O
is	O
available	O
for	O
designing	O
the	O
W65C02S	B-General_Concept
core	O
into	O
an	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
or	O
a	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
.	O
</s>
<s>
As	O
is	O
common	O
in	O
the	O
semiconductor	O
industry	O
,	O
WDC	O
offers	O
a	O
development	O
system	O
,	O
which	O
includes	O
a	O
developer	O
board	O
,	O
an	O
in-circuit	B-Application
emulator	I-Application
(	O
ICE	O
)	O
and	O
a	O
software	O
development	O
system	O
.	O
</s>
<s>
The	O
W65C02S	B-General_Concept
–	O
14	O
is	O
the	O
production	O
version	O
,	O
and	O
is	O
available	O
in	O
PDIP	B-Algorithm
,	O
PLCC	O
and	O
QFP	B-Algorithm
packages	O
.	O
</s>
<s>
The	O
maximum	O
officially	O
supported	O
Ø2	O
(	O
primary	O
)	O
clock	O
speed	O
is	O
14MHz	O
when	O
operated	O
at	O
5	O
volts	O
,	O
indicated	O
by	O
the	O
–	O
14	O
part	O
number	O
suffix	O
(	O
hobbyists	O
have	O
developed	O
65C02	B-General_Concept
homebrew	B-Device
systems	O
that	O
run	O
faster	O
than	O
the	O
official	O
rating	O
)	O
.	O
</s>
<s>
Typical	O
microprocessors	B-Architecture
not	O
implemented	O
in	O
CMOS	B-Device
have	O
dynamic	O
cores	O
and	O
will	O
lose	O
their	O
internal	O
register	B-General_Concept
contents	O
(	O
and	O
thus	O
crash	O
)	O
if	O
they	O
are	O
not	O
continuously	O
clocked	O
at	O
a	O
rate	O
between	O
some	O
minimum	O
and	O
maximum	O
specified	O
values	O
.	O
</s>
<s>
8-bit	O
processor	B-General_Concept
registers	I-General_Concept
:	O
</s>
<s>
The	O
W65C02S	B-General_Concept
may	O
be	O
operated	O
at	O
any	O
convenient	O
supply	O
voltage	O
(	O
VDD	O
)	O
between	O
1.8	O
and	O
5	O
volts	O
( ±5%	O
)	O
.	O
</s>
<s>
The	O
W65C02S	B-General_Concept
support	O
for	O
arbitrary	O
clock	O
rates	O
allows	O
it	O
to	O
use	O
a	O
clock	O
that	O
runs	O
at	O
a	O
rate	O
ideal	O
for	O
some	O
other	O
part	O
of	O
the	O
system	O
,	O
such	O
as	O
13.5MHz	O
(	O
digital	O
SDTV	O
luma	O
sampling	O
rate	O
)	O
,	O
14.31818MHz	O
(	O
NTSC	O
colour	O
carrier	O
frequency	O
×	O
4	O
)	O
,	O
14.75MHz	O
(	O
PAL	O
square	O
pixels	O
)	O
,	O
14.7456	O
(	O
baud	O
rate	O
crystal	O
)	O
,	O
etc.	O
,	O
as	O
long	O
as	O
VDD	O
is	O
sufficient	O
to	O
support	O
the	O
frequency	O
.	O
</s>
<s>
Designer	O
Bill	O
Mensch	O
has	O
pointed	O
out	O
that	O
FMAX	O
is	O
affected	O
by	O
off-chip	O
factors	O
,	O
such	O
as	O
the	O
capacitive	O
load	O
on	O
the	O
microprocessor	B-Architecture
's	O
pins	O
.	O
</s>
<s>
The	O
PLCC	O
and	O
QFP	B-Algorithm
packages	O
have	O
less	O
pin-to-pin	O
capacitance	O
than	O
the	O
PDIP	B-Algorithm
package	O
,	O
and	O
are	O
more	O
economical	O
in	O
the	O
use	O
of	O
printed	O
circuit	O
board	O
space	O
.	O
</s>
<s>
WDC	O
has	O
reported	O
that	O
FPGA	B-Architecture
realizations	O
of	O
the	O
W65C02S	B-General_Concept
have	O
been	O
successfully	O
operated	O
at	O
200MHz	O
.	O
</s>
<s>
Although	O
the	O
65C02	B-General_Concept
can	O
mostly	O
be	O
thought	O
of	O
as	O
a	O
low-power	O
6502	B-General_Concept
,	O
it	O
also	O
fixes	O
several	O
bugs	O
found	O
in	O
the	O
original	O
and	O
adds	O
new	O
instructions	O
,	O
addressing	B-Language
modes	I-Language
and	O
features	O
that	O
can	O
assist	O
the	O
programmer	O
in	O
writing	O
smaller	O
and	O
faster-executing	O
programs	O
.	O
</s>
<s>
It	O
is	O
estimated	O
that	O
the	O
average	O
6502	B-General_Concept
assembly	O
language	O
program	O
can	O
be	O
made	O
10	O
to	O
15	O
percent	O
smaller	O
on	O
the	O
65C02	B-General_Concept
and	O
see	O
a	O
similar	O
improvement	O
in	O
performance	O
,	O
largely	O
through	O
avoided	O
memory	O
accesses	O
through	O
the	O
use	O
of	O
fewer	O
instructions	O
to	O
accomplish	O
a	O
given	O
task	O
.	O
</s>
<s>
The	O
original	O
6502	B-General_Concept
has	O
56	O
instructions	O
,	O
which	O
,	O
when	O
combined	O
with	O
different	O
addressing	B-Language
modes	I-Language
,	O
produce	O
a	O
total	O
of	O
151	O
opcodes	B-Language
of	O
the	O
possible	O
256	O
8-bit	O
opcode	B-Language
patterns	O
.	O
</s>
<s>
The	O
remaining	O
105	O
unused	O
opcodes	B-Language
are	O
undefined	O
,	O
with	O
the	O
set	O
of	O
codes	O
with	O
low-order	O
4-bits	O
with	O
3	O
,	O
7	O
,	O
B	O
or	O
F	O
left	O
entirely	O
unused	O
,	O
the	O
code	O
with	O
low-order	O
2	O
having	O
only	O
a	O
single	O
opcode	B-Language
.	O
</s>
<s>
On	O
the	O
6502	B-General_Concept
,	O
some	O
of	O
these	O
leftover	O
codes	O
actually	O
perform	O
computation	O
.	O
</s>
<s>
Due	O
to	O
the	O
way	O
the	O
6502	B-General_Concept
's	O
instruction	B-General_Concept
decoder	O
works	O
,	O
simply	O
setting	O
certain	O
bits	O
in	O
the	O
opcode	B-Language
cause	O
parts	O
of	O
the	O
instruction	B-General_Concept
processing	O
to	O
take	O
place	O
.	O
</s>
<s>
Some	O
of	O
these	O
opcodes	B-Language
immediately	O
crash	O
the	O
processor	O
,	O
while	O
other	O
perform	O
useful	O
functions	O
and	O
were	O
even	O
given	O
unofficial	O
assembler	O
mnemonics	O
by	O
some	O
programmers	O
.	O
</s>
<s>
The	O
65C02	B-General_Concept
adds	O
new	O
opcodes	B-Language
that	O
use	O
some	O
of	O
these	O
previously	O
undocumented	O
instruction	B-General_Concept
slots	O
.	O
</s>
<s>
For	O
example	O
,	O
$FF	O
is	O
used	O
for	O
the	O
new	O
BBS	O
instruction	B-General_Concept
.	O
</s>
<s>
Those	O
which	O
remain	O
truly	O
unused	O
are	O
equivalent	O
to	O
NOPs	B-Language
.	O
</s>
<s>
6502	B-General_Concept
programs	O
using	O
those	O
opcodes	B-Language
will	O
not	O
work	O
on	O
the	O
65C02	B-General_Concept
.	O
</s>
<s>
The	O
original	O
6502	B-General_Concept
had	O
several	O
errata	O
when	O
initially	O
launched	O
.	O
</s>
<s>
Early	O
versions	O
of	O
the	O
processor	O
had	O
a	O
defective	O
ROR	O
(	O
rotate	O
right	O
)	O
instruction	B-General_Concept
,	O
which	O
MOS	O
Technology	O
addressed	O
by	O
not	O
documenting	O
the	O
instruction	B-General_Concept
.	O
</s>
<s>
A	O
bug	O
that	O
is	O
present	O
in	O
all	O
NMOS	B-Algorithm
variants	O
of	O
the	O
6502	B-General_Concept
involves	O
the	O
jump	O
instruction	B-General_Concept
when	O
using	O
indirect	B-Language
addressing	I-Language
.	O
</s>
<s>
In	O
this	O
addressing	B-Language
mode	I-Language
,	O
the	O
target	O
address	O
of	O
the	O
JMP	O
instruction	B-General_Concept
is	O
fetched	O
from	O
memory	O
,	O
the	O
jump	O
vector	O
,	O
rather	O
than	O
being	O
an	O
operand	O
to	O
the	O
JMP	O
instruction	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
JMP	O
( $1234	O
)	O
would	O
fetch	O
the	O
value	O
in	O
memory	O
locations	O
(	O
least	O
significant	O
byte	O
)	O
and	O
(	O
most	O
significant	O
byte	O
)	O
and	O
load	O
those	O
values	O
into	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
which	O
would	O
then	O
cause	O
the	O
processor	O
to	O
continue	O
execution	O
at	O
the	O
address	O
stored	O
in	O
the	O
vector	O
.	O
</s>
<s>
The	O
bug	O
appears	O
when	O
the	O
vector	O
address	O
ends	O
in	O
,	O
which	O
is	O
the	O
boundary	O
of	O
a	O
memory	B-General_Concept
page	I-General_Concept
.	O
</s>
<s>
The	O
65C02	B-General_Concept
corrected	O
this	O
issue	O
.	O
</s>
<s>
More	O
of	O
an	O
oversight	O
than	O
a	O
bug	O
,	O
the	O
state	O
of	O
the	O
(	O
D	O
)	O
ecimal	O
flag	O
in	O
the	O
NMOS	B-Algorithm
6502	B-General_Concept
's	O
status	B-General_Concept
register	I-General_Concept
is	O
undefined	O
after	O
a	O
reset	B-General_Concept
or	O
interrupt	B-Application
.	O
</s>
<s>
As	O
a	O
result	O
,	O
one	O
finds	O
a	O
CLD	O
instruction	B-General_Concept
(	O
CLear	O
Decimal	O
)	O
in	O
almost	O
all	O
6502	B-General_Concept
interrupt	B-General_Concept
handlers	I-General_Concept
,	O
as	O
well	O
as	O
early	O
in	O
the	O
reset	B-General_Concept
code	O
.	O
</s>
<s>
The	O
65C02	B-General_Concept
automatically	O
clears	O
this	O
flag	O
after	O
pushing	O
the	O
status	B-General_Concept
register	I-General_Concept
onto	O
the	O
stack	B-Application
in	O
response	O
any	O
interrupt	B-Application
or	O
in	O
response	O
to	O
a	O
hardware	O
reset	B-General_Concept
,	O
thus	O
placing	O
the	O
processor	O
back	O
into	O
binary	O
arithmetic	O
mode	O
.	O
</s>
<s>
During	O
decimal	O
mode	O
arithmetic	O
,	O
the	O
NMOS	B-Algorithm
6502	B-General_Concept
will	O
update	O
the	O
(	O
N	B-Algorithm
)	O
egative	O
,	O
o(V )	O
erflow	O
and	O
(	O
Z	B-Algorithm
)	O
ero	O
flags	O
to	O
reflect	O
the	O
result	O
of	O
underlying	O
binary	O
arithmetic	O
,	O
that	O
is	O
,	O
the	O
flags	O
are	O
reflecting	O
a	O
result	O
computed	O
prior	O
to	O
the	O
processor	O
performing	O
decimal	O
correction	O
.	O
</s>
<s>
In	O
contrast	O
,	O
the	O
65C02	B-General_Concept
sets	O
these	O
flags	O
according	O
to	O
the	O
result	O
of	O
decimal	O
arithmetic	O
,	O
at	O
the	O
cost	O
of	O
an	O
extra	O
clock	O
cycle	O
per	O
arithmetic	O
instruction	B-General_Concept
.	O
</s>
<s>
When	O
executing	O
a	O
read-modify-write	B-Operating_System
(	O
R-M-W	O
)	O
instruction	B-General_Concept
,	O
such	O
as	O
INC	O
addr	O
,	O
all	O
NMOS	B-Algorithm
variants	O
will	O
do	O
a	O
double	O
write	O
on	O
addr	O
,	O
first	O
rewriting	O
the	O
current	O
value	O
found	O
at	O
addr	O
and	O
then	O
writing	O
the	O
modified	O
value	O
.	O
</s>
<s>
This	O
behavior	O
can	O
result	O
in	O
difficult-to-resolve	O
bugs	O
if	O
addr	O
is	O
a	O
hardware	O
register	B-General_Concept
.	O
</s>
<s>
This	O
may	O
occur	O
if	O
the	O
hardware	O
is	O
watching	O
for	O
changes	O
to	O
the	O
value	O
in	O
the	O
register	B-General_Concept
and	O
then	O
performs	O
an	O
action	O
,	O
in	O
this	O
case	O
,	O
it	O
will	O
perform	O
two	O
actions	O
,	O
one	O
with	O
the	O
original	O
value	O
and	O
then	O
again	O
with	O
the	O
new	O
value	O
.	O
</s>
<s>
The	O
65C02	B-General_Concept
instead	O
performs	O
a	O
double	O
read	O
of	O
addr	O
,	O
followed	O
by	O
a	O
single	O
write	O
.	O
</s>
<s>
When	O
performing	O
indexed	B-Language
addressing	I-Language
,	O
if	O
indexing	O
crosses	O
a	O
page	O
boundary	O
all	O
NMOS	B-Algorithm
variants	O
will	O
read	O
from	O
an	O
invalid	O
address	O
before	O
accessing	O
the	O
correct	O
address	O
.	O
</s>
<s>
As	O
with	O
a	O
R-M-W	O
instruction	B-General_Concept
,	O
this	O
behavior	O
can	O
cause	O
problems	O
when	O
accessing	O
hardware	O
registers	O
via	O
indexing	O
.	O
</s>
<s>
The	O
65C02	B-General_Concept
fixed	O
this	O
problem	O
by	O
performing	O
a	O
dummy	O
read	O
of	O
the	O
instruction	B-Language
opcode	I-Language
when	O
indexing	O
crosses	O
a	O
page	O
boundary	O
.	O
</s>
<s>
Again	O
,	O
if	O
indexing	O
on	O
hardware	O
register	B-General_Concept
addresses	O
,	O
this	O
bug	O
can	O
result	O
in	O
undefined	O
behavior	O
.	O
</s>
<s>
If	O
an	O
NMOS	B-Algorithm
6502	B-General_Concept
is	O
fetching	O
a	O
BRK	B-General_Concept
(	O
software	O
interrupt	B-Application
)	O
opcode	B-Language
at	O
the	O
same	O
time	O
a	O
hardware	O
interrupt	B-Application
occurs	O
,	O
the	O
BRK	B-General_Concept
will	O
be	O
ignored	O
as	O
the	O
processor	O
reacts	O
to	O
the	O
hardware	O
interrupt	B-Application
.	O
</s>
<s>
The	O
65C02	B-General_Concept
correctly	O
handles	O
this	O
situation	O
by	O
servicing	O
the	O
interrupt	B-Application
and	O
then	O
executing	O
BRK	B-General_Concept
.	O
</s>
<s>
The	O
6502	B-General_Concept
has	O
two	O
indirect	B-Language
addressing	I-Language
modes	O
which	O
dereference	O
through	O
16-bit	B-Device
addresses	O
stored	O
in	O
page	B-General_Concept
zero	I-General_Concept
:	O
</s>
<s>
LDA	O
( $10	O
,	O
X	O
)	O
,	O
adds	O
the	O
X	O
register	B-General_Concept
to	O
the	O
given	O
page	B-General_Concept
zero	I-General_Concept
address	O
before	O
reading	O
the	O
16-bit	B-Device
vector	O
.	O
</s>
<s>
In	O
this	O
example	O
,	O
if	O
X	O
is	O
5	O
,	O
it	O
reads	O
the	O
16-bit	B-Device
address	O
from	O
location	O
$	O
15/	O
$16	O
.	O
</s>
<s>
This	O
is	O
useful	O
when	O
there	O
is	O
an	O
array	O
of	O
pointers	O
in	O
page	B-General_Concept
zero	I-General_Concept
.	O
</s>
<s>
Indirect	O
indexed	O
LDA	O
( $10	O
)	O
,	O
Y	O
adds	O
the	O
Y	O
register	B-General_Concept
to	O
the	O
16-bit	B-Device
vector	O
read	O
from	O
the	O
given	O
page	B-General_Concept
zero	I-General_Concept
address	O
.	O
</s>
<s>
A	O
downside	O
of	O
this	O
model	O
is	O
that	O
if	O
indexing	O
is	O
not	O
needed	O
but	O
the	O
address	O
is	O
in	O
the	O
zero	B-General_Concept
page	I-General_Concept
,	O
one	O
of	O
the	O
index	B-General_Concept
registers	I-General_Concept
must	O
still	O
be	O
set	O
to	O
zero	O
and	O
used	O
in	O
one	O
of	O
these	O
instructions	O
.	O
</s>
<s>
The	O
65C02	B-General_Concept
added	O
a	O
non-indexed	O
indirect	B-Language
addressing	I-Language
mode	O
LDA	O
( $10	O
)	O
to	O
all	O
instructions	O
that	O
used	O
indexed	O
indirect	O
and	O
indirect	O
indexed	O
modes	O
,	O
freeing	O
up	O
the	O
index	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
The	O
6502	B-General_Concept
's	O
instruction	B-General_Concept
had	O
a	O
unique	O
(	O
among	O
6502	B-General_Concept
instructions	O
)	O
addressing	B-Language
mode	I-Language
known	O
as	O
"	O
absolute	O
indirect	O
"	O
that	O
read	O
a	O
16-bit	B-Device
value	O
from	O
a	O
given	O
memory	O
address	O
and	O
then	O
jumped	O
to	O
the	O
address	O
in	O
that	O
16-bit	B-Device
value	O
.	O
</s>
<s>
One	O
common	O
use	O
for	O
indirect	B-Language
addressing	I-Language
is	O
to	O
build	O
branch	O
tables	O
,	O
a	O
list	O
of	O
entry	O
points	O
for	O
subroutines	O
that	O
can	O
be	O
accessed	O
using	O
an	O
index	O
.	O
</s>
<s>
For	O
instance	O
,	O
a	O
device	B-Application
driver	I-Application
might	O
list	O
the	O
entry	O
points	O
for	O
,	O
,	O
,	O
etc	O
in	O
a	O
table	O
at	O
.	O
</s>
<s>
is	O
the	O
third	O
entry	O
,	O
zero	O
indexed	O
,	O
and	O
each	O
address	O
requires	O
16-bits	B-Device
,	O
so	O
to	O
call	O
one	O
would	O
use	O
something	O
similar	O
to	O
JMP	O
( $A004	O
)	O
.	O
</s>
<s>
The	O
65C02	B-General_Concept
added	O
the	O
new	O
"	O
indexed	O
absolute	O
indirect	O
"	O
mode	O
which	O
eased	O
the	O
use	O
of	O
branch	O
tables	O
.	O
</s>
<s>
This	O
mode	O
added	O
the	O
value	O
of	O
the	O
X	O
register	B-General_Concept
to	O
the	O
absolute	O
address	O
and	O
took	O
the	O
16-bit	B-Device
address	O
from	O
the	O
resulting	O
location	O
.	O
</s>
<s>
The	O
same	O
could	O
be	O
achieved	O
in	O
the	O
NMOS	B-Algorithm
version	O
using	O
indexed	O
indirect	O
mode	O
,	O
but	O
only	O
if	O
the	O
table	O
was	O
in	O
the	O
zero	B-General_Concept
page	I-General_Concept
,	O
a	O
limited	O
resource	O
.	O
</s>
<s>
Allowing	O
these	O
to	O
be	O
constructed	O
outside	O
zero	B-General_Concept
page	I-General_Concept
not	O
only	O
lessened	O
the	O
demand	O
for	O
this	O
resource	O
,	O
but	O
also	O
allowed	O
the	O
tables	O
to	O
be	O
constructed	O
in	O
ROM	O
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
new	O
addressing	B-Language
modes	I-Language
,	O
the	O
"	O
base	O
model	O
"	O
65C02	B-General_Concept
also	O
added	O
a	O
set	O
of	O
new	O
instructions	O
.	O
</s>
<s>
INC	O
and	O
DEC	O
with	O
no	O
parameters	O
now	O
increment	O
or	O
decrement	O
the	O
accumulator	B-General_Concept
.	O
</s>
<s>
This	O
was	O
an	O
odd	O
oversight	O
in	O
the	O
original	O
instruction	B-General_Concept
set	I-General_Concept
,	O
which	O
only	O
included	O
INX/DEX	O
,	O
INY/DEY	O
and	O
INC	O
addr/DEC	O
addr	O
.	O
</s>
<s>
Replaces	O
the	O
need	O
to	O
LDA	O
#0	O
;	O
STA	O
addr	O
and	O
does	O
n't	O
require	O
changing	O
the	O
value	O
of	O
the	O
accumulator	B-General_Concept
.	O
</s>
<s>
As	O
this	O
task	O
is	O
common	O
in	O
most	O
programs	O
,	O
using	O
STZ	O
can	O
reduce	O
code	O
size	O
,	O
both	O
by	O
eliminating	O
the	O
LDA	O
as	O
well	O
as	O
any	O
code	O
needed	O
to	O
save	O
the	O
value	O
of	O
the	O
accumulator	B-General_Concept
,	O
typically	O
a	O
PHA	O
PLA	O
pair	O
.	O
</s>
<s>
PHX	O
,	O
PLX	O
,	O
PHY	O
,	O
PLY	O
,	O
push	O
and	O
pull	O
the	O
X	O
and	O
Y	O
registers	O
to/from	O
the	O
stack	B-Application
.	O
</s>
<s>
Previously	O
,	O
only	O
the	O
accumulator	B-General_Concept
and	O
status	B-General_Concept
register	I-General_Concept
had	O
push	O
and	O
pull	O
instructions	O
.	O
</s>
<s>
X	O
and	O
Y	O
could	O
only	O
be	O
stacked	O
by	O
moving	O
them	O
to	O
the	O
accumulator	B-General_Concept
first	O
with	O
TXA	O
or	O
TYA	O
,	O
thereby	O
changing	O
the	O
accumulator	B-General_Concept
contents	O
,	O
then	O
using	O
PHA	O
.	O
</s>
<s>
As	O
the	O
address	O
is	O
relative	O
,	O
it	O
is	O
also	O
useful	O
when	O
writing	O
relocatable	O
code	O
,	O
a	O
common	O
task	O
in	O
the	O
era	O
before	O
memory	B-General_Concept
management	I-General_Concept
units	I-General_Concept
.	O
</s>
<s>
Both	O
WDC	O
and	O
Rockwell	O
contributed	O
improvements	O
to	O
the	O
bit	O
testing	O
and	O
manipulation	O
functions	O
in	O
the	O
65C02	B-General_Concept
.	O
</s>
<s>
WDC	O
added	O
new	O
addressing	B-Language
modes	I-Language
to	O
the	O
BIT	O
instruction	B-General_Concept
that	O
was	O
present	O
in	O
the	O
6502	B-General_Concept
,	O
as	O
well	O
two	O
new	O
instructions	O
for	O
convenient	O
manipulation	O
of	O
bit	O
fields	O
,	O
a	O
common	O
activity	O
in	O
device	B-Application
drivers	I-Application
.	O
</s>
<s>
BIT	O
in	O
the	O
65C02	B-General_Concept
adds	O
immediate	O
mode	O
,	O
zero	B-General_Concept
page	I-General_Concept
indexed	O
by	O
X	O
and	O
absolute	O
indexed	O
by	O
X	O
addressing	O
.	O
</s>
<s>
The	O
operation	O
changes	O
the	O
value	O
in	O
the	O
accumulator	B-General_Concept
,	O
so	O
the	O
original	O
value	O
loaded	O
from	O
$1234	O
is	O
lost	O
.	O
</s>
<s>
Using	O
leaves	O
the	O
value	O
in	O
the	O
accumulator	B-General_Concept
unchanged	O
,	O
so	O
subsequent	O
code	O
can	O
make	O
additional	O
tests	O
against	O
the	O
original	O
value	O
,	O
avoiding	O
having	O
to	O
re-load	O
the	O
value	O
from	O
memory	O
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
enhancements	O
of	O
the	O
BIT	O
instruction	B-General_Concept
,	O
WDC	O
added	O
two	O
instructions	O
designed	O
to	O
conveniently	O
manipulate	O
bit	O
fields	O
:	O
</s>
<s>
TSB	O
addr	O
and	O
TRB	O
addr	O
,	O
Test	O
and	O
Set	O
Bits	O
and	O
Test	O
and	O
Reset	B-General_Concept
Bits	O
.	O
</s>
<s>
A	O
mask	O
in	O
the	O
accumulator	B-General_Concept
(	O
.A	O
)	O
is	O
logically	O
ANDed	O
with	O
memory	O
at	O
addr	O
,	O
which	O
location	O
may	O
be	O
zero	B-General_Concept
page	I-General_Concept
or	O
absolute	O
.	O
</s>
<s>
The	O
Z	B-Algorithm
flag	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
is	O
conditioned	O
according	O
to	O
the	O
result	O
of	O
the	O
logical	O
AND	O
—	O
no	O
other	O
status	B-General_Concept
register	I-General_Concept
flags	O
are	O
affected	O
.	O
</s>
<s>
In	O
both	O
cases	O
,	O
the	O
Z	B-Algorithm
flag	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
indicates	O
the	O
result	O
of	O
.A	O
AND	O
addr	O
before	O
the	O
content	O
of	O
addr	O
is	O
changed	O
.	O
</s>
<s>
TRB	O
and	O
TSB	O
thus	O
replace	O
a	O
sequence	O
of	O
instructions	O
,	O
essentially	O
combining	O
the	O
BIT	O
instruction	B-General_Concept
with	O
additional	O
steps	O
to	O
save	O
the	O
computational	O
changes	O
,	O
but	O
in	O
a	O
way	O
that	O
reports	O
the	O
status	O
of	O
the	O
affected	O
value	O
before	O
it	O
is	O
changed	O
.	O
</s>
<s>
Rockwell	O
's	O
changes	O
added	O
more	O
bit	O
manipulation	O
instructions	O
for	O
directly	O
setting	O
and	O
testing	O
any	O
bit	O
,	O
and	O
combining	O
the	O
test	O
,	O
clear	O
and	O
branch	O
into	O
a	O
single	O
opcode	B-Language
.	O
</s>
<s>
The	O
new	O
instructions	O
were	O
available	O
from	O
the	O
start	O
in	O
Rockwell	O
's	O
R65C00	O
family	O
,	O
but	O
was	O
not	O
part	O
of	O
the	O
original	O
65C02	B-General_Concept
specification	O
and	O
not	O
found	O
in	O
versions	O
made	O
by	O
WDC	O
or	O
its	O
other	O
licensees	O
.	O
</s>
<s>
Set	O
or	O
Reset	B-General_Concept
(	O
clear	O
)	O
bit	O
number	O
bit#	O
in	O
zero	B-General_Concept
page	I-General_Concept
byte	O
zp	O
.	O
</s>
<s>
As	O
RMB	O
and	O
SMB	O
are	O
zero	B-General_Concept
page	I-General_Concept
addressing	O
only	O
,	O
these	O
instructions	O
are	O
limited	O
in	O
usefulness	O
and	O
are	O
primarily	O
of	O
value	O
in	O
systems	O
in	O
which	O
device	O
registers	O
are	O
present	O
in	O
zero	B-General_Concept
page	I-General_Concept
.	O
</s>
<s>
The	O
bit#	O
component	O
of	O
the	O
instruction	B-General_Concept
is	O
often	O
written	O
as	O
part	O
of	O
the	O
mnemonic	O
,	O
such	O
as	O
SMB1	O
$12	O
which	O
sets	O
bit	O
1	O
in	O
zero-page	O
address	O
$12	O
.	O
</s>
<s>
Some	O
assemblers	O
treat	O
bit#	O
as	O
part	O
of	O
the	O
instruction	B-General_Concept
's	O
operand	O
,	O
e.g.	O
,	O
SMB	O
1	O
,	O
$12	O
,	O
which	O
has	O
the	O
advantage	O
of	O
allowing	O
it	O
to	O
be	O
replaced	O
by	O
a	O
variable	O
name	O
or	O
calculated	O
number	O
.	O
</s>
<s>
BBR	O
bit#	O
,	O
offset	O
,	O
addr	O
and	O
BBS	O
bit#	O
,	O
offset	O
,	O
addr	O
,	O
Branch	O
on	O
Bit	O
Set/Reset	O
.	O
</s>
<s>
,	O
STop	O
the	O
Processor	O
,	O
halted	O
all	O
processing	O
until	O
a	O
hardware	O
reset	B-General_Concept
was	O
issued	O
.	O
</s>
<s>
This	O
could	O
be	O
used	O
to	O
put	O
a	O
system	O
to	O
"	O
sleep	O
"	O
and	O
then	O
rapidly	O
wake	O
it	O
with	O
a	O
reset	B-General_Concept
.	O
</s>
<s>
t	O
had	O
a	O
similar	O
effect	O
,	O
entering	O
low-power	O
mode	O
,	O
but	O
this	O
instruction	B-General_Concept
woke	O
the	O
processor	O
up	O
again	O
on	O
the	O
reception	O
of	O
an	O
interrupt	B-Application
.	O
</s>
<s>
Previously	O
,	O
handling	O
an	O
interrupt	B-Application
generally	O
involved	O
running	O
a	O
loop	O
to	O
check	O
if	O
an	O
interrupt	B-Application
has	O
been	O
received	O
,	O
sometimes	O
known	O
as	O
"	O
spinning	B-Operating_System
"	O
,	O
checking	O
the	O
type	O
when	O
one	O
is	O
received	O
,	O
and	O
then	O
jumping	O
to	O
the	O
processing	O
code	O
.	O
</s>
<s>
This	O
meant	O
the	O
processor	O
was	O
running	O
during	O
the	O
entire	O
process	O
,	O
even	O
when	O
no	O
interrupts	B-Application
were	O
occurring	O
.	O
</s>
<s>
In	O
contrast	O
,	O
in	O
the	O
65C02	B-General_Concept
,	O
interrupt	B-Application
code	O
could	O
be	O
written	O
by	O
having	O
a	O
followed	O
immediately	O
by	O
a	O
or	O
to	O
the	O
handler	O
.	O
</s>
<s>
When	O
the	O
interrupt	B-Application
was	O
received	O
,	O
it	O
immediately	O
processed	O
the	O
and	O
handled	O
the	O
request	O
.	O
</s>
<s>
In	O
the	O
spinning	B-Operating_System
case	O
,	O
the	O
interrupt	B-Application
might	O
arrive	O
in	O
the	O
middle	O
of	O
one	O
of	O
the	O
loop	O
's	O
instructions	O
,	O
and	O
to	O
allow	O
it	O
to	O
restart	O
after	O
returning	O
from	O
the	O
handler	O
,	O
the	O
processor	O
spends	O
one	O
cycle	O
to	O
save	O
its	O
location	O
.	O
</s>
<s>
With	O
,	O
the	O
processor	O
enters	O
the	O
low-power	O
state	O
in	O
a	O
known	O
location	O
where	O
all	O
instructions	O
are	O
guaranteed	O
to	O
be	O
complete	O
,	O
so	O
when	O
the	O
interrupt	B-Application
arrives	O
it	O
cannot	O
possibly	O
interrupt	B-Application
an	O
instruction	B-General_Concept
and	O
the	O
processor	O
can	O
safely	O
continue	O
without	O
spending	O
a	O
cycle	O
saving	O
state	O
.	O
</s>
<s>
The	O
65SC02	O
is	O
a	O
variant	O
of	O
the	O
WDC	B-General_Concept
65C02	I-General_Concept
without	O
bit	O
instructions	O
.	O
</s>
<s>
many	O
dedicated	O
chess	B-Application
computers	I-Application
i.e.	O
</s>
