<s>
The	O
Warp	B-Device
machines	O
were	O
a	O
series	O
of	O
increasingly	O
general-purpose	O
systolic	B-Architecture
array	I-Architecture
processors	O
,	O
created	O
by	O
Carnegie	O
Mellon	O
University	O
(	O
CMU	O
)	O
,	O
in	O
conjunction	O
with	O
industrial	O
partners	O
G.E.	O
,	O
Honeywell	O
and	O
Intel	O
,	O
and	O
funded	O
by	O
the	O
U.S.	O
Defense	O
Advanced	O
Research	O
Projects	O
Agency	O
(	O
DARPA	O
)	O
.	O
</s>
<s>
The	O
Warp	B-Device
projects	O
were	O
started	O
in	O
1984	O
by	O
H	O
.	O
T	O
.	O
Kung	O
at	O
Carnegie	O
Mellon	O
University	O
.	O
</s>
<s>
The	O
Warp	B-Device
projects	O
yielded	O
research	O
results	O
,	O
publications	O
and	O
advancements	O
in	O
general	O
purpose	O
systolic	O
hardware	O
design	O
,	O
compiler	O
design	O
and	O
systolic	O
software	O
algorithms	O
.	O
</s>
<s>
There	O
were	O
three	O
distinct	O
machine	O
designs	O
known	O
as	O
the	O
WW-Warp	O
(	O
Wire	O
Wrap	O
Warp	B-Device
)	O
,	O
PC-Warp	O
(	O
Printed	O
Circuit	O
Warp	B-Device
)	O
,	O
and	O
iWarp	B-Device
(	O
integrated	O
circuit	O
Warp	B-Device
,	O
conveniently	O
also	O
a	O
play	O
on	O
the	O
“	O
i	O
”	O
for	O
Intel	O
)	O
.	O
</s>
<s>
Only	O
the	O
original	O
WW-Warp	O
forced	O
a	O
truly	O
lock	O
step	O
sequencing	O
of	O
stages	O
,	O
which	O
severely	O
restricted	O
its	O
programmability	O
but	O
was	O
in	O
a	O
sense	O
the	O
purest	O
“	O
systolic-array	O
”	O
design	O
.	O
</s>
<s>
Warp	B-Device
machines	O
were	O
attached	O
to	O
Sun	O
workstations	O
(	O
UNIX	O
based	O
)	O
.	O
</s>
<s>
Software	O
development	O
for	O
all	O
models	O
of	O
Warp	B-Device
machines	O
was	O
done	O
on	O
Sun	O
workstations	O
.	O
</s>
<s>
A	O
research	O
compiler	O
,	O
for	O
a	O
language	O
known	O
as	O
“	O
W2	O
,	O
”	O
targeted	O
all	O
three	O
machines	O
and	O
was	O
the	O
only	O
compiler	O
for	O
the	O
WW-Warp	O
and	O
PC-Warp	O
while	O
it	O
served	O
as	O
an	O
early	O
compiler	O
during	O
development	O
of	O
the	O
iWarp	B-Device
.	O
</s>
<s>
The	O
production	O
compiler	O
for	O
iWarp	B-Device
was	O
a	O
C	O
and	O
Fortran	O
compiler	O
based	O
on	O
the	O
AT&T	O
pcc	O
compiler	O
for	O
UNIX	O
,	O
ported	O
under	O
contract	O
for	O
Intel	O
and	O
then	O
extensively	O
modified	O
and	O
extend	O
by	O
Intel	O
.	O
</s>
<s>
The	O
WW-Warp	O
and	O
PC-Warp	O
machines	O
were	O
systolic	B-Architecture
array	I-Architecture
computers	O
with	O
a	O
linear	O
array	O
of	O
ten	O
or	O
more	O
cells	O
,	O
each	O
of	O
which	O
is	O
a	O
programmable	O
processor	O
capable	O
of	O
performing	O
10	O
million	O
single	O
precision	O
floating-point	O
operations	O
per	O
second	O
(	O
10	O
MFLOPS	O
)	O
.	O
</s>
<s>
The	O
iWarp	B-Device
machines	O
doubled	O
this	O
performance	O
,	O
delivering	O
20	O
MFLOPS	O
single	O
precision	O
and	O
supporting	O
double	O
precision	O
floating	O
point	O
at	O
half	O
the	O
performance	O
.	O
</s>
<s>
A	O
two	O
cell	O
prototype	O
of	O
WW-Warp	O
was	O
complete	O
at	O
Carnegie	O
Mellon	O
in	O
June	O
1985	O
.	O
</s>
<s>
Two	O
essentially	O
identical	O
ten-cell	O
WW-Warp	O
were	O
produced	O
in	O
1986	O
,	O
one	O
by	O
Honeywell	O
and	O
one	O
by	O
G.E.	O
,	O
for	O
use	O
at	O
Carnegie	O
Mellon	O
University	O
.	O
</s>
<s>
The	O
first	O
of	O
the	O
significantly	O
redesign	O
production	O
model	O
,	O
the	O
PC-Warp	O
,	O
was	O
delivered	O
by	O
G.E.	O
</s>
<s>
About	O
twenty	O
production	O
models	O
of	O
the	O
PC-Warp	O
were	O
produced	O
and	O
sold	O
by	O
G.E.	O
</s>
<s>
The	O
iWarp	B-Device
machines	O
were	O
based	O
on	O
a	O
single-chip	O
custom	O
700,000	O
transistor	O
microprocessor	O
,	O
designed	O
specifically	O
for	O
the	O
Warp	B-Device
project	O
,	O
that	O
utilized	O
long-instruction-word	O
(	O
LIW	O
)	O
format	O
instructions	O
and	O
tightly	O
integrated	O
communications	O
with	O
the	O
computational	O
processor	O
.	O
</s>
<s>
The	O
standard	O
iWarp	B-Device
machines	O
configuration	O
arranged	O
iWarp	B-Device
nodes	O
in	O
a	O
2m	O
x	O
2n	O
torus	O
.	O
</s>
<s>
All	O
iWarp	B-Device
machines	O
included	O
the	O
“	O
backedges	O
”	O
and	O
,	O
therefore	O
,	O
were	O
tori	O
.	O
</s>
<s>
In	O
1986	O
,	O
Intel	O
was	O
selected	O
,	O
as	O
a	O
result	O
of	O
competitive	O
bidding	O
,	O
to	O
be	O
the	O
industrial	O
partner	O
for	O
the	O
integrated	O
circuit	O
implementation	O
of	O
Warp	B-Device
.	O
</s>
<s>
The	O
first	O
iWarp	B-Device
system	O
,	O
a	O
twelve	O
node	O
system	O
,	O
became	O
operational	O
in	O
March	O
1990	O
.	O
</s>
<s>
After	O
a	O
number	O
of	O
stepping	O
of	O
the	O
part	O
,	O
about	O
39	O
machines	O
,	O
consisting	O
of	O
ten	O
or	O
more	O
C-Step	O
iWarp	B-Device
chips	O
running	O
at	O
20MHz	O
,	O
were	O
produced	O
and	O
sold	O
by	O
Intel	O
in	O
1992	O
and	O
1993	O
to	O
universities	O
,	O
government	O
agencies	O
and	O
industrial	O
research	O
laboratories	O
.	O
</s>
