<s>
The	O
Vortex86	B-Device
is	O
a	O
computing	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
based	O
on	O
a	O
core	O
compatible	O
with	O
the	O
x86	B-Operating_System
microprocessor	I-Operating_System
family	O
.	O
</s>
<s>
Vortex86	B-Device
previously	O
belonged	O
to	O
SiS	O
,	O
which	O
got	O
the	O
basic	O
design	O
from	O
Rise	O
Technology	O
.	O
</s>
<s>
Before	O
adopting	O
the	O
Vortex86	B-Device
series	O
,	O
DM&P	O
manufactured	O
the	O
M6117D	O
,	O
an	O
Intel	O
386SX	O
compatible	O
,	O
25	O
–	O
40MHz	O
SoC	O
.	O
</s>
<s>
Vortex86	B-Device
CPUs	O
implement	O
the	O
IA-32	B-Device
architecture	O
but	O
which	O
instructions	O
are	O
implemented	O
varies	O
depending	O
on	O
the	O
model	O
.	O
</s>
<s>
Vortex86SX	B-Device
and	O
the	O
early	O
versions	O
of	O
Vortex86	B-Device
do	O
not	O
have	O
a	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	B-General_Concept
)	O
.	O
</s>
<s>
Any	O
i586	O
code	O
will	O
run	O
on	O
Vortex86DX	B-Device
and	O
later	O
.	O
</s>
<s>
Some	O
Linux	B-Application
kernels	O
(	O
by	O
build-time	O
option	O
)	O
emulate	O
the	O
FPU	B-General_Concept
on	O
any	O
CPU	O
that	O
is	O
missing	O
one	O
,	O
so	O
a	O
program	O
that	O
uses	O
i586-level	O
floating	O
point	O
instructions	O
will	O
work	O
on	O
any	O
Vortex86	B-Device
family	O
CPU	O
under	O
such	O
a	O
kernel	O
,	O
albeit	O
more	O
slowly	O
on	O
a	O
model	O
with	O
no	O
FPU	B-General_Concept
.	O
</s>
<s>
Code	O
intended	O
for	O
i686	O
may	O
fail	O
on	O
some	O
models	O
because	O
they	O
lack	O
a	O
Conditional	B-General_Concept
Move	I-General_Concept
(	O
CMOV	O
)	O
instruction	O
.	O
</s>
<s>
Linux	B-Application
systems	O
intended	O
to	O
run	O
on	O
i686	O
are	O
generally	O
not	O
compatible	O
with	O
these	O
Vortex86	B-Device
models	O
because	O
the	O
GNU	O
C	O
Library	O
,	O
when	O
built	O
for	O
i686	O
,	O
uses	O
a	O
CMOV	O
instruction	O
in	O
its	O
assembly	O
language	O
strcmp	O
function	O
,	O
which	O
its	O
dynamic	O
loader	O
(	O
ld.so	O
)	O
uses	O
.	O
</s>
<s>
Below	O
are	O
the	O
properties	O
of	O
a	O
Vortex86	B-Device
original	O
CPU	O
reported	O
by	O
the	O
Linux	B-Application
kernel	O
tool	O
/proc/cpuinfo	O
.	O
</s>
<s>
Note	O
that	O
this	O
CPU	O
is	O
a	O
later	O
version	O
with	O
an	O
FPU	B-General_Concept
.	O
</s>
<s>
DM&P	O
maintained	O
an	O
embedded	B-Architecture
Linux	B-Application
distribution	O
customized	O
to	O
use	O
the	O
SoCs	B-Architecture
features	O
.	O
</s>
<s>
Other	O
operating	O
systems	O
may	O
work	O
depending	O
on	O
the	O
SoC	O
model	O
,	O
including	O
various	O
RTOS	B-Operating_System
systems	O
such	O
as	O
QNX	B-Operating_System
and	O
VxWorks	B-Operating_System
,	O
Linux	B-Application
distributions	O
,	O
FreeBSD	B-Operating_System
or	O
various	O
versions	O
of	O
Microsoft	B-Application
Windows	I-Application
systems	O
such	O
as	O
Windows	B-Operating_System
Embedded	I-Operating_System
Compact	I-Operating_System
or	O
Windows	B-Operating_System
IoT	I-Operating_System
.	O
</s>
<s>
The	O
ability	O
to	O
identify	O
Vortex86	B-Device
processors	O
was	O
added	O
to	O
Linux	B-Application
5.16	O
,	O
released	O
in	O
January	O
2022	O
.	O
</s>
<s>
The	O
Vortex86	B-Device
(	O
M6127D	O
)	O
is	O
a	O
rebadged	O
SiS	O
551	O
system-on-chip	B-Architecture
(	O
SoC	O
)	O
.	O
</s>
<s>
The	O
CPU	O
core	O
is	O
derived	O
from	O
the	O
Rise	O
mP6	B-General_Concept
,	O
which	O
has	O
three	O
integer	O
and	O
MMX	B-Architecture
pipelines	B-General_Concept
and	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
Introduced	O
in	O
February	O
2007	O
,	O
the	O
Vortex86SX	B-Device
is	O
an	O
x86-compatible	O
System-on-chip	B-Architecture
(	O
SoC	O
)	O
with	O
built-in	O
north	O
and	O
south	O
bridge	O
on	O
a	O
0.13micron	O
process	O
in	O
a	O
27x27mm	O
581-ball	O
BGA	O
package	O
.	O
</s>
<s>
It	O
has	O
a	O
six-stage	O
pipeline	B-General_Concept
with	O
a	O
direct-mapped	O
write-through	O
16KB	O
Data	O
+	O
16KB	O
Instruction	O
L1	O
cache	B-General_Concept
but	O
,	O
unlike	O
the	O
Vortex86	B-Device
,	O
lacks	O
L2	O
cache	B-General_Concept
and	O
an	O
FPU	B-General_Concept
.	O
</s>
<s>
Unlike	O
the	O
original	O
Vortex86	B-Device
,	O
it	O
does	O
not	O
integrate	O
video	O
or	O
audio	O
controllers	O
.	O
</s>
<s>
Introduced	O
in	O
August	O
2008	O
,	O
the	O
Vortex86DX	B-Device
retains	O
the	O
same	O
BGA	O
package	O
as	O
the	O
SX	O
and	O
is	O
pin-compatible	O
.	O
</s>
<s>
The	O
CPU	O
core	O
is	O
clocked	O
at	O
600MHz	O
to	O
1GHz	O
(	O
2.02W	O
@	O
800MHz	O
)	O
and	O
improves	O
on	O
the	O
SX	O
with	O
a	O
4-way	O
16KB	O
Data	O
+	O
16	O
KBInstruction	O
L1	O
cache	B-General_Concept
,	O
adds	O
a	O
4-way	O
256KB	O
L2	O
cache	B-General_Concept
,	O
in	O
write-through	O
or	O
write-back	O
mode	O
,	O
and	O
an	O
FPU	B-General_Concept
.	O
</s>
<s>
The	O
SoC	O
adds	O
the	O
ability	O
to	O
function	O
as	O
a	O
USB	O
1.1	O
client	O
on	O
1	O
port	O
and	O
increases	O
the	O
embedded	B-Architecture
flash	O
capacity	O
to	O
2MB	O
.	O
</s>
<s>
The	O
PDX-600	B-Device
is	O
a	O
version	O
of	O
the	O
Vortex86DX	B-Device
that	O
differs	O
only	O
in	O
the	O
number	O
of	O
RS-232	O
ports	O
(	O
three	O
instead	O
of	O
five	O
)	O
and	O
has	O
no	O
I²C	O
and	O
servo	O
controllers	O
,	O
thus	O
targeting	O
more	O
the	O
embedded	B-Architecture
than	O
the	O
industrial	O
market	O
.	O
</s>
<s>
Netbooks	B-Device
similar	O
to	O
the	O
Belco	O
450R	O
use	O
this	O
chip	O
.	O
</s>
<s>
The	O
Vortex86MX	B-Device
uses	O
a	O
larger	O
31x31mm	O
720-ball	O
BGA	O
package	O
,	O
still	O
on	O
a	O
90nm	O
process	O
.	O
</s>
<s>
The	O
CPU	O
core	O
improves	O
on	O
the	O
DX	O
by	O
adding	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
cache-access	O
optimisation	O
and	O
MMX	B-Architecture
instructions	O
.	O
</s>
<s>
The	O
consumer	O
grade	O
version	O
is	O
known	O
as	O
the	O
PMX-1000	B-Device
.	O
</s>
<s>
Current	O
models	O
of	O
the	O
Gecko	O
Edubook	O
use	O
the	O
Xcore86	B-Device
,	O
a	O
rebadge	O
of	O
the	O
Vortex86MX	B-Device
.	O
</s>
<s>
Introduced	O
in	O
June	O
2010	O
,	O
the	O
Vortex86MX+	B-Device
retains	O
the	O
same	O
BGA	O
package	O
and	O
CPU	O
core	O
as	O
the	O
MX	O
.	O
</s>
<s>
Vortex86EX	B-Device
has	O
a	O
32KB	O
write	O
through	O
2-way	O
L1	O
cache	B-General_Concept
,	O
128KB	O
write	O
through/write	O
back	O
2-way	O
L2	O
cache	B-General_Concept
,	O
PCI-e	O
bus	O
interface	O
,	O
300MHz	O
DDR3	O
,	O
ROM	O
controller	O
,	O
IPC	O
(	O
Internal	O
Peripheral	O
Controllers	O
with	O
DMA	O
and	O
interrupt	O
timer/counter	O
included	O
)	O
,	O
Fast	O
Ethernet	O
,	O
FIFO	O
UART	O
,	O
USB2.0	O
Host	O
and	O
ATA	O
controller	O
.	O
</s>
<s>
Vortex86DX3	B-Device
has	O
a	O
1.0GHz	O
dual-core	O
i686-compatible	O
CPU	O
.	O
</s>
<s>
It	O
has	O
an	O
eight-way	O
32K	O
I-Cache	O
,	O
an	O
eight-way	O
32K	O
D-Cache	O
,	O
a	O
four-way	O
512KB	O
L2	O
cache	B-General_Concept
with	O
a	O
write-through	O
or	O
write-back	O
policy	O
,	O
ability	O
to	O
use	O
up	O
to	O
2GB	O
of	O
DDR3	O
RAM	O
,	O
a	O
PCI-e	O
bus	O
interface	O
,	O
100	O
Mbit/s	O
Ethernet	O
,	O
FIFO	O
UART	O
,	O
a	O
USB	O
2.0	O
host	O
,	O
integrated	O
GPU	O
,	O
an	O
ATA	O
controller	O
at	O
Primary	O
Channel	O
,	O
and	O
a	O
SATA	O
1.5Gbit/s	O
controller	O
(	O
one	O
port	O
)	O
at	O
Secondary	O
Channel	O
.	O
</s>
<s>
Vortex86EX2	B-Device
has	O
two	O
asymmetrical	O
master/slave	O
CPU	O
cores	O
.	O
</s>
<s>
The	O
master	O
core	O
runs	O
at	O
600MHz	O
,	O
has	O
16K	O
I-Cache	O
,	O
16K	O
D-Cache	O
,	O
and	O
four-way	O
128KB	O
L2	O
cache	B-General_Concept
with	O
a	O
write-through	O
or	O
write-back	O
policy	O
.	O
</s>
<s>
The	O
slave	O
core	O
operates	O
at	O
400MHz	O
and	O
also	O
has	O
16KB	O
I-Cache	O
,	O
16KB	O
D-Cache	O
,	O
but	O
has	O
no	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
Both	O
have	O
a	O
built-in	O
FPU	B-General_Concept
.	O
</s>
<s>
It	O
can	O
also	O
use	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
