<s>
Virtex	B-General_Concept
is	O
the	O
flagship	O
family	O
of	O
FPGA	B-Architecture
products	O
developed	O
by	O
Xilinx	O
,	O
a	O
part	O
of	O
AMD	O
.	O
</s>
<s>
Virtex	B-General_Concept
FPGAs	B-Architecture
are	O
typically	O
programmed	O
in	O
hardware	O
description	O
languages	O
such	O
as	O
VHDL	B-Language
or	O
Verilog	B-Language
,	O
using	O
the	O
Xilinx	B-Algorithm
ISE	I-Algorithm
or	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
computer	O
software	O
.	O
</s>
<s>
Xilinx	O
FPGA	B-Architecture
products	O
have	O
been	O
recognized	O
by	O
EE	O
Times	O
,	O
EDN	O
and	O
others	O
for	O
innovation	O
and	O
market	O
impact	O
.	O
</s>
<s>
The	O
Virtex	B-General_Concept
series	O
of	O
FPGAs	B-Architecture
are	O
based	O
on	O
Configurable	O
Logic	O
Blocks	O
(	O
CLBs	O
)	O
,	O
where	O
each	O
CLB	O
is	O
equivalent	O
to	O
multiple	O
ASIC	O
gates	O
.	O
</s>
<s>
Each	O
CLB	O
is	O
composed	O
of	O
multiple	O
slices	O
,	O
that	O
differ	O
in	O
construction	O
between	O
Virtex	B-General_Concept
families	O
.	O
</s>
<s>
Virtex	B-General_Concept
FPGAs	B-Architecture
include	O
an	O
I/O	O
Block	O
for	O
controlling	O
input/output	O
pins	O
on	O
the	O
Virtex	B-General_Concept
chip	O
,	O
that	O
support	O
a	O
variety	O
of	O
signalling	O
standards	O
.	O
</s>
<s>
In	O
addition	O
to	O
configurable	O
FPGA	B-Architecture
logic	O
,	O
Virtex	B-General_Concept
FPGAs	B-Architecture
include	O
fixed-function	O
hardware	O
for	O
multipliers	O
,	O
memories	O
,	O
microprocessor	O
cores	O
,	O
FIFO	O
and	O
ECC	O
logic	O
,	O
DSP	O
blocks	O
,	O
PCI	O
Express	O
controllers	O
,	O
Ethernet	B-Protocol
MAC	I-Protocol
blocks	O
,	O
and	O
high-speed	O
serial	O
transceivers	O
.	O
</s>
<s>
Some	O
Virtex	B-General_Concept
family	O
members	O
(	O
such	O
as	O
the	O
Virtex-5QX	O
)	O
are	O
available	O
in	O
radiation-hardened	O
packages	O
,	O
for	O
outer-space	O
applications	O
.	O
</s>
<s>
The	O
Virtex-E	O
family	O
was	O
introduced	O
in	O
September	O
1999	O
on	O
a	O
180nm	O
process	O
technology	O
.	O
</s>
<s>
Virtex-E	O
includes	O
a	O
two	O
million	O
system	O
gate	O
device	O
and	O
supports	O
twice	O
the	O
system-gate	O
density	O
and	O
has	O
a	O
50	O
percent	O
higher	O
I/O	O
performance	O
than	O
the	O
original	O
Virtex	B-General_Concept
FPGAs	B-Architecture
.	O
</s>
<s>
Xilinx	O
introduced	O
Virtex-II	O
family	O
in	O
January	O
2001	O
on	O
150nm	O
process	O
technology	O
,	O
and	O
Virtex-II	O
Pro	O
family	O
in	O
March	O
2002	O
on	O
90nm	O
process	O
technology	O
.	O
</s>
<s>
The	O
Virtex-II	O
and	O
Virtex-II	O
Pro	O
families	O
are	O
considered	O
legacy	O
devices	O
,	O
and	O
are	O
not	O
recommended	O
for	O
use	O
in	O
new	O
designs	O
,	O
although	O
they	O
are	O
still	O
produced	O
by	O
Xilinx	O
for	O
existing	O
designs	O
.	O
</s>
<s>
The	O
Virtex-4	O
family	O
are	O
considered	O
legacy	O
devices	O
,	O
and	O
are	O
not	O
recommended	O
for	O
use	O
in	O
new	O
designs	O
,	O
although	O
they	O
are	O
still	O
produced	O
by	O
Xilinx	O
for	O
existing	O
designs	O
.	O
</s>
<s>
Virtex-4	O
family	O
was	O
introduced	O
in	O
June	O
2004	O
on	O
90nm	O
process	O
technology	O
.	O
</s>
<s>
Virtex-4	O
FPGAs	B-Architecture
have	O
been	O
used	O
for	O
the	O
ALICE	O
(	O
A	O
Large	O
Ion	O
Collider	O
Experiment	O
)	O
at	O
the	O
CERN	O
European	O
laboratory	O
on	O
the	O
French-Swiss	O
border	O
to	O
map	O
and	O
disentangle	O
the	O
trajectories	O
of	O
thousands	O
of	O
subatomic	O
particles	O
.	O
</s>
<s>
The	O
Virtex-5	O
family	O
was	O
introduced	O
in	O
May	O
2006	O
on	O
65nm	O
process	O
technology	O
.	O
</s>
<s>
The	O
Virtex-5	O
LX	O
and	O
the	O
LXT	O
are	O
intended	O
for	O
logic-intensive	O
applications	O
,	O
and	O
the	O
Virtex-5	O
SXT	O
is	O
for	O
DSP	O
applications	O
.	O
</s>
<s>
With	O
the	O
Virtex-5	O
,	O
Xilinx	O
changed	O
the	O
logic	O
fabric	O
from	O
four-input	O
LUTs	O
to	O
six-input	O
LUTs	O
.	O
</s>
<s>
The	O
Virtex-5	O
series	O
is	O
a	O
65nm	O
design	O
fabricated	B-Architecture
in	O
1.0V	O
,	O
triple-oxide	O
process	O
technology	O
.	O
</s>
<s>
The	O
Virtex-6	O
family	O
was	O
introduced	O
in	O
February	O
2009	O
on	O
a	O
40nm	O
process	O
technology	O
for	O
compute-intensive	O
electronic	O
systems	O
,	O
and	O
the	O
company	O
claims	O
it	O
consumes	O
15	O
percent	O
less	O
power	O
and	O
has	O
15	O
percent	O
improved	O
performance	O
over	O
competing	O
40nm	O
FPGAs	B-Architecture
.	O
</s>
<s>
The	O
Virtex-7	O
family	O
was	O
introduced	O
in	O
June	O
2010	O
on	O
a	O
28nm	O
process	O
technology	O
,	O
and	O
is	O
reported	O
to	O
deliver	O
a	O
two-fold	O
system	O
performance	O
improvement	O
at	O
50	O
percent	O
lower	O
power	O
compared	O
to	O
previous	O
generation	O
Virtex-6	O
devices	O
.	O
</s>
<s>
In	O
addition	O
,	O
Virtex-7	O
doubles	O
the	O
memory	O
bandwidth	O
compared	O
to	O
previous	O
generation	O
Virtex	B-General_Concept
FPGAs	B-Architecture
with	O
1866Mbit/s	O
memory	O
interfacing	O
performance	O
and	O
over	O
two	O
million	O
logic	O
cells	O
.	O
</s>
<s>
In	O
2011	O
,	O
Xilinx	O
began	O
shipping	O
sample	O
quantities	O
of	O
the	O
Virtex-7	O
2000T	O
FPGA	B-Architecture
,	O
which	O
combines	O
four	O
smaller	O
FPGAs	B-Architecture
into	O
a	O
single	O
package	O
by	O
placing	O
them	O
on	O
a	O
special	O
silicon	O
interconnection	O
pad	O
(	O
called	O
an	O
interposer	O
)	O
to	O
deliver	O
6.8	O
billion	O
transistors	O
in	O
a	O
single	O
large	O
chip	O
.	O
</s>
<s>
The	O
interposer	O
provides	O
10,000	O
data	O
pathways	O
between	O
the	O
individual	O
FPGAs	B-Architecture
–	O
roughly	O
10	O
to	O
100	O
times	O
more	O
than	O
would	O
usually	O
be	O
available	O
on	O
a	O
board	O
–	O
to	O
create	O
a	O
single	O
FPGA	B-Architecture
.	O
</s>
<s>
In	O
2012	O
,	O
using	O
the	O
same	O
3D	O
technology	O
,	O
Xilinx	O
introduced	O
initial	O
shipments	O
of	O
their	O
Virtex-7	O
H580T	O
FPGA	B-Architecture
,	O
a	O
heterogeneous	O
device	O
,	O
so	O
called	O
because	O
it	O
comprises	O
two	O
FPGA	B-Architecture
dies	O
and	O
one	O
8-channel	O
28Gbit/s	O
transceiver	O
die	O
in	O
the	O
same	O
package	O
.	O
</s>
<s>
As	O
Xilinx	O
introduced	O
new	O
high	O
capacity	O
3D	O
FPGAs	B-Architecture
,	O
including	O
Virtex-7	O
2000T	O
and	O
Virtex-7	O
H580T	O
products	O
,	O
these	O
devices	O
began	O
to	O
outpace	O
the	O
capacity	O
of	O
Xilinx	O
’s	O
design	O
software	O
,	O
which	O
led	O
the	O
company	O
to	O
completely	O
redesign	O
its	O
tool	O
set	O
.	O
</s>
<s>
The	O
result	O
was	O
the	O
introduction	O
of	O
the	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
,	O
which	O
reduces	O
the	O
time	O
needed	O
for	O
programmable	O
logic	O
and	O
I/O	O
design	O
,	O
and	O
speeds	O
systems	O
integration	O
and	O
implementation	O
compared	O
to	O
the	O
previous	O
software	O
.	O
</s>
<s>
The	O
Virtex	B-General_Concept
UltraScale	O
family	O
was	O
introduced	O
in	O
May	O
,	O
2014	O
on	O
a	O
20nm	O
process	O
technology	O
.	O
</s>
<s>
The	O
UltraScale	O
is	O
a	O
"	O
3D	O
FPGA	B-Architecture
"	O
that	O
contains	O
up	O
to	O
4.4M	O
logic	O
cells	O
,	O
and	O
uses	O
up	O
to	O
45%	O
lower	O
power	O
vs.	O
previous	O
generations	O
,	O
and	O
up	O
to	O
50%	O
lower	O
BOM	O
cost	O
.	O
</s>
<s>
The	O
Virtex	B-General_Concept
UltraScale+	O
family	O
was	O
introduced	O
in	O
January	O
2016	O
on	O
a	O
16nm	O
process	O
technology	O
.	O
</s>
<s>
The	O
Virtex-II	O
Pro	O
,	O
Virtex-4	O
,	O
Virtex-5	O
,	O
and	O
Virtex-6	O
FPGA	B-Architecture
families	O
,	O
which	O
include	O
up	O
to	O
two	O
embedded	O
IBM	B-Architecture
PowerPC	I-Architecture
cores	O
,	O
are	O
targeted	O
to	O
the	O
needs	O
of	O
system-on-chip	B-Architecture
(	O
SoC	O
)	O
designers	O
.	O
</s>
