<s>
Very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
refers	O
to	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
designed	O
to	O
exploit	O
instruction	B-Operating_System
level	I-Operating_System
parallelism	I-Operating_System
(	O
ILP	O
)	O
.	O
</s>
<s>
Whereas	O
conventional	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPU	O
,	O
processor	O
)	O
mostly	O
allow	O
programs	O
to	O
specify	O
instructions	O
to	O
execute	O
in	O
sequence	O
only	O
,	O
a	O
VLIW	B-General_Concept
processor	O
allows	O
programs	O
to	O
explicitly	O
specify	O
instructions	O
to	O
execute	O
in	O
parallel	B-Operating_System
.	O
</s>
<s>
The	O
traditional	O
means	O
to	O
improve	O
performance	O
in	O
processors	O
include	O
dividing	O
instructions	O
into	O
substeps	O
so	O
the	O
instructions	O
can	O
be	O
executed	O
partly	O
at	O
the	O
same	O
time	O
(	O
termed	O
pipelining	O
)	O
,	O
dispatching	O
individual	O
instructions	O
to	O
be	O
executed	O
independently	O
,	O
in	O
different	O
parts	O
of	O
the	O
processor	O
(	O
superscalar	B-General_Concept
architectures	I-General_Concept
)	O
,	O
and	O
even	O
executing	O
instructions	O
in	O
an	O
order	O
different	O
from	O
the	O
program	O
(	O
out-of-order	B-General_Concept
execution	I-General_Concept
)	O
.	O
</s>
<s>
In	O
contrast	O
,	O
the	O
VLIW	B-General_Concept
method	O
depends	O
on	O
the	O
programs	O
providing	O
all	O
the	O
decisions	O
regarding	O
which	O
instructions	O
to	O
execute	O
simultaneously	O
and	O
how	O
to	O
resolve	O
conflicts	O
.	O
</s>
<s>
As	O
a	O
practical	O
matter	O
,	O
this	O
means	O
that	O
the	O
compiler	B-Language
(	O
software	O
used	O
to	O
create	O
the	O
final	O
programs	O
)	O
becomes	O
more	O
complex	O
,	O
but	O
the	O
hardware	O
is	O
simpler	O
than	O
in	O
many	O
other	O
means	O
of	O
parallelism	B-Operating_System
.	O
</s>
<s>
A	O
processor	O
that	O
executes	O
every	O
instruction	O
one	O
after	O
the	O
other	O
(	O
i.e.	O
,	O
a	O
non-pipelined	O
scalar	O
architecture	O
)	O
may	O
use	O
processor	O
resources	O
inefficiently	O
,	O
yielding	O
potential	O
poor	O
performance	O
.	O
</s>
<s>
The	O
performance	O
can	O
be	O
improved	O
by	O
executing	O
different	O
substeps	O
of	O
sequential	O
instructions	O
simultaneously	O
(	O
termed	O
pipelining	O
)	O
,	O
or	O
even	O
executing	O
multiple	O
instructions	O
entirely	O
simultaneously	O
as	O
in	O
superscalar	B-General_Concept
architectures	I-General_Concept
.	O
</s>
<s>
Further	O
improvement	O
can	O
be	O
achieved	O
by	O
executing	O
instructions	O
in	O
an	O
order	O
different	O
from	O
that	O
in	O
which	O
they	O
occur	O
in	O
a	O
program	O
,	O
termed	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
Before	O
executing	O
any	O
operations	O
in	O
parallel	B-Operating_System
,	O
the	O
processor	O
must	O
verify	O
that	O
the	O
instructions	O
have	O
no	O
interdependencies	O
.	O
</s>
<s>
In	O
contrast	O
,	O
VLIW	B-General_Concept
executes	O
operations	O
in	O
parallel	B-Operating_System
,	O
based	O
on	O
a	O
fixed	O
schedule	O
,	O
determined	O
when	O
programs	O
are	O
compiled	B-Language
.	O
</s>
<s>
Since	O
determining	O
the	O
order	O
of	O
execution	O
of	O
operations	O
(	O
including	O
which	O
operations	O
can	O
execute	O
simultaneously	O
)	O
is	O
handled	O
by	O
the	O
compiler	B-Language
,	O
the	O
processor	O
does	O
not	O
need	O
the	O
scheduling	O
hardware	O
that	O
the	O
three	O
methods	O
described	O
above	O
require	O
.	O
</s>
<s>
Thus	O
,	O
VLIW	B-General_Concept
CPUs	O
offer	O
more	O
computing	O
with	O
less	O
hardware	O
complexity	O
(	O
but	O
greater	O
compiler	B-Language
complexity	O
)	O
than	O
do	O
most	O
superscalar	B-General_Concept
CPUs	O
.	O
</s>
<s>
This	O
is	O
also	O
complementary	O
to	O
the	O
idea	O
that	O
as	O
many	O
computations	O
as	O
possible	O
should	O
be	O
done	O
before	O
the	O
program	O
is	O
executed	O
,	O
at	O
compile	B-Application
time	I-Application
.	O
</s>
<s>
In	O
superscalar	B-General_Concept
designs	O
,	O
the	O
number	O
of	O
execution	B-General_Concept
units	I-General_Concept
is	O
invisible	O
to	O
the	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
For	O
most	O
superscalar	B-General_Concept
designs	O
,	O
the	O
instruction	B-General_Concept
width	I-General_Concept
is	O
32	O
bits	O
or	O
fewer	O
.	O
</s>
<s>
In	O
contrast	O
,	O
one	O
VLIW	B-General_Concept
instruction	O
encodes	O
multiple	O
operations	O
,	O
at	O
least	O
one	O
operation	O
for	O
each	O
execution	B-General_Concept
unit	I-General_Concept
of	O
a	O
device	O
.	O
</s>
<s>
For	O
example	O
,	O
if	O
a	O
VLIW	B-General_Concept
device	O
has	O
five	O
execution	B-General_Concept
units	I-General_Concept
,	O
then	O
a	O
VLIW	B-General_Concept
instruction	O
for	O
the	O
device	O
has	O
five	O
operation	O
fields	O
,	O
each	O
field	O
specifying	O
what	O
operation	O
should	O
be	O
done	O
on	O
that	O
corresponding	O
execution	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
To	O
accommodate	O
these	O
operation	O
fields	O
,	O
VLIW	B-General_Concept
instructions	O
are	O
usually	O
at	O
least	O
64	O
bits	O
wide	O
,	O
and	O
far	O
wider	O
on	O
some	O
architectures	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
following	O
is	O
an	O
instruction	O
for	O
the	O
Super	B-General_Concept
Harvard	I-General_Concept
Architecture	I-General_Concept
Single-Chip	I-General_Concept
Computer	I-General_Concept
(	O
SHARC	B-General_Concept
)	O
.	O
</s>
<s>
Since	O
the	O
earliest	O
days	O
of	O
computer	O
architecture	O
,	O
some	O
CPUs	O
have	O
added	O
several	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
to	O
run	O
in	O
parallel	B-Operating_System
.	O
</s>
<s>
Superscalar	B-General_Concept
CPUs	O
use	O
hardware	O
to	O
decide	O
which	O
operations	O
can	O
run	O
in	O
parallel	B-Operating_System
at	O
runtime	O
,	O
while	O
VLIW	B-General_Concept
CPUs	O
use	O
software	O
(	O
the	O
compiler	B-Language
)	O
to	O
decide	O
which	O
operations	O
can	O
run	O
in	O
parallel	B-Operating_System
in	O
advance	O
.	O
</s>
<s>
Because	O
the	O
complexity	O
of	O
instruction	O
scheduling	O
is	O
moved	O
into	O
the	O
compiler	B-Language
,	O
complexity	O
of	O
hardware	O
can	O
be	O
reduced	O
substantially	O
.	O
</s>
<s>
Most	O
modern	O
CPUs	O
guess	O
which	O
branch	O
will	O
be	O
taken	O
even	O
before	O
the	O
calculation	O
is	O
complete	O
,	O
so	O
that	O
they	O
can	O
load	O
the	O
instructions	O
for	O
the	O
branch	O
,	O
or	O
(	O
in	O
some	O
architectures	O
)	O
even	O
start	O
to	O
compute	B-General_Concept
them	I-General_Concept
speculatively	I-General_Concept
.	O
</s>
<s>
This	O
has	O
led	O
to	O
increasingly	O
complex	O
instruction-dispatch	O
logic	O
that	O
attempts	O
to	O
guess	O
correctly	O
,	O
and	O
the	O
simplicity	O
of	O
the	O
original	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
(	O
RISC	B-Architecture
)	O
designs	O
has	O
been	O
eroded	O
.	O
</s>
<s>
VLIW	B-General_Concept
lacks	O
this	O
logic	O
,	O
and	O
thus	O
lacks	O
its	O
energy	O
use	O
,	O
possible	O
design	O
defects	O
,	O
and	O
other	O
negative	O
aspects	O
.	O
</s>
<s>
In	O
a	O
VLIW	B-General_Concept
,	O
the	O
compiler	B-Language
uses	O
heuristics	O
or	O
profile	O
information	O
to	O
guess	O
the	O
direction	O
of	O
a	O
branch	O
.	O
</s>
<s>
If	O
the	O
branch	O
takes	O
an	O
unexpected	O
way	O
,	O
the	O
compiler	B-Language
has	O
already	O
generated	O
compensating	O
code	O
to	O
discard	O
speculative	O
results	O
to	O
preserve	O
program	O
semantics	O
.	O
</s>
<s>
Vector	B-Operating_System
processor	I-Operating_System
cores	O
(	O
designed	O
for	O
large	O
one-dimensional	B-Data_Structure
arrays	I-Data_Structure
of	O
data	O
called	O
vectors	O
)	O
can	O
be	O
combined	O
with	O
the	O
VLIW	B-General_Concept
architecture	O
such	O
as	O
in	O
the	O
Fujitsu	B-General_Concept
FR-V	I-General_Concept
microprocessor	O
,	O
further	O
increasing	O
throughput	O
and	O
speed	O
.	O
</s>
<s>
The	O
concept	O
of	O
VLIW	B-General_Concept
architecture	O
,	O
and	O
the	O
term	O
VLIW	B-General_Concept
,	O
were	O
invented	O
by	O
Josh	O
Fisher	O
in	O
his	O
research	O
group	O
at	O
Yale	O
University	O
in	O
the	O
early	O
1980s	O
.	O
</s>
<s>
His	O
original	O
development	O
of	O
trace	B-Application
scheduling	I-Application
as	O
a	O
compiling	B-Language
method	O
for	O
VLIW	B-General_Concept
was	O
developed	O
when	O
he	O
was	O
a	O
graduate	O
student	O
at	O
New	O
York	O
University	O
.	O
</s>
<s>
Before	O
VLIW	B-General_Concept
,	O
the	O
notion	O
of	O
prescheduling	O
execution	B-General_Concept
units	I-General_Concept
and	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
in	O
software	O
was	O
well	O
established	O
in	O
the	O
practice	O
of	O
developing	O
horizontal	O
microcode	O
.	O
</s>
<s>
Before	O
Fisher	O
the	O
theoretical	O
aspects	O
of	O
what	O
would	O
be	O
later	O
called	O
VLIW	B-General_Concept
were	O
developed	O
by	O
the	O
Soviet	O
computer	O
scientist	O
Mikhail	O
Kartsev	O
based	O
on	O
his	O
Sixties	O
work	O
on	O
military-oriented	O
M-9	O
and	O
M-10	O
computers	O
.	O
</s>
<s>
Fisher	O
's	O
innovations	O
involved	O
developing	O
a	O
compiler	B-Language
that	O
could	O
target	O
horizontal	O
microcode	O
from	O
programs	O
written	O
in	O
an	O
ordinary	O
programming	O
language	O
.	O
</s>
<s>
He	O
realized	O
that	O
to	O
get	O
good	O
performance	O
and	O
target	O
a	O
wide-issue	B-Operating_System
machine	O
,	O
it	O
would	O
be	O
necessary	O
to	O
find	O
parallelism	B-Operating_System
beyond	O
that	O
generally	O
within	O
a	O
basic	B-Application
block	I-Application
.	O
</s>
<s>
He	O
also	O
developed	O
region	O
scheduling	O
methods	O
to	O
identify	O
parallelism	B-Operating_System
beyond	O
basic	B-Application
blocks	I-Application
.	O
</s>
<s>
Trace	B-Application
scheduling	I-Application
is	O
such	O
a	O
method	O
,	O
and	O
involves	O
scheduling	O
the	O
most	O
likely	O
path	O
of	O
basic	B-Application
blocks	I-Application
first	O
,	O
inserting	O
compensating	O
code	O
to	O
deal	O
with	O
speculative	O
motions	O
,	O
scheduling	O
the	O
second	O
most	O
likely	O
trace	O
,	O
and	O
so	O
on	O
,	O
until	O
the	O
schedule	O
is	O
complete	O
.	O
</s>
<s>
Fisher	O
's	O
second	O
innovation	O
was	O
the	O
notion	O
that	O
the	O
target	O
CPU	O
architecture	O
should	O
be	O
designed	O
to	O
be	O
a	O
reasonable	O
target	O
for	O
a	O
compiler	B-Language
;	O
that	O
the	O
compiler	B-Language
and	O
the	O
architecture	O
for	O
a	O
VLIW	B-General_Concept
processor	O
must	O
be	O
codesigned	O
.	O
</s>
<s>
This	O
was	O
inspired	O
partly	O
by	O
the	O
difficulty	O
Fisher	O
observed	O
at	O
Yale	O
of	O
compiling	B-Language
for	O
architectures	O
like	O
Floating	O
Point	O
Systems	O
 '	O
FPS164	O
,	O
which	O
had	O
a	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
(	O
CISC	O
)	O
architecture	O
that	O
separated	O
instruction	O
initiation	O
from	O
the	O
instructions	O
that	O
saved	O
the	O
result	O
,	O
needing	O
very	O
complex	O
scheduling	O
algorithms	O
.	O
</s>
<s>
Fisher	O
developed	O
a	O
set	O
of	O
principles	O
characterizing	O
a	O
proper	O
VLIW	B-General_Concept
design	O
,	O
such	O
as	O
self-draining	O
pipelines	O
,	O
wide	O
multi-port	O
register	B-General_Concept
files	I-General_Concept
,	O
and	O
memory	B-General_Concept
architectures	I-General_Concept
.	O
</s>
<s>
These	O
principles	O
made	O
it	O
easier	O
for	O
compilers	B-Language
to	O
emit	O
fast	O
code	O
.	O
</s>
<s>
The	O
first	O
VLIW	B-General_Concept
compiler	B-Language
was	O
described	O
in	O
a	O
Ph.D.	O
thesis	O
by	O
John	O
Ellis	O
,	O
supervised	O
by	O
Fisher	O
.	O
</s>
<s>
The	O
compiler	B-Language
was	O
named	O
Bulldog	O
,	O
after	O
Yale	O
's	O
mascot	O
.	O
</s>
<s>
Multiflow	O
produced	O
the	O
TRACE	O
series	O
of	O
VLIW	B-General_Concept
minisupercomputers	B-Device
,	O
shipping	O
their	O
first	O
machines	O
in	O
1987	O
.	O
</s>
<s>
Multiflow	O
's	O
VLIW	B-General_Concept
could	O
issue	O
28	O
operations	O
in	O
parallel	B-Operating_System
per	O
instruction	O
.	O
</s>
<s>
The	O
major	O
semiconductor	O
companies	O
recognized	O
the	O
value	O
of	O
Multiflow	O
technology	O
in	O
this	O
context	O
,	O
so	O
the	O
compiler	B-Language
and	O
architecture	O
were	O
subsequently	O
licensed	O
to	O
most	O
of	O
these	O
firms	O
.	O
</s>
<s>
Cydrome	O
was	O
a	O
company	O
producing	O
VLIW	B-General_Concept
numeric	O
processors	O
using	O
emitter-coupled	B-General_Concept
logic	I-General_Concept
(	O
ECL	O
)	O
integrated	O
circuits	O
in	O
the	O
same	O
timeframe	O
(	O
late	O
1980s	O
)	O
.	O
</s>
<s>
Along	O
with	O
the	O
above	O
systems	O
,	O
during	O
the	O
same	O
time	O
(	O
1989	O
–	O
1990	O
)	O
,	O
Intel	O
implemented	O
VLIW	B-General_Concept
in	O
the	O
Intel	B-General_Concept
i860	I-General_Concept
,	O
their	O
first	O
64-bit	O
microprocessor	O
,	O
and	O
the	O
first	O
processor	O
to	O
implement	O
VLIW	B-General_Concept
on	O
one	O
chip	O
.	O
</s>
<s>
This	O
processor	O
could	O
operate	O
in	O
both	O
simple	O
RISC	B-Architecture
mode	O
and	O
VLIW	B-General_Concept
mode	O
:	O
</s>
<s>
In	O
the	O
early	O
1990s	O
,	O
Intel	O
introduced	O
the	O
i860	O
RISC	B-Architecture
microprocessor	O
.	O
</s>
<s>
This	O
simple	O
chip	O
had	O
two	O
modes	O
of	O
operation	O
:	O
a	O
scalar	O
mode	O
and	O
a	O
VLIW	B-General_Concept
mode	O
.	O
</s>
<s>
In	O
the	O
VLIW	B-General_Concept
mode	O
,	O
the	O
processor	O
always	O
fetched	O
two	O
instructions	O
and	O
assumed	O
that	O
one	O
was	O
an	O
integer	O
instruction	O
and	O
the	O
other	O
floating-point	O
.	O
</s>
<s>
The	O
i860	O
's	O
VLIW	B-General_Concept
mode	O
was	O
used	O
extensively	O
in	O
embedded	B-Architecture
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	B-Architecture
)	O
applications	O
since	O
the	O
application	O
execution	O
and	O
datasets	O
were	O
simple	O
,	O
well	O
ordered	O
and	O
predictable	O
,	O
allowing	O
designers	O
to	O
fully	O
exploit	O
the	O
parallel	B-Operating_System
execution	O
advantages	O
enabled	O
by	O
VLIW	B-General_Concept
.	O
</s>
<s>
In	O
VLIW	B-General_Concept
mode	O
,	O
the	O
i860	O
could	O
maintain	O
floating-point	O
performance	O
in	O
the	O
range	O
of	O
20-40	O
double-precision	O
MFLOPS	O
;	O
a	O
very	O
high	O
value	O
for	O
its	O
time	O
and	O
for	O
a	O
processor	O
running	O
at	O
25-50Mhz	O
.	O
</s>
<s>
In	O
the	O
1990s	O
,	O
Hewlett-Packard	O
researched	O
this	O
problem	O
as	O
a	O
side	O
effect	O
of	O
ongoing	O
work	O
on	O
their	O
PA-RISC	B-Device
processor	O
family	O
.	O
</s>
<s>
They	O
found	O
that	O
the	O
CPU	O
could	O
be	O
greatly	O
simplified	O
by	O
removing	O
the	O
complex	O
dispatch	O
logic	O
from	O
the	O
CPU	O
and	O
placing	O
it	O
in	O
the	O
compiler	B-Language
.	O
</s>
<s>
Compilers	B-Language
of	O
the	O
day	O
were	O
far	O
more	O
complex	O
than	O
those	O
of	O
the	O
1980s	O
,	O
so	O
the	O
added	O
complexity	O
in	O
the	O
compiler	B-Language
was	O
considered	O
to	O
be	O
a	O
small	O
cost	O
.	O
</s>
<s>
VLIW	B-General_Concept
CPUs	O
are	O
usually	O
made	O
of	O
multiple	O
RISC-like	O
execution	B-General_Concept
units	I-General_Concept
that	O
operate	O
independently	O
.	O
</s>
<s>
Contemporary	O
VLIWs	B-General_Concept
usually	O
have	O
four	O
to	O
eight	O
main	O
execution	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
Compilers	B-Language
generate	O
initial	O
instruction	O
sequences	O
for	O
the	O
VLIW	B-General_Concept
CPU	O
in	O
roughly	O
the	O
same	O
manner	O
as	O
for	O
traditional	O
CPUs	O
,	O
generating	O
a	O
sequence	O
of	O
RISC-like	O
instructions	O
.	O
</s>
<s>
The	O
compiler	B-Language
analyzes	O
this	O
code	O
for	O
dependence	O
relationships	O
and	O
resource	O
requirements	O
.	O
</s>
<s>
In	O
this	O
process	O
,	O
independent	O
instructions	O
can	O
be	O
scheduled	O
in	O
parallel	B-Operating_System
.	O
</s>
<s>
Because	O
VLIWs	B-General_Concept
typically	O
represent	O
instructions	O
scheduled	O
in	O
parallel	B-Operating_System
with	O
a	O
longer	O
instruction	B-Language
word	I-Language
that	O
incorporates	O
the	O
individual	O
instructions	O
,	O
this	O
results	O
in	O
a	O
much	O
longer	O
opcode	B-Language
(	O
termed	O
very	O
long	O
)	O
to	O
specify	O
what	O
executes	O
on	O
a	O
given	O
cycle	O
.	O
</s>
<s>
Examples	O
of	O
contemporary	O
VLIW	B-General_Concept
CPUs	O
include	O
the	O
TriMedia	B-General_Concept
media	O
processors	O
by	O
NXP	O
(	O
formerly	O
Philips	O
Semiconductors	O
)	O
,	O
the	O
Super	B-General_Concept
Harvard	I-General_Concept
Architecture	I-General_Concept
Single-Chip	I-General_Concept
Computer	I-General_Concept
(	O
SHARC	B-General_Concept
)	O
DSP	B-Architecture
by	O
Analog	O
Devices	O
,	O
the	O
ST200	B-General_Concept
family	I-General_Concept
by	O
STMicroelectronics	O
based	O
on	O
the	O
Lx	O
architecture	O
(	O
designed	O
in	O
Josh	O
Fisher	O
's	O
HP	O
lab	O
by	O
Paolo	O
Faraboschi	O
)	O
,	O
the	O
FR-V	B-General_Concept
from	O
Fujitsu	O
,	O
the	O
BSP15/16	O
from	O
Pixelworks	O
,	O
the	O
CEVA-X	O
DSP	B-Architecture
from	O
CEVA	O
,	O
the	O
Jazz	B-General_Concept
DSP	I-General_Concept
from	O
Improv	O
Systems	O
,	O
the	O
HiveFlex	O
series	O
from	O
Silicon	O
Hive	O
,	O
and	O
the	O
MPPA	O
Manycore	O
family	O
by	O
Kalray	O
.	O
</s>
<s>
The	O
Texas	B-Architecture
Instruments	I-Architecture
TMS320	I-Architecture
DSP	B-Architecture
line	O
has	O
evolved	O
,	O
in	O
its	O
C6000	O
family	O
,	O
to	O
look	O
more	O
like	O
a	O
VLIW	B-General_Concept
,	O
in	O
contrast	O
to	O
the	O
earlier	O
C5000	O
family	O
.	O
</s>
<s>
These	O
contemporary	O
VLIW	B-General_Concept
CPUs	O
are	O
mainly	O
successful	O
as	O
embedded	B-Architecture
media	O
processors	O
for	O
consumer	O
electronic	O
devices	O
.	O
</s>
<s>
VLIW	B-General_Concept
features	O
have	O
also	O
been	O
added	O
to	O
configurable	O
processor	O
cores	O
for	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
designs	O
.	O
</s>
<s>
The	O
Xtensa	O
C/C	O
++	O
compiler	B-Language
can	O
freely	O
intermix	O
32	O
-	O
or	O
64-bit	O
FLIX	O
instructions	O
with	O
the	O
Xtensa	O
processor	O
's	O
one-operation	O
RISC	B-Architecture
instructions	O
,	O
which	O
are	O
16	O
or	O
24	O
bits	O
wide	O
.	O
</s>
<s>
By	O
packing	O
multiple	O
operations	O
into	O
a	O
wide	O
32	O
-	O
or	O
64-bit	O
instruction	B-Language
word	I-Language
and	O
allowing	O
these	O
multi-operation	O
instructions	O
to	O
intermix	O
with	O
shorter	O
RISC	B-Architecture
instructions	O
,	O
FLIX	O
allows	O
SoC	O
designers	O
to	O
realize	O
VLIW	B-General_Concept
's	O
performance	O
advantages	O
while	O
eliminating	O
the	O
code	O
bloat	O
of	O
early	O
VLIW	B-General_Concept
architectures	O
.	O
</s>
<s>
The	O
Infineon	O
Carmel	O
DSP	B-Architecture
is	O
another	O
VLIW	B-General_Concept
processor	O
core	O
intended	O
for	O
SoC	O
.	O
</s>
<s>
It	O
uses	O
a	O
similar	O
code	O
density	O
improvement	O
method	O
called	O
configurable	O
long	O
instruction	B-Language
word	I-Language
(	O
CLIW	O
)	O
.	O
</s>
<s>
Outside	O
embedded	B-Architecture
processing	O
markets	O
,	O
Intel	O
's	O
Itanium	B-General_Concept
IA-64	O
explicitly	B-General_Concept
parallel	I-General_Concept
instruction	I-General_Concept
computing	I-General_Concept
(	O
EPIC	O
)	O
and	O
Elbrus	B-General_Concept
2000	I-General_Concept
appear	O
as	O
the	O
only	O
examples	O
of	O
a	O
widely	O
used	O
VLIW	B-General_Concept
CPU	O
architectures	O
.	O
</s>
<s>
However	O
,	O
EPIC	B-General_Concept
architecture	I-General_Concept
is	O
sometimes	O
distinguished	O
from	O
a	O
pure	O
VLIW	B-General_Concept
architecture	O
,	O
since	O
EPIC	O
advocates	O
full	O
instruction	O
predication	O
,	O
rotating	O
register	B-General_Concept
files	I-General_Concept
,	O
and	O
a	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
that	O
can	O
encode	O
non-parallel	O
instruction	O
groups	O
.	O
</s>
<s>
VLIWs	B-General_Concept
also	O
gained	O
significant	O
consumer	O
penetration	O
in	O
the	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
market	O
,	O
though	O
both	O
Nvidia	O
and	O
AMD	O
have	O
since	O
moved	O
to	O
RISC	B-Architecture
architectures	I-Architecture
to	O
improve	O
performance	O
on	O
non-graphics	O
workloads	O
.	O
</s>
<s>
ATI	O
Technologies	O
 '	O
(	O
ATI	O
)	O
and	O
Advanced	O
Micro	O
Devices	O
 '	O
(	O
AMD	O
)	O
TeraScale	B-Architecture
microarchitecture	O
for	O
graphics	B-Architecture
processing	I-Architecture
units	I-Architecture
(	O
GPUs	B-Architecture
)	O
is	O
a	O
VLIW	B-General_Concept
microarchitecture	O
.	O
</s>
<s>
In	O
December	O
2015	O
,	O
the	O
first	O
shipment	O
of	O
PCs	O
based	O
on	O
VLIW	B-General_Concept
CPU	O
Elbrus-4s	B-General_Concept
was	O
made	O
in	O
Russia	O
.	O
</s>
<s>
The	O
Neo	O
by	O
REX	O
Computing	O
is	O
a	O
processor	O
consisting	O
of	O
a	O
2D	O
mesh	O
of	O
VLIW	B-General_Concept
cores	O
aimed	O
at	O
power	O
efficiency	O
.	O
</s>
<s>
The	O
Elbrus	B-General_Concept
2000	I-General_Concept
(	O
)	O
and	O
its	O
successors	O
are	O
Russian	O
512-bit	O
wide	O
VLIW	B-General_Concept
microprocessors	O
developed	O
by	O
Moscow	O
Center	O
of	O
SPARC	O
Technologies	O
(	O
MCST	O
)	O
and	O
fabricated	O
by	O
TSMC	O
.	O
</s>
<s>
When	O
silicon	O
technology	O
allowed	O
for	O
wider	O
implementations	O
(	O
with	O
more	O
execution	B-General_Concept
units	I-General_Concept
)	O
to	O
be	O
built	O
,	O
the	O
compiled	B-Language
programs	O
for	O
the	O
earlier	O
generation	O
would	O
not	O
run	O
on	O
the	O
wider	O
implementations	O
,	O
as	O
the	O
encoding	O
of	O
binary	O
instructions	O
depended	O
on	O
the	O
number	O
of	O
execution	B-General_Concept
units	I-General_Concept
of	O
the	O
machine	O
.	O
</s>
<s>
Transmeta	O
addressed	O
this	O
issue	O
by	O
including	O
a	O
binary-to-binary	O
software	O
compiler	B-Language
layer	O
(	O
termed	O
code	O
morphing	O
)	O
in	O
their	O
Crusoe	B-General_Concept
implementation	O
of	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
.	O
</s>
<s>
This	O
mechanism	O
was	O
advertised	O
to	O
basically	O
recompile	B-Language
,	O
optimize	O
,	O
and	O
translate	O
x86	B-Operating_System
opcodes	B-Language
at	O
runtime	O
into	O
the	O
CPU	O
's	O
internal	O
machine	O
code	O
.	O
</s>
<s>
Thus	O
,	O
the	O
Transmeta	O
chip	O
is	O
internally	O
a	O
VLIW	B-General_Concept
processor	O
,	O
effectively	O
decoupled	O
from	O
the	O
x86	B-Operating_System
CISC	O
instruction	B-General_Concept
set	I-General_Concept
that	O
it	O
executes	O
.	O
</s>
<s>
Intel	O
's	O
Itanium	B-General_Concept
architecture	O
(	O
among	O
others	O
)	O
solved	O
the	O
backward-compatibility	O
problem	O
with	O
a	O
more	O
general	O
mechanism	O
.	O
</s>
<s>
Within	O
each	O
of	O
the	O
multiple-opcode	O
instructions	O
,	O
a	O
bit	O
field	O
is	O
allocated	O
to	O
denote	O
dependency	O
on	O
the	O
prior	O
VLIW	B-General_Concept
instruction	O
within	O
the	O
program	O
instruction	O
stream	O
.	O
</s>
<s>
These	O
bits	O
are	O
set	O
at	O
compile	B-Application
time	I-Application
,	O
thus	O
relieving	O
the	O
hardware	O
from	O
calculating	O
this	O
dependency	O
information	O
.	O
</s>
<s>
Having	O
this	O
dependency	O
information	O
encoded	O
in	O
the	O
instruction	O
stream	O
allows	O
wider	O
implementations	O
to	O
issue	O
multiple	O
non-dependent	O
VLIW	B-General_Concept
instructions	O
in	O
parallel	B-Operating_System
per	O
cycle	O
,	O
while	O
narrower	O
implementations	O
would	O
issue	O
a	O
smaller	O
number	O
of	O
VLIW	B-General_Concept
instructions	O
per	O
cycle	O
.	O
</s>
<s>
Another	O
perceived	O
deficiency	O
of	O
VLIW	B-General_Concept
designs	O
is	O
the	O
code	O
bloat	O
that	O
occurs	O
when	O
one	O
or	O
more	O
execution	O
unit(s )	O
have	O
no	O
useful	O
work	O
to	O
do	O
and	O
thus	O
must	O
execute	O
No	B-Language
Operation	I-Language
NOP	B-Language
instructions	O
.	O
</s>
<s>
This	O
occurs	O
when	O
there	O
are	O
dependencies	O
in	O
the	O
code	O
and	O
the	O
instruction	B-General_Concept
pipelines	I-General_Concept
must	O
be	O
allowed	O
to	O
drain	O
before	O
later	O
operations	O
can	O
proceed	O
.	O
</s>
<s>
Since	O
the	O
number	O
of	O
transistors	O
on	O
a	O
chip	O
has	O
grown	O
,	O
the	O
perceived	O
disadvantages	O
of	O
the	O
VLIW	B-General_Concept
have	O
diminished	O
in	O
importance	O
.	O
</s>
<s>
VLIW	B-General_Concept
architectures	O
are	O
growing	O
in	O
popularity	O
,	O
especially	O
in	O
the	O
embedded	B-Architecture
system	I-Architecture
market	O
,	O
where	O
it	O
is	O
possible	O
to	O
customize	O
a	O
processor	O
for	O
an	O
application	O
in	O
a	O
system-on-a-chip	B-Architecture
.	O
</s>
