<s>
In	O
integrated	O
circuit	O
design	O
,	O
VerilogCSP	B-Language
is	O
a	O
set	O
of	O
macros	O
added	O
to	O
Verilog	B-Language
HDL	I-Language
to	O
support	O
Communicating	O
Sequential	O
Processes	O
(	O
CSP	O
)	O
channel	O
communications	O
.	O
</s>
<s>
These	O
macros	O
are	O
intended	O
to	O
be	O
used	O
in	O
designing	O
digital	B-Application
asynchronous	I-Application
circuits	I-Application
.	O
</s>
<s>
VerilogCSP	B-Language
also	O
describes	O
nonlinear	O
pipelines	B-General_Concept
and	O
high-level	O
channel	O
timing	O
properties	O
,	O
such	O
as	O
forward	O
and	O
backward	O
latencies	O
,	O
minimum	O
cycle	O
time	O
,	O
and	O
slack	O
.	O
</s>
