<s>
Verilog	B-Language
,	O
standardized	O
as	O
IEEE	B-Language
1364	I-Language
,	O
is	O
a	O
hardware	O
description	O
language	O
(	O
HDL	O
)	O
used	O
to	O
model	O
electronic	O
systems	O
.	O
</s>
<s>
It	O
is	O
most	O
commonly	O
used	O
in	O
the	O
design	O
and	O
verification	O
of	O
digital	O
circuits	O
at	O
the	O
register-transfer	O
level	O
of	O
abstraction	B-Application
.	O
</s>
<s>
In	O
2009	O
,	O
the	O
Verilog	B-Language
standard	O
(	O
IEEE	O
1364-2005	O
)	O
was	O
merged	O
into	O
the	O
SystemVerilog	B-Language
standard	O
,	O
creating	O
IEEE	O
Standard	O
1800-2009	O
.	O
</s>
<s>
Since	O
then	O
,	O
Verilog	B-Language
is	O
officially	O
part	O
of	O
the	O
SystemVerilog	B-Language
language	O
.	O
</s>
<s>
Hardware	O
description	O
languages	O
such	O
as	O
Verilog	B-Language
are	O
similar	O
to	O
software	O
programming	O
languages	O
because	O
they	O
include	O
ways	O
of	O
describing	O
the	O
propagation	O
time	O
and	O
signal	O
strengths	O
(	O
sensitivity	O
)	O
.	O
</s>
<s>
Since	O
these	O
concepts	O
are	O
part	O
of	O
Verilog	B-Language
's	O
language	O
semantics	O
,	O
designers	O
could	O
quickly	O
write	O
descriptions	O
of	O
large	O
circuits	O
in	O
a	O
relatively	O
compact	O
and	O
concise	O
form	O
.	O
</s>
<s>
At	O
the	O
time	O
of	O
Verilog	B-Language
's	O
introduction	O
(	O
1984	O
)	O
,	O
Verilog	B-Language
represented	O
a	O
tremendous	O
productivity	O
improvement	O
for	O
circuit	O
designers	O
who	O
were	O
already	O
using	O
graphical	O
schematic	O
capture	O
software	O
and	O
specially	O
written	O
software	O
programs	O
to	O
document	O
and	O
simulate	B-Language
electronic	I-Language
circuits	I-Language
.	O
</s>
<s>
The	O
designers	O
of	O
Verilog	B-Language
wanted	O
a	O
language	O
with	O
syntax	O
similar	O
to	O
the	O
C	B-Language
programming	I-Language
language	I-Language
,	O
which	O
was	O
already	O
widely	O
used	O
in	O
engineering	O
software	O
development	O
.	O
</s>
<s>
Like	O
C	B-Language
,	O
Verilog	B-Language
is	O
case-sensitive	O
and	O
has	O
a	O
basic	O
preprocessor	B-General_Concept
(	O
though	O
less	O
sophisticated	O
than	O
that	O
of	O
ANSI	O
C/C	O
++	O
)	O
.	O
</s>
<s>
are	O
equivalent	O
,	O
and	O
its	O
operator	O
precedence	O
is	O
compatible	O
with	O
C	B-Language
.	O
Syntactic	O
differences	O
include	O
:	O
required	O
bit-widths	O
for	O
variable	O
declarations	O
,	O
demarcation	O
of	O
procedural	O
blocks	O
(	O
Verilog	B-Language
uses	O
begin/end	O
instead	O
of	O
curly	O
braces	O
 {  } 	O
)	O
,	O
and	O
many	O
other	O
minor	O
differences	O
.	O
</s>
<s>
Verilog	B-Language
requires	O
that	O
variables	O
be	O
given	O
a	O
definite	O
size	O
.	O
</s>
<s>
In	O
C	B-Language
these	O
sizes	O
are	O
inferred	O
from	O
the	O
'	O
type	O
 '	O
of	O
the	O
variable	O
(	O
for	O
instance	O
an	O
integer	O
type	O
may	O
be	O
32	O
bits	O
)	O
.	O
</s>
<s>
A	O
Verilog	B-Language
design	O
consists	O
of	O
a	O
hierarchy	O
of	O
modules	O
.	O
</s>
<s>
)	O
,	O
concurrent	B-Operating_System
and	O
sequential	O
statement	O
blocks	O
,	O
and	O
instances	O
of	O
other	O
modules	O
(	O
sub-hierarchies	O
)	O
.	O
</s>
<s>
However	O
,	O
the	O
blocks	O
themselves	O
are	O
executed	O
concurrently	O
,	O
making	O
Verilog	B-Language
a	O
dataflow	B-Application
language	I-Application
.	O
</s>
<s>
Verilog	B-Language
's	O
concept	O
of	O
'	O
wire	O
 '	O
consists	O
of	O
both	O
signal	O
values	O
(	O
4-state	O
:	O
"	O
1	O
,	O
0	O
,	O
floating	O
,	O
undefined	O
"	O
)	O
and	O
signal	O
strengths	O
(	O
strong	O
,	O
weak	O
,	O
etc	O
.	O
)	O
.	O
</s>
<s>
A	O
subset	O
of	O
statements	O
in	O
the	O
Verilog	B-Language
language	O
are	O
synthesizable	O
.	O
</s>
<s>
Verilog	B-Language
modules	O
that	O
conform	O
to	O
a	O
synthesizable	O
coding	O
style	O
,	O
known	O
as	O
RTL	O
(	O
register-transfer	O
level	O
)	O
,	O
can	O
be	O
physically	O
realized	O
by	O
synthesis	O
software	O
.	O
</s>
<s>
Synthesis	O
software	O
algorithmically	O
transforms	O
the	O
(	O
abstract	O
)	O
Verilog	B-Language
source	O
into	O
a	O
netlist	O
,	O
a	O
logically	O
equivalent	O
description	O
consisting	O
only	O
of	O
elementary	O
logic	O
primitives	O
(	O
AND	O
,	O
OR	O
,	O
NOT	O
,	O
flip-flops	B-General_Concept
,	O
etc	O
.	O
)	O
</s>
<s>
that	O
are	O
available	O
in	O
a	O
specific	O
FPGA	B-Architecture
or	O
VLSI	O
technology	O
.	O
</s>
<s>
Further	O
manipulations	O
to	O
the	O
netlist	O
ultimately	O
lead	O
to	O
a	O
circuit	O
fabrication	O
blueprint	O
(	O
such	O
as	O
a	O
photo	B-Algorithm
mask	I-Algorithm
set	I-Algorithm
for	O
an	O
ASIC	O
or	O
a	O
bitstream	O
file	O
for	O
an	O
FPGA	B-Architecture
)	O
.	O
</s>
<s>
Verilog	B-Language
was	O
created	O
by	O
Prabhu	O
Goel	O
,	O
Phil	O
Moorby	O
and	O
Chi-Lai	O
Huang	O
between	O
late	O
1983	O
and	O
early	O
1984	O
.	O
</s>
<s>
Cadence	O
now	O
has	O
full	O
proprietary	O
rights	O
to	O
Gateway	O
's	O
Verilog	B-Language
and	O
the	O
Verilog-XL	O
,	O
the	O
HDL-simulator	O
that	O
would	O
become	O
the	O
de	O
facto	O
standard	O
(	O
of	O
Verilog	B-Language
logic	O
simulators	O
)	O
for	O
the	O
next	O
decade	O
.	O
</s>
<s>
Originally	O
,	O
Verilog	B-Language
was	O
only	O
intended	O
to	O
describe	O
and	O
allow	O
simulation	O
;	O
the	O
automated	O
synthesis	O
of	O
subsets	O
of	O
the	O
language	O
to	O
physically	O
realizable	O
structures	O
(	O
gates	O
etc	O
.	O
)	O
</s>
<s>
Verilog	B-Language
is	O
a	O
portmanteau	O
of	O
the	O
words	O
"	O
verification	O
"	O
and	O
"	O
logic	O
"	O
.	O
</s>
<s>
With	O
the	O
increasing	O
success	O
of	O
VHDL	B-Language
at	O
the	O
time	O
,	O
Cadence	O
decided	O
to	O
make	O
the	O
language	O
available	O
for	O
open	O
standardization	O
.	O
</s>
<s>
Cadence	O
transferred	O
Verilog	B-Language
into	O
the	O
public	O
domain	O
under	O
the	O
(	O
OVI	O
)	O
(	O
now	O
known	O
as	O
Accellera	O
)	O
organization	O
.	O
</s>
<s>
Verilog	B-Language
was	O
later	O
submitted	O
to	O
IEEE	O
and	O
became	O
IEEE	O
Standard	O
1364-1995	O
,	O
commonly	O
referred	O
to	O
as	O
Verilog-95	O
.	O
</s>
<s>
In	O
the	O
same	O
time	O
frame	O
Cadence	O
initiated	O
the	O
creation	O
of	O
Verilog-A	B-Language
to	O
put	O
standards	O
support	O
behind	O
its	O
analog	O
simulator	O
Spectre	B-Algorithm
.	O
</s>
<s>
Verilog-A	B-Language
was	O
never	O
intended	O
to	O
be	O
a	O
standalone	O
language	O
and	O
is	O
a	O
subset	O
of	O
Verilog-AMS	B-Language
which	O
encompassed	O
Verilog-95	O
.	O
</s>
<s>
Extensions	O
to	O
Verilog-95	O
were	O
submitted	O
back	O
to	O
IEEE	O
to	O
cover	O
the	O
deficiencies	O
that	O
users	O
had	O
found	O
in	O
the	O
original	O
Verilog	B-Language
standard	O
.	O
</s>
<s>
These	O
extensions	O
became	O
IEEE	O
Standard	O
1364-2001	O
known	O
as	O
Verilog-2001	O
.	O
</s>
<s>
Verilog-2001	O
is	O
a	O
significant	O
upgrade	O
from	O
Verilog-95	O
.	O
</s>
<s>
The	O
same	O
function	O
under	O
Verilog-2001	O
can	O
be	O
more	O
succinctly	O
described	O
by	O
one	O
of	O
the	O
built-in	O
operators	O
:	O
+	O
,	O
-	O
,	O
/	O
,	O
*	O
,	O
>>>	O
.	O
</s>
<s>
A	O
generate	O
–	O
endgenerate	O
construct	O
(	O
similar	O
to	O
VHDL	B-Language
's	O
generate	O
–	O
endgenerate	O
)	O
allows	O
Verilog-2001	O
to	O
control	O
instance	O
and	O
statement	O
instantiation	O
through	O
normal	O
decision	O
operators	O
(	O
case	O
–	O
if	O
–	O
else	O
)	O
.	O
</s>
<s>
Using	O
generate	O
–	O
endgenerate	O
,	O
Verilog-2001	O
can	O
instantiate	O
an	O
array	O
of	O
instances	O
,	O
with	O
control	O
over	O
the	O
connectivity	O
of	O
the	O
individual	O
instances	O
.	O
</s>
<s>
And	O
finally	O
,	O
a	O
few	O
syntax	O
additions	O
were	O
introduced	O
to	O
improve	O
code	O
readability	O
(	O
e.g.	O
</s>
<s>
always	O
,	O
@*	O
,	O
named	O
parameter	O
override	O
,	O
C-style	O
function/task/module	O
header	O
declaration	O
)	O
.	O
</s>
<s>
Verilog-2001	O
is	O
the	O
version	O
of	O
Verilog	B-Language
supported	O
by	O
the	O
majority	O
of	O
commercial	O
EDA	O
software	O
packages	O
.	O
</s>
<s>
Not	O
to	O
be	O
confused	O
with	O
SystemVerilog	B-Language
,	O
Verilog	B-Language
2005	O
(	O
IEEE	O
Standard	O
1364-2005	O
)	O
consists	O
of	O
minor	O
corrections	O
,	O
spec	O
clarifications	O
,	O
and	O
a	O
few	O
new	O
language	O
features	O
(	O
such	O
as	O
the	O
uwire	O
keyword	O
)	O
.	O
</s>
<s>
A	O
separate	O
part	O
of	O
the	O
Verilog	B-Language
standard	O
,	O
Verilog-AMS	B-Language
,	O
attempts	O
to	O
integrate	O
analog	O
and	O
mixed	O
signal	O
modeling	O
with	O
traditional	O
Verilog	B-Language
.	O
</s>
<s>
The	O
advent	O
of	O
hardware	B-Language
verification	I-Language
languages	I-Language
such	O
as	O
OpenVera	B-Language
,	O
and	O
Verisity	O
's	O
e	B-Language
language	I-Language
encouraged	O
the	O
development	O
of	O
Superlog	O
by	O
Co-Design	O
Automation	O
Inc	O
(	O
acquired	O
by	O
Synopsys	O
)	O
.	O
</s>
<s>
The	O
foundations	O
of	O
Superlog	O
and	O
Vera	O
were	O
donated	O
to	O
Accellera	O
,	O
which	O
later	O
became	O
the	O
IEEE	O
standard	O
P1800-2005	O
:	O
SystemVerilog	B-Language
.	O
</s>
<s>
SystemVerilog	B-Language
is	O
a	O
superset	O
of	O
Verilog-2005	O
,	O
with	O
many	O
new	O
features	O
and	O
capabilities	O
to	O
aid	O
design	O
verification	O
and	O
design	O
modeling	O
.	O
</s>
<s>
As	O
of	O
2009	O
,	O
the	O
SystemVerilog	B-Language
and	O
Verilog	B-Language
language	O
standards	O
were	O
merged	O
into	O
SystemVerilog	B-Language
2009	O
(	O
IEEE	O
Standard	O
1800-2009	O
)	O
.	O
</s>
<s>
A	O
simple	O
example	O
of	O
two	O
flip-flops	B-General_Concept
follows	O
:	O
</s>
<s>
The	O
<=	O
operator	O
in	O
Verilog	B-Language
is	O
another	O
aspect	O
of	O
its	O
being	O
a	O
hardware	O
description	O
language	O
as	O
opposed	O
to	O
a	O
normal	O
procedural	O
language	O
.	O
</s>
<s>
The	O
always	O
clause	O
above	O
illustrates	O
the	O
other	O
type	O
of	O
method	O
of	O
use	O
,	O
i.e.	O
</s>
<s>
it	O
executes	O
whenever	O
any	O
of	O
the	O
entities	O
in	O
the	O
list	O
(	O
the	O
b	O
or	O
e	B-Language
)	O
changes	O
.	O
</s>
<s>
After	O
a	O
delay	O
of	O
5	O
time	O
units	O
,	O
c	B-Language
is	O
assigned	O
the	O
value	O
of	O
b	O
and	O
the	O
value	O
of	O
c	B-Language
^	O
e	B-Language
is	O
tucked	O
away	O
in	O
an	O
invisible	O
store	O
.	O
</s>
<s>
The	O
definition	O
of	O
constants	O
in	O
Verilog	B-Language
supports	O
the	O
addition	O
of	O
a	O
width	O
parameter	O
.	O
</s>
<s>
Verilog	B-Language
is	O
widely	O
considered	O
to	O
be	O
a	O
HDL	O
(	O
Hardware	O
Description	O
Language	O
)	O
.	O
</s>
<s>
There	O
are	O
several	O
statements	O
in	O
Verilog	B-Language
that	O
have	O
no	O
analog	O
in	O
real	O
hardware	O
,	O
e.g.	O
</s>
<s>
This	O
would	O
seem	O
to	O
imply	O
that	O
the	O
very	O
definition	O
of	O
the	O
Verilog	B-Language
language	O
in	O
general	O
needs	O
to	O
be	O
properly	O
recharacterized	O
.	O
</s>
<s>
The	O
next	O
interesting	O
structure	O
is	O
a	O
transparent	O
latch	B-General_Concept
;	O
it	O
will	O
pass	O
the	O
input	O
to	O
the	O
output	O
when	O
the	O
gate	O
signal	O
is	O
set	O
for	O
"	O
pass-through	O
"	O
,	O
and	O
captures	O
the	O
input	O
and	O
stores	O
it	O
upon	O
transition	O
of	O
the	O
gate	O
signal	O
to	O
"	O
hold	O
"	O
.	O
</s>
<s>
In	O
the	O
example	O
below	O
the	O
"	O
pass-through	O
"	O
level	O
of	O
the	O
gate	O
would	O
be	O
when	O
the	O
value	O
of	O
the	O
if	O
clause	O
is	O
true	O
,	O
i.e.	O
</s>
<s>
The	O
flip-flop	B-General_Concept
is	O
the	O
next	O
significant	O
template	O
;	O
in	O
Verilog	B-Language
,	O
the	O
D-flop	O
is	O
the	O
simplest	O
,	O
and	O
it	O
can	O
be	O
modeled	O
as	O
:	O
</s>
<s>
The	O
next	O
variant	O
is	O
including	O
both	O
an	O
asynchronous	O
reset	O
and	O
asynchronous	O
set	O
condition	O
;	O
again	O
the	O
convention	O
comes	O
into	O
play	O
,	O
i.e.	O
</s>
<s>
Note	O
:	O
If	O
this	O
model	O
is	O
used	O
to	O
model	O
a	O
Set/Reset	O
flip	B-General_Concept
flop	I-General_Concept
then	O
simulation	O
errors	O
can	O
result	O
.	O
</s>
<s>
This	O
condition	O
may	O
or	O
may	O
not	O
be	O
correct	O
depending	O
on	O
the	O
actual	O
flip	B-General_Concept
flop	I-General_Concept
.	O
</s>
<s>
In	O
a	O
real	O
flip	B-General_Concept
flop	I-General_Concept
this	O
will	O
cause	O
the	O
output	O
to	O
go	O
to	O
a	O
1	O
.	O
</s>
<s>
A	O
different	O
approach	O
may	O
be	O
necessary	O
for	O
set/reset	O
flip	B-General_Concept
flops	I-General_Concept
.	O
</s>
<s>
There	O
is	O
a	O
split	O
between	O
FPGA	B-Architecture
and	O
ASIC	O
synthesis	O
tools	O
on	O
this	O
structure	O
.	O
</s>
<s>
FPGA	B-Architecture
tools	O
allow	O
initial	O
blocks	O
where	O
reg	O
values	O
are	O
established	O
instead	O
of	O
using	O
a	O
"	O
reset	O
"	O
signal	O
.	O
</s>
<s>
The	O
reason	O
is	O
that	O
an	O
FPGA	B-Architecture
's	O
initial	O
state	O
is	O
something	O
that	O
is	O
downloaded	O
into	O
the	O
memory	O
tables	O
of	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
There	O
are	O
two	O
separate	O
ways	O
of	O
declaring	O
a	O
Verilog	B-Language
process	O
.	O
</s>
<s>
The	O
always	O
keyword	O
acts	O
similar	O
to	O
the	O
C	B-Language
language	I-Language
construct	O
while(1 )	O
 { .. } 	O
in	O
the	O
sense	O
that	O
it	O
will	O
execute	O
forever	O
.	O
</s>
<s>
The	O
fork/join	O
pair	O
are	O
used	O
by	O
Verilog	B-Language
to	O
create	O
parallel	O
processes	O
.	O
</s>
<s>
Notice	O
that	O
VHDL	B-Language
cannot	O
dynamically	O
spawn	O
multiple	O
processes	O
like	O
Verilog	B-Language
.	O
</s>
<s>
The	O
order	O
of	O
execution	O
is	O
n't	O
always	O
guaranteed	O
within	O
Verilog	B-Language
.	O
</s>
<s>
NOT	O
&&	O
AND	O
||	O
ORReduction	O
&	O
Reduction	O
AND	O
~	O
&	O
Reduction	O
NAND	O
|	O
Reduction	O
OR	O
~	O
|	O
Reduction	O
NOR	O
^	O
Reduction	O
XOR	O
~	O
^	O
or	O
^	O
~	O
Reduction	O
XNORArithmetic	O
+	O
Addition	O
-	O
Subtraction	O
-	O
2	O
's	O
complement	O
*	O
Multiplication	O
/	O
Division	O
**	O
Exponentiation	O
( *	O
Verilog-2001	O
)	O
Relational	O
>	O
Greater	O
than	O
<  Less than >=  Greater than or equal to <=  Less than or equal to ==  Logical equality (bit-value 1'bX is removed from comparison )  !=  Logical inequality (bit-value 1'bX is removed from comparison )  ===  4-state logical equality (bit-value 1'bX is taken as literal )  !==  4-state logical inequality (bit-value 1'bX is taken as literal )  Shift  >>  Logical right shift <<  Logical left shift >>>	O
Arithmetic	O
right	O
shift	O
( *	O
Verilog-2001	O
)	O
<<<	O
Arithmetic	O
left	O
shift	O
( *	O
Verilog-2001	O
)	O
Concatenation	O
{	O
,	O
}	O
Concatenation	O
Replication	O
 { n { m }  } 	O
Replicate	O
value	O
m	O
for	O
n	O
times	O
Conditional	O
?	O
</s>
<s>
The	O
IEEE	B-Language
1364	I-Language
standard	O
defines	O
a	O
four-valued	B-Language
logic	I-Language
with	O
four	O
states	O
:	O
0	O
,	O
1	O
,	O
Z	O
(	O
high	O
impedance	O
)	O
,	O
and	O
X	O
(	O
unknown	O
logic	O
value	O
)	O
.	O
</s>
<s>
For	O
the	O
competing	O
VHDL	B-Language
,	O
a	O
dedicated	O
standard	O
for	O
multi-valued	O
logic	O
exists	O
as	O
IEEE	O
1164	O
with	O
nine	O
levels	O
.	O
</s>
<s>
The	O
PLI	O
provides	O
a	O
programmer	O
with	O
a	O
mechanism	O
to	O
transfer	O
control	O
from	O
Verilog	B-Language
to	O
a	O
program	O
function	O
written	O
in	O
C	B-Language
language	I-Language
.	O
</s>
<s>
It	O
is	O
officially	O
deprecated	B-General_Concept
by	O
IEEE	O
Std	O
1364-2005	O
in	O
favor	O
of	O
the	O
newer	O
Verilog	B-Language
Procedural	O
Interface	O
,	O
which	O
completely	O
replaces	O
the	O
PLI	O
.	O
</s>
<s>
The	O
PLI	O
(	O
now	O
VPI	O
)	O
enables	O
Verilog	B-Language
to	O
cooperate	O
with	O
other	O
programs	O
written	O
in	O
the	O
C	B-Language
language	I-Language
such	O
as	O
test	O
harnesses	O
,	O
instruction	B-Application
set	I-Application
simulators	I-Application
of	O
a	O
microcontroller	B-Architecture
,	O
debuggers	B-Application
,	O
and	O
so	O
on	O
.	O
</s>
<s>
For	O
example	O
,	O
it	O
provides	O
the	O
C	B-Language
functions	O
tf_putlongp( )	O
and	O
tf_getlongp( )	O
which	O
are	O
used	O
to	O
write	O
and	O
read	O
the	O
argument	O
of	O
the	O
current	O
Verilog	B-Language
task	O
or	O
function	O
,	O
respectively	O
.	O
</s>
<s>
For	O
information	O
on	O
Verilog	B-Language
simulators	O
,	O
see	O
the	O
list	B-Algorithm
of	I-Algorithm
Verilog	I-Algorithm
simulators	I-Algorithm
.	O
</s>
