<s>
Verilog-to-Routing	B-Algorithm
(	O
VTR	O
)	O
is	O
an	O
open	O
source	O
CAD	B-Application
flow	O
for	O
FPGA	B-Architecture
devices	O
.	O
</s>
<s>
VTR	O
's	O
main	O
purpose	O
is	O
to	O
map	O
a	O
given	O
circuit	O
described	O
in	O
Verilog	B-Language
,	O
a	O
Hardware	O
Description	O
Language	O
,	O
on	O
a	O
given	O
FPGA	B-Architecture
architecture	O
for	O
research	O
and	O
development	O
purposes	O
;	O
the	O
FPGA	B-Architecture
architecture	O
targeted	O
could	O
be	O
a	O
novel	O
architecture	O
that	O
a	O
researcher	O
wishes	O
to	O
explore	O
,	O
or	O
it	O
could	O
be	O
an	O
existing	O
commercial	O
FPGA	B-Architecture
whose	O
architecture	O
has	O
been	O
captured	O
in	O
the	O
VTR	O
input	O
format	O
.	O
</s>
<s>
Additional	O
contributors	O
include	O
Google	B-Application
,	O
The	O
University	O
of	O
Utah	O
,	O
Princeton	O
University	O
,	O
Altera	O
,	O
Intel	O
,	O
Texas	O
Instruments	O
,	O
and	O
MIT	O
Lincoln	O
Lab	O
.	O
</s>
<s>
The	O
VTR	O
design	O
flow	O
usually	O
consists	O
of	O
three	O
main	O
component	O
applications	O
:	O
ODIN	O
II	O
which	O
compiles	O
Verilog	B-Language
code	O
to	O
a	O
circuit	O
in	O
Berkeley	O
Logic	O
Interchange	O
Format	O
(	O
BLIF	O
)	O
,	O
a	O
human-readable	O
graph	O
representation	O
of	O
the	O
circuit	O
;	O
ABC	O
which	O
optimizes	O
the	O
BLIF	O
circuit	O
produced	O
by	O
ODIN	O
II	O
;	O
and	O
VPR	O
which	O
packs	O
,	O
places	O
and	O
routes	B-Algorithm
the	O
optimized	O
circuit	O
on	O
the	O
given	O
FPGA	B-Architecture
architecture	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
FASM	O
FPGA	B-Architecture
Assembly	O
tool	O
can	O
produce	O
programming	O
bitstreams	O
for	O
some	O
commercial	O
FPGAs	B-Architecture
(	O
Xilinx	O
Artix	O
and	O
Lattice	O
ice40	O
)	O
at	O
the	O
end	O
of	O
the	O
VTR	O
flow	O
,	O
while	O
the	O
OpenFPGA	O
tool	O
integrates	O
with	O
VTR	O
to	O
produce	O
a	O
standard	O
cell	O
layout	O
of	O
a	O
novel	O
(	O
proposed	O
)	O
FPGA	B-Architecture
.	O
</s>
<s>
It	O
is	O
also	O
possible	O
to	O
use	O
different	O
tools	O
for	O
the	O
first	O
(	O
HDL	O
synthesis	O
)	O
stage	O
of	O
the	O
VTR	O
flow	O
;	O
for	O
example	O
the	O
Titan	O
Flow	O
uses	O
Quartus	O
to	O
perform	O
the	O
HDL	O
to	O
logic	O
synthesis	O
stage	O
,	O
and	O
then	O
VPR	O
to	O
perform	O
placement	O
and	O
routing	B-Algorithm
,	O
while	O
uses	O
the	O
synthesis	O
tool	O
followed	O
by	O
VPR	O
placement	O
and	O
routing	B-Algorithm
.	O
</s>
<s>
It	O
transforms	O
a	O
given	O
Verilog	B-Language
code	O
to	O
a	O
BLIF	O
circuit	O
,	O
performs	O
code	O
and	O
circuit	O
optimizations	O
,	O
visualizes	O
circuits	O
,	O
and	O
performs	O
partial	O
mapping	O
of	O
logic	O
to	O
available	O
hard	O
blocks	O
of	O
the	O
given	O
architecture	O
.	O
</s>
<s>
Its	O
input	O
is	O
a	O
BLIF	O
circuit	O
,	O
which	O
it	O
packs	O
,	O
places	O
and	O
routes	B-Algorithm
on	O
an	O
input	O
FPGA	B-Architecture
architecture	O
.	O
</s>
<s>
During	O
packing	O
,	O
neighboring	O
and	O
related	O
logic	O
elements	O
of	O
the	O
circuit	O
are	O
clustered	O
together	O
into	O
Logic	O
Blocks	O
matching	O
the	O
hardware	O
of	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
During	O
placement	O
,	O
these	O
logic	O
blocks	O
as	O
well	O
as	O
hard	O
blocks	O
are	O
assigned	O
to	O
the	O
available	O
hardware	O
resources	O
of	O
the	O
FPGA	B-Architecture
.	O
</s>
<s>
Finally	O
,	O
during	O
routing	B-Algorithm
the	O
signal	O
connections	O
between	O
blocks	O
are	O
made	O
.	O
</s>
<s>
The	O
FPGA	B-Architecture
Assembly	O
(	O
genfasm	O
)	O
tool	O
will	O
produce	O
a	O
programming	O
bitstream	O
from	O
a	O
VTR	O
implementation	O
(	O
placement	O
and	O
routing	B-Algorithm
of	O
a	O
circuit	O
)	O
on	O
commercial	O
architectures	O
for	O
which	O
complete	O
VTR	O
architecture	O
files	O
describing	O
the	O
FPGA	B-Architecture
device	O
have	O
been	O
produced	O
.	O
</s>
<s>
Currently	O
this	O
includes	O
the	O
Xilinx	O
Artix	O
and	O
Lattice	O
ice40	O
FPGA	B-Architecture
families	O
.	O
</s>
<s>
This	O
tool	O
is	O
primarily	O
developed	O
by	O
Google	B-Application
.	I-Application
</s>
