<s>
Verilog-AMS	B-Language
is	O
a	O
derivative	O
of	O
the	O
Verilog	B-Language
hardware	O
description	O
language	O
that	O
includes	O
analog	O
and	O
mixed-signal	O
extensions	O
(	O
AMS	O
)	O
in	O
order	O
to	O
define	O
the	O
behavior	O
of	O
analog	O
and	O
mixed-signal	O
systems	O
.	O
</s>
<s>
It	O
extends	O
the	O
event-based	O
simulator	O
loops	O
of	O
Verilog/SystemVerilog/VHDL	O
,	O
by	O
a	O
continuous-time	O
simulator	O
,	O
which	O
solves	O
the	O
differential	O
equations	O
in	O
analog-domain	O
.	O
</s>
<s>
The	O
Verilog-AMS	B-Language
standard	O
was	O
created	O
with	O
the	O
intent	O
of	O
enabling	O
designers	O
of	O
analog	O
and	O
mixed	O
signal	O
systems	O
and	O
integrated	O
circuits	O
to	O
create	O
and	O
use	O
modules	O
that	O
encapsulate	O
high-level	O
behavioral	O
descriptions	O
as	O
well	O
as	O
structural	O
descriptions	O
of	O
systems	O
and	O
components	O
.	O
</s>
<s>
Verilog-AMS	B-Language
is	O
an	O
industry	O
standard	O
modeling	O
language	O
for	O
mixed	O
signal	O
circuits	O
.	O
</s>
<s>
Verilog	B-Language
and	O
Verilog/AMS	O
are	O
not	O
procedural	O
programming	O
languages	O
,	O
but	O
event-based	O
hardware	O
description	O
languages	O
(	O
HDLs	O
)	O
.	O
</s>
<s>
However	O
,	O
Verilog/AMS	O
can	O
be	O
coupled	O
with	O
procedural	O
languages	O
like	O
the	O
ANSI	O
C	O
language	O
using	O
the	O
Verilog	B-Language
Procedural	O
Interface	O
of	O
the	O
simulator	O
,	O
which	O
eases	O
testsuite	O
implementation	O
,	O
and	O
allows	O
interaction	O
with	O
legacy	O
code	O
or	O
testbench	O
equipment	O
.	O
</s>
<s>
The	O
original	O
intention	O
of	O
the	O
Verilog-AMS	B-Language
committee	O
was	O
a	O
single	O
language	O
for	O
both	O
analog	O
and	O
digital	O
design	O
,	O
however	O
due	O
to	O
delays	O
in	O
the	O
merger	O
process	O
it	O
remains	O
at	O
Accellera	O
while	O
Verilog	B-Language
evolved	O
into	O
SystemVerilog	B-Language
and	O
went	O
to	O
the	O
IEEE	O
.	O
</s>
<s>
Verilog/AMS	O
is	O
a	O
superset	O
of	O
the	O
Verilog	B-Language
digital	O
HDL	O
,	O
so	O
all	O
statements	O
in	O
digital	O
domain	O
work	O
as	O
in	O
Verilog	B-Language
(	O
see	O
there	O
for	O
examples	O
)	O
.	O
</s>
<s>
All	O
analog	O
parts	O
work	O
as	O
in	O
Verilog-A	B-Language
.	O
</s>
<s>
The	O
following	O
code	O
example	O
in	O
Verilog-AMS	B-Language
shows	O
a	O
DAC	O
which	O
is	O
an	O
example	O
for	O
analog	O
processing	O
which	O
is	O
triggered	O
by	O
a	O
digital	O
signal	O
:	O
</s>
<s>
While	O
the	O
language	O
was	O
initially	O
only	O
supported	O
by	O
commercial	O
companies	O
,	O
a	O
"	O
Verilog-A	B-Language
"	O
subset	O
was	O
adopted	O
by	O
the	O
transistor-modeling	O
community	O
through	O
ADMS	O
,	O
which	O
works	O
for	O
open-source	O
simulators	O
like	O
Xyce	O
and	O
ngSPICE	O
.	O
</s>
