<s>
Verilog-A	B-Language
is	O
an	O
industry	O
standard	O
modeling	O
language	O
for	O
analog	O
circuits	O
.	O
</s>
<s>
It	O
is	O
the	O
continuous-time	O
subset	O
of	O
Verilog-AMS	B-Language
.	O
</s>
<s>
A	O
few	O
commercial	O
applications	O
may	O
export	O
MEMS	B-General_Concept
designs	O
in	O
Verilog-A	B-Language
format	O
.	O
</s>
<s>
Verilog-A	B-Language
was	O
created	O
out	O
of	O
a	O
need	O
to	O
standardize	O
the	O
Spectre	B-Algorithm
behavioral	O
language	O
in	O
face	O
of	O
competition	O
from	O
VHDL	B-Language
(	O
an	O
IEEE	O
standard	O
)	O
,	O
which	O
was	O
absorbing	O
analog	O
capability	O
from	O
other	O
languages	O
(	O
e.g.	O
</s>
<s>
Open	O
Verilog	B-Language
International	O
(	O
OVI	O
,	O
the	O
body	O
that	O
originally	O
standardized	O
Verilog	B-Language
)	O
agreed	O
to	O
support	O
the	O
standardization	O
,	O
provided	O
that	O
it	O
was	O
part	O
of	O
a	O
plan	O
to	O
create	O
Verilog-AMS	B-Language
a	O
single	O
language	O
covering	O
both	O
analog	O
and	O
digital	O
design	O
.	O
</s>
<s>
Verilog-A	B-Language
was	O
an	O
all-analog	O
subset	O
of	O
Verilog-AMS	B-Language
that	O
was	O
the	O
first	O
phase	O
of	O
the	O
project	O
.	O
</s>
<s>
There	O
was	O
considerable	O
delay	O
(	O
possibly	O
procrastination	O
)	O
between	O
the	O
first	O
Verilog-A	B-Language
language	B-Language
reference	I-Language
manual	I-Language
and	O
the	O
full	O
Verilog-AMS	B-Language
,	O
and	O
in	O
that	O
time	O
Verilog	B-Language
moved	O
to	O
the	O
IEEE	O
,	O
leaving	O
Verilog-AMS	B-Language
behind	O
at	O
Accellera	O
.	O
</s>
<s>
Verilog-A	B-Language
standard	O
does	O
not	O
exist	O
stand-alone	O
-	O
it	O
is	O
part	O
of	O
the	O
complete	O
Verilog-AMS	B-Language
standard	O
.	O
</s>
<s>
However	O
,	O
the	O
initial	O
and	O
subsequent	O
releases	O
can	O
be	O
found	O
,	O
with	O
what	O
will	O
probably	O
be	O
the	O
final	O
release	O
since	O
future	O
work	O
will	O
leverage	O
the	O
new	O
net-type	O
capabilities	O
in	O
SystemVerilog	B-Language
.	O
</s>
<s>
Built-in	O
types	O
like	O
"	O
wreal	O
"	O
in	O
Verilog-AMS	B-Language
will	O
become	O
user-defined	O
types	O
in	O
SystemVerilog	B-Language
more	O
in	O
line	O
with	O
the	O
VHDL	B-Language
methodology	O
.	O
</s>
<s>
A	O
subset	O
of	O
Verilog-A	B-Language
can	O
be	O
translated	O
automatically	O
to	O
the	O
C	B-Language
programming	I-Language
language	I-Language
using	O
the	O
Automatic	O
Device	O
Model	O
Synthesizer	O
(	O
ADMS	B-Algorithm
)	O
.	O
</s>
<s>
This	O
feature	O
is	O
used	O
for	O
example	O
to	O
translate	O
the	O
BSIM	B-Algorithm
Verilog-A	B-Language
transistor	O
models	O
,	O
which	O
are	O
no	O
more	O
released	O
in	O
C	B-Language
,	O
for	O
use	O
in	O
simulators	O
like	O
ngspice	B-Algorithm
.	O
</s>
<s>
This	O
first	O
example	O
gives	O
a	O
first	O
demonstration	O
of	O
modeling	O
in	O
Verilog-A	B-Language
:	O
</s>
<s>
This	O
Verilog-AMS	B-Language
example	O
implements	O
an	O
ideal	O
diode	O
,	O
by	O
defining	O
the	O
current	O
through	O
the	O
branch	O
(	O
a	O
,	O
c	B-Language
)	O
depending	O
on	O
voltage	O
at	O
branch	O
terminals	O
(	O
a	O
)	O
,	O
(	O
c	B-Language
)	O
,	O
and	O
the	O
ambient	O
temperature	O
of	O
the	O
simulated	O
circuit	O
:	O
</s>
