<s>
Verilator	B-Application
is	O
a	O
free	B-License
and	I-License
open-source	I-License
software	I-License
tool	O
which	O
converts	O
Verilog	B-Language
(	O
a	O
hardware	O
description	O
language	O
)	O
to	O
a	O
cycle-accurate	B-Application
behavioral	I-Application
model	I-Application
in	O
C++	B-Language
or	O
SystemC	B-Language
.	O
</s>
<s>
Verilator	B-Application
is	O
now	O
used	O
within	O
academic	O
research	O
,	O
open	O
source	O
projects	O
and	O
for	O
commercial	O
semiconductor	O
development	O
.	O
</s>
<s>
It	O
is	O
part	O
of	O
the	O
growing	O
body	O
of	O
free	B-Algorithm
EDA	I-Algorithm
software	I-Algorithm
.	O
</s>
<s>
Verilator	B-Application
has	O
seen	O
its	O
widest	O
adoption	O
in	O
the	O
academic	O
and	O
open	O
source	O
communities	O
.	O
</s>
<s>
Researchers	O
have	O
used	O
Verilator	B-Application
to	O
develop	O
new	O
co-simulation	O
environments	O
,	O
as	O
part	O
of	O
general	O
ASIC	O
and	O
FPGA	B-Architecture
design	O
flows	O
and	O
in	O
performance	O
and	O
power	O
analysis	O
.	O
</s>
<s>
Verilator	B-Application
is	O
also	O
a	O
popular	O
tool	O
for	O
student	O
dissertations	O
,	O
for	O
example	O
.	O
</s>
<s>
Verilator	B-Application
is	O
an	O
open	O
source	O
tool	O
,	O
and	O
has	O
in	O
turn	O
been	O
adopted	O
by	O
a	O
number	O
of	O
other	O
projects	O
.	O
</s>
<s>
The	O
Fedora	O
Electronic	O
Lab	O
has	O
adopted	O
Verilator	B-Application
as	O
part	O
of	O
its	O
open	O
source	O
design	O
flow	O
for	O
Fedora	O
11	O
.	O
</s>
<s>
The	O
OpenRISC	B-Device
architecture	O
from	O
OpenCores	O
includes	O
a	O
cycle	O
accurate	O
reference	O
model	O
,	O
generated	O
from	O
Verilog	B-Language
using	O
Verilator	B-Application
.	O
</s>
<s>
A	O
recent	O
paper	O
described	O
how	O
the	O
regression	O
test	O
suite	O
for	O
GCC	B-Application
could	O
be	O
run	O
against	O
a	O
Verilator	B-Application
model	O
of	O
the	O
OpenRISC	B-Device
1200	O
as	O
a	O
way	O
of	O
detecting	O
errors	O
in	O
the	O
Verilog	B-Language
RTL	O
implementation	O
.	O
</s>
<s>
TestDrive	O
Profiling	O
Master	O
tool	O
provides	O
the	O
virtual	O
FPGA	B-Architecture
environment	O
using	O
Verilator	B-Application
.	O
</s>
<s>
Their	O
use	O
of	O
Verilator	B-Application
is	O
becoming	O
more	O
widespread	O
,	O
for	O
example	O
within	O
application	O
notes	O
.	O
</s>
<s>
More	O
recently	O
Art	O
of	O
Silicon	O
have	O
described	O
their	O
use	O
of	O
Verilator	B-Application
on	O
a	O
farm	O
of	O
Linux	B-Application
processors	O
as	O
a	O
route	O
to	O
faster	O
regression	O
testing	O
of	O
their	O
commercial	O
designs	O
.	O
</s>
<s>
The	O
current	O
maintainer	O
of	O
Verilator	B-Application
identified	O
27	O
companies	O
and	O
universities	O
who	O
had	O
reported	O
use	O
of	O
Verilator	B-Application
or	O
contributed	O
to	O
its	O
development	O
,	O
including	O
Intel	O
,	O
Arm	O
,	O
CSR	O
,	O
Broadcom	O
,	O
Raytheon	O
,	O
Infineon	O
,	O
Stanford	O
University	O
,	O
Imperial	O
College	O
London	O
and	O
Embecosm	O
.	O
</s>
<s>
Verilator	B-Application
's	O
user	O
manual	O
provides	O
a	O
short	O
history	O
.	O
</s>
<s>
It	O
was	O
used	O
to	O
convert	O
Verilog	B-Language
code	O
to	O
C	O
for	O
co-simulation	O
with	O
a	O
C	O
based	O
CPU	O
model	O
of	O
the	O
Alpha	O
processor	O
.	O
</s>
<s>
A	O
SystemC	B-Language
mode	O
was	O
added	O
and	O
the	O
tool	O
rewritten	O
from	O
scratch	O
in	O
C++	B-Language
,	O
leading	O
to	O
an	O
increase	O
in	O
performance	O
.	O
</s>
<s>
In	O
2022	O
Verilator	B-Application
Version	O
5	O
added	O
an	O
IEEE-compliant	O
scheduler	O
and	O
delay	O
semantics	O
,	O
relaxing	O
previous	O
restrictions	O
that	O
ignored	O
all	O
delays	O
.	O
</s>
<s>
Verilator	B-Application
converts	O
Verilog	B-Language
to	O
C++	B-Language
or	O
SystemC	B-Language
.	O
</s>
<s>
It	O
can	O
handle	O
all	O
versions	O
of	O
Verilog	B-Language
and	O
also	O
some	O
SystemVerilog	O
assertions	O
.	O
</s>
<s>
A	O
C++	B-Language
class	O
is	O
generated	O
with	O
a	O
function	O
which	O
takes	O
2-state	O
values	O
on	O
input	O
ports	O
and	O
advance	O
them	O
to	O
values	O
on	O
output	O
ports	O
at	O
the	O
next	O
clock	O
edge	O
.	O
</s>
<s>
SystemC	B-Language
is	O
supported	O
by	O
providing	O
a	O
wrapper	O
class	O
using	O
SystemC	B-Language
ports	O
and	O
with	O
sensitivity	O
to	O
the	O
clock(s )	O
,	O
which	O
will	O
drive	O
the	O
ports	O
of	O
the	O
underlying	O
C++	B-Language
model	O
.	O
</s>
<s>
Verilator	B-Application
supports	O
automatically	O
partitioning	O
designs	O
into	O
multiple	O
threads	O
,	O
also	O
potentially	O
improving	O
performance	O
.	O
</s>
<s>
Verilator	B-Application
converts	O
synthesizable	O
Verilog	B-Language
to	O
C++	B-Language
,	O
while	O
C++	B-Language
library	O
could	O
be	O
compiled	O
into	O
a	O
MEX	B-Operating_System
file	I-Operating_System
using	O
MATLAB	O
interface	O
to	O
C++	B-Language
.	O
</s>
<s>
This	O
is	O
how	O
Verilog	B-Language
designs	O
can	O
be	O
directly	O
simulated	O
from	O
MATLAB	O
.	O
</s>
<s>
Using	O
compiled	O
C++	B-Language
models	O
with	O
MATLAB	O
is	O
faster	O
than	O
using	O
co-simulation	O
interfaces	O
with	O
a	O
separate	O
HDL	B-Algorithm
simulator	I-Algorithm
.	O
</s>
<s>
There	O
is	O
an	O
open-source	O
project	O
called	O
that	O
compiles	O
Verilog	B-Language
into	O
a	O
MEX	B-Operating_System
file	I-Operating_System
using	O
Verilator	B-Application
and	O
provides	O
a	O
set	O
of	O
functions	O
for	O
model	O
simulation	O
from	O
MATLAB	O
.	O
</s>
