<s>
In	O
computer	B-General_Concept
science	I-General_Concept
,	O
a	O
vectored	B-Architecture
interrupt	I-Architecture
is	O
a	O
processing	O
technique	O
in	O
which	O
the	O
interrupting	B-Application
device	O
directs	O
the	O
processor	O
to	O
the	O
appropriate	O
interrupt	B-General_Concept
service	I-General_Concept
routine	I-General_Concept
.	O
</s>
<s>
This	O
is	O
in	O
contrast	O
to	O
a	O
polled	B-General_Concept
interrupt	I-General_Concept
system	O
,	O
in	O
which	O
a	O
single	O
interrupt	B-General_Concept
service	I-General_Concept
routine	I-General_Concept
must	O
determine	O
the	O
source	O
of	O
the	O
interrupt	B-Application
by	O
checking	O
all	O
potential	O
interrupt	B-Application
sources	O
,	O
a	O
slow	O
and	O
relatively	O
laborious	O
process	O
.	O
</s>
<s>
Vectored	B-Architecture
interrupts	I-Architecture
are	O
achieved	O
by	O
assigning	O
each	O
interrupting	B-Application
device	O
a	O
unique	O
code	O
,	O
typically	O
four	O
to	O
eight	O
bits	O
in	O
length	O
.	O
</s>
<s>
When	O
a	O
device	O
interrupts	B-Application
,	O
it	O
sends	O
its	O
unique	O
code	O
over	O
the	O
data	B-General_Concept
bus	I-General_Concept
to	O
the	O
processor	O
,	O
telling	O
the	O
processor	O
which	O
interrupt	B-General_Concept
service	I-General_Concept
routine	I-General_Concept
to	O
execute	O
.	O
</s>
